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Title:
AMPLIFIER CIRCUIT WITH TUNABLE PEAKING
Document Type and Number:
WIPO Patent Application WO/2022/058011
Kind Code:
A1
Abstract:
An amplifier circuit (100A) includes a first cascode circuit (102A) and a second cascode circuit (102B). The first cascode circuit (102A) includes a first input transistor (104) and a first output transistor (106). The second cascode circuit (102B) includes a second input transistor (108) and a second output transistor (110). The amplifier circuit (100A) further includes a variable resistor (126) and a capacitor (128) connected in series between a first node (112) and a second node (118). Each of the first and second input and output transistors (104, 106, 108, 110) are Gallium-Arsenide field effect transistors. The amplifier circuit (100A) enables tunable peaking by use of the variable resistor (126) and the capacitor (128)..

Inventors:
PIAZZON LUCA (DE)
MUSIO ANTONIO (DE)
Application Number:
PCT/EP2020/075925
Publication Date:
March 24, 2022
Filing Date:
September 17, 2020
Export Citation:
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Assignee:
HUAWEI TECH CO LTD (CN)
PIAZZON LUCA (DE)
International Classes:
H03F3/45; H03F1/42; H03F3/193; H03F3/24; H03G1/00; H03G3/30
Foreign References:
US20050248396A12005-11-10
Other References:
LI DAN ET AL: "A Low-Noise Design Technique for High-Speed CMOS Optical Receivers", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 49, no. 6, 28 May 2014 (2014-05-28), pages 1437 - 1447, XP011549324, ISSN: 0018-9200, [retrieved on 20140528], DOI: 10.1109/JSSC.2014.2322868
YUNZHI DONG ET AL: "A High-Speed Fully-Integrated POF Receiver With Large-Area Photo Detectors in 65 nm CMOS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 47, no. 9, 21 August 2012 (2012-08-21), pages 2080 - 2092, XP011457918, ISSN: 0018-9200, DOI: 10.1109/JSSC.2012.2200529
RUI TAO ET AL: "Monolithically integrated 5 Gb/s CMOS duobinary transmitter for optical communication systems", RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, 2004. DIGEST OF PAPERS. 2004 IEEE FORT WORTH, TX, USA JUNE 6-8, 2004, PISCATAWAY, NJ, USA,IEEE, 6 June 2004 (2004-06-06), pages 21 - 24, XP010713996, ISBN: 978-0-7803-8333-3, DOI: 10.1109/RFIC.2004.1320513
Attorney, Agent or Firm:
KREUZ, Georg (DE)
Download PDF:
Claims:
CLAIMS

1. An amplifier circuit (100A-1 OOF) comprising: a) a first cascode circuit (102A) comprising: a first input transistor (104) having a gate (104A), a source (104B) and a drain (104C), and configured to be driven by a first signal (111) applied at its gate (104A), and a first output transistor (106) having a gate (106A), a source (106B) and a drain (106C), and connected in series through its source (106B) with the drain (104C) of the first input transistor (104) via a first node (112) so as to be driven by said first input transistor (104) and to deliver a first output signal (114) through the drain (106C) of the first output transistor (106), and b) a second cascode circuit (102B) comprising: a second input transistor (108) having a gate (108A), a source (108B) and a drain (108C), and configured to be driven by a second signal (116) applied at its gate (108A), and a second output transistor (110) having a gate, (110A) a source (110B) and a drain (110C), and connected in series through its source (110B) with the drain (108C) of the second input transistor (108) via a second node (118) so as to be driven by said second input transistor (108) and to deliver a second output signal (120) through the drain (110C) of the second output transistor (110), wherein the gate (106A) of the first output transistor (106) and the gate (110A) of the second output transistor (110) are connected together, the drain (106C) of the first output transistor (106) and the drain (110C) of the second output transistor (110) are connected together through a first resistor-inductor circuit (122) and a second resistor-inductor circuit (124), and the source (104B) of the first input transistor (104) and the source (108B) of the second input transistor (108) are connected together, the first (104) and second input transistors (108), the first (106) and second output transistors (110) and the first resistor-inductor circuit (122) and second resistor-inductor circuit (124) forming a cascode differential pair, and the amplifier circuit (100A-100F) further comprising a variable resistor (126) and a capacitor (128) connected in series between the first node (112) and the second node (118).

2. An amplifier circuit (100A-100F) according to claim 1 , wherein the variable resistor (126) comprises one or more first controllable transistors (142A-142N) each having a drain connected to the capacitor (128), a source connected to the first node (112), and a gate controllable by a control voltage signal distinct of the control voltage signals to control the gates of the other first controllable transistors.

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3. An amplifier circuit (100A-100F) according to any of claims 1 and 2, wherein the variable resistor (126) comprises one or more second controllable transistors each having a drain connected to the capacitor (128), a source connected to the second node (118), and a gate controllable by a control voltage signal distinct of the control voltage signals to control the gates of the other second controllable transistors.

4. An amplifier circuit (100A-100F) according to claim 3, wherein the respective gates (136A, 140A) of at least one of the first controllable transistors (136) and at least one of the second controllable transistors (140) are connected together so as to be controllable by the same control voltage signal (138).

5. An amplifier circuit (100A-100F) according to any of claims 1 to 4, wherein it comprises a first voltage source connecting point , to be connected to a first voltage source (134), between the first (122) and the second resistor-inductor circuits (124).

6. An amplifier circuit (100A-100F) according to any of claims 1 to 5, wherein it comprises a second voltage source connecting point , to be connected to a second voltage source (132), between the respective gates (106A, 110A) of the first (106) and second output transistors (110).

7. An amplifier circuit (100A-100F) according to any of claims 1 to 6, wherein it comprises a resistor (130) connected to the ground and between the respective source (104B, 108B) of the first (104) and second input transistors (108).

8. An amplifier circuit (100A-100F) according to any of claims 1 to 7, wherein each of the first and second input and output transistors (104, 106, 108, and 110) and each of the first and second controllable transistors are Gallium-Arsenide field effect transistors.

9. A transmitter (600) for optical communication comprising a digital source (602), an amplifier circuit (100A-100F, 604) according to any of claims 1 to 8, and an electro-optical modulator (606), the digital source (602) being connected to the amplifier circuit (100A-100F, 604) so as to provide a digital signal (608) to the amplifier circuit (100A-100F, 604), the amplifier circuit (100A-100F, 604) being connected to the electro-optical modulator (606) so as to amplify a received digital signal (608) by increasing its power level and to transmit the amplified signal (610) to the electro- optical modulator (606), the electro-optical modulator (606) being configured to transduce a received amplified signal (610) to an optical signal (612) due to be transferred into an optical communication line.

Description:
AMPLIFIER CIRCUIT WITH TUNABLE PEAKING

TECHNICAL FIELD

The present disclosure relates generally to the field of ultra-wideband amplifiers for optical communication; and more specifically to an amplifier circuit based on a Gallium Arsenide (GaAs) technology with a tunable peaking feature.

BACKGROUND

Generally, transmitters used for high speed optical communications are implemented by cascading a digital source, a conventional amplifier, and an electro-optical modulator. The conventional amplifier (e.g. a driver amplifier) is typically used to increase a power level of an electrical signal which is generated by the digital source in order to provide an appropriate supply power to the electro-optical modulator. The electro-optical modulator is typically configured to transduce the electrical signal to an optical signal which is transferred via an optical fiber. Typically, the conventional amplifier (i.e. the driver amplifier) is required to achieve a high frequency peaking in order to compensate for high frequency losses which are introduced by the electro-optical modulator, package, and connection between various components of the electro-optical modulator. Each part of the electro-optical modulator is mathematically modelled, and despite of this, a final real bandwidth of the electro-optical modulator is difficult to predict. Moreover, different modules oriented for different applications and transmission standards, require different peaking amplitude and frequency.

Currently, certain attempts have been made to implement a conventional amplifier based on a Silicon-Germanium (SiGe) technology. For example, the conventional amplifier is typically implemented by using a variable resistor/capacitor (i.e. R/C) on a differential ground, a variable resistor (R), inductor (L), and a capacitor (C) (i.e. R/L/C) on an output side or a variable feedback, and is based on the silicon-germanium (SiGe) technology. However, there are limitations associated with each attempt, for example, the conventional amplifier with the variable R/C reduces a maximum available gain. Additionally, in the conventional amplifier with the variable R/L/C a direct current flows across variable inductors which results in a reliability risk. Also, the variable R/L/C constitute variable components on the output ports (or side) of the conventional amplifier and therefore, affect a gain roll-off of the conventional amplifier. Moreover, the conventional amplifier with the variable feedback increase a direct current (DC) power consumption in order to bias the variable feedback, causing a pulsating direct current (DC) and also faces stability issues due to limitation in a stability phase margin.

A Gallium Arsenide (GaAs) technology is found to be generally advantageous over the SiGe technology because GaAs devices are relatively insensitive to overheating, owing to wider energy band gap, and also tend to create less noise, especially at high frequencies due to high carrier mobilities and low resistive device parasitics. However, the conventional amplifier that either uses the variable R/C on the differential ground, or the variable R/L/C on the output side or the variable feedback, currently cannot be implemented using the GaAs technology. The reason is that the variable capacitor with a large value and enough variation range is not available based on the GaAs technology. Similarly, the variable inductor is also not available based on the GaAs technology. Moreover, due to large size of GaAs transistor and limited stackup metals, it is impractical to achieve a wideband feedback with enough stability phase margin. Thus, there exists a technical problem of an inefficient amplifier that fails to achieve a tunable peaking function when used in a conventional transmitter and not being implementable using the GaAs technology.

Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with the conventional amplifier, and the conventional transmitter that uses the conventional amplifier.

SUMMARY

The present disclosure seeks to provide an amplifier circuit based on a GaAs technology with a tunable peaking function. The present disclosure further seeks to provide a transmitter that uses the amplifier circuit and is suitable for use in an optical communication system for high data-rate applications. The present disclosure seeks to provide a solution to the existing problem of an inefficient amplifier that fails to achieve a tunable peaking function when used in a conventional transmitter and not being implementable using a Gallium Arsenide (GaAs) technology. An aim of the present disclosure is to provide a solution that overcomes at least partially the problems encountered in prior art, and provide an improved amplifier circuit with the tunable peaking function and implementable using the GaAs technology, which can be used as an ultra wideband amplifier in the optical communication system for high data-rate applications.

The object of the present disclosure is achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims. In one aspect, the present disclosure provides an amplifier circuit comprising a first cascode circuit. The first cascode circuit comprises a first input transistor (Q1) and a first output transistor (Q3). The first input transistor (Q1) has a gate, a source and a drain, and configured to be driven by a first signal (Vin+) applied at its gate. The first output transistor (Q3) has a gate, a source, and a drain, and connected in series through its source with the drain of the first input transistor (Q1) via a first node so as to be driven by the first input transistor (Q1) and to deliver a first output signal (Vout-) through the drain of the first output transistor (Q3). The amplifier circuit further comprises a second cascode circuit comprising a second input transistor (Q2) and a second output transistor (Q4). The second input transistor (Q2) has a gate, a source and a drain, and configured to be driven by a second signal (Vin-) applied at its gate. The second output transistor (Q4) has a gate, a source and a drain, and connected in series through its source with the drain of the second input transistor (Q2) via a second node so as to be driven by the second input transistor (Q2) and to deliver a second output signal (Vout+) through the drain of the second output transistor (Q4). The gate of the first output transistor (Q3) and the gate of the second output transistor (Q4) are connected together, the drain of the first output transistor (Q3) and the drain of the second output transistor (Q4) are connected together through a first resistor-inductor circuit (RL1, L1) and a second resistor-inductor circuit (RL2, L2), and the source of the first input transistor (Q1) and the source of the second input transistor (Q2) are connected together, the first and second input transistors (Q1 , Q2), the first and second output transistors (Q3, Q4) and the first and second resistor-inductor circuits ((RL1 , L1), (RL2, L2)) forming a cascode differential pair. The amplifier circuit further comprises a variable resistor (RVAR) and a capacitor (C) connected in series between the first node and the second node.

The amplifier circuit of the present disclosure does not require variable capacitors, variable inductors or a variable feedback circuitry for achieving tunable peaking function and thus can be easily implemented by use of the GaAs technology. The amplifier circuit of the present disclosure achieves a maximum available gain in a full operating frequency range. The disclosed amplifier circuit does not require direct currents flowing on variable components and consequently does not affect a gain roll-off owing to the variable components being isolated from the output ports by the first and the second output transistors (i.e. Q3) and (i.e. Q4). Additionally, the disclosed amplifier circuit does not increase DC power consumption with respect to a standard DC power consumption that is required to bias the differential cascode pair. The disclosed amplifier circuit is not susceptible to instability because the amplifier circuit does not introduce any closed loop in its circuit. Moreover, the disclosed amplifier circuit can be used for different electro-optical modulators such as indium phosphide (InP) mach-zehnder modulator (MZM) and silicon polymer (SiP) mach-zehnder modulator (MZM) because of the tunable peaking function.

In an implementation form, the variable resistor comprises one or more first controllable transistors (Q5, Q5i) each having a drain connected to the capacitor (C), a source connected to the first node, and a gate controllable by a control voltage signal (VT, VTi) distinct of the control voltage signals to control the gates of the other first controllable transistors (Q5i).

It is advantageous to have one or more first controllable transistors (Q5, Q5i) as the variable resistor as it is a simplest way to implement a low pass lossy filter. Further, the resistance offered by the one or more first controllable transistors (Q5, Q5i) can be controlled by use of the control voltage signal (VT, VTi).

In a further implementation form, the variable resistor (RVAR) comprises one or more second controllable transistors (Q6, Q6i) each having a drain connected to the capacitor (C), a source connected to the second node, and a gate controllable by a control voltage signal (VT) distinct of the control voltage signals to control the gates of the other second controllable transistors (Q6i).

It is advantageous to have one or more second controllable transistors (Q6, Q6i) as the variable resistor because of its simplicity. Further, the controllable transistors are digitally controlled transistors and can be controlled by use of the control voltage signal.

In a further implementation form, the respective gates of at least one of the first controllable transistors (Q5) and at least one of the second controllable transistors (Q6) are connected together so as to be controllable by the same control voltage signal (VT).

It is advantageous to control at least one of the first controllable transistors and at least one of the second controllable transistors by same control voltage signal so as to enable a differential symmetry in the amplifier circuit.

In a further implementation form, the amplifier circuit comprises a first voltage source connecting point (VDD), to be connected to a first voltage source, between the first and the second resistorinductor circuits ((RL1 , L1), (RL2, L2)).

It is advantageous to have the voltage source connecting point (VDD) to be connected to a first voltage source so that the inductors L1 and L2 of the first and second resistor-inductor circuits are used to pass a direct current (DC) bias current and block the radio frequency signals getting back into the power supply. Also, by connecting the first voltage source, between the first and the second resistor-inductor circuits ((RL1 , L1), (RL2, L2)), the first and second resistorinductor circuits together with the first and second input transistors (Q1, Q2), the first and second output transistors (Q3, Q4) form the cascode differential pair, and the cascode differential pair enable the amplifier circuit to achieve a high gain, and a high bandwidth.

In a further implementation form, the amplifier circuit comprises a second voltage source connecting point (VGG), to be connected to a second voltage source, between the respective gates of the first and second output transistors (Q3, Q4).

It is advantageous to have the second voltage source connecting point (VGG), to be connected to the second voltage source in order to provide a reference voltage in the amplifier circuit.

In a further implementation form, the amplifier circuit includes a resistor (Rs) connected to the ground and between the respective sources of the first and second input transistors (Q1, Q2).

It is advantageous to include the resistor (Rs), to limit an input bias current to the amplifier circuit, provide a safe baising voltage and improve common mode rejection.

In a further implementation form, each of the first and second input and output transistors (Q1 to Q4) and each of the first and second controllable transistors (Q5, Q5i, Q6, Q6i) are Gallium- Arsenide (GaAs) field effect transistors.

It is advantageous to have GaAs transistors to implement each of the first and second input and output transistors (Q1 to Q4) and each of the first and second controllable transistors (Q5, Q5i, Q6, Q6i) as the GaAs transistors offer several advantages over SiGe transistors. For example, GaAs transistors are relatively insensitive to overheating, owing to a wider energy band gap, and they also tend to create less noise, especially at high frequencies due to high carrier mobilities and low resistive device parasitics, thereby enabling tunable peaking with low noise at higher frequencies.

In another aspect, the present disclosure provides a transmitter for optical communication. The transmitter includes a digital source, an amplifier circuit of the present disclosure, and an electro-optical modulator. The digital source is connected to the amplifier circuit so as to provide a digital signal to the amplifier circuit. The amplifier circuit is connected to the electro- optical modulator so as to amplify a received digital signal by increasing its power level and to transmit the amplified signal to the electro-optical modulator. The electro-optical modulator is configured to transduce a received amplified signal to an optical signal to be transferred into an optical communication line. The transmitter achieves all the advantages and effects of the amplifier circuit of the present disclosure.

It has to be noted that all devices, elements, circuitry, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. It will be appreciated that features of the present disclosure are susceptible to being combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims.

Additional aspects, advantages, features and objects of the present disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations construed in conjunction with the appended claims that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.

Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein:

FIG. 1A is a circuit diagram of an amplifier circuit, in accordance with an embodiment of the present disclosure;

FIG. 1B depicts a low frequency equivalent circuit of an amplifier circuit, in accordance with an embodiment; FIG. 1C depicts a high frequency equivalent circuit of an amplifier circuit, in accordance with an embodiment;

FIG. 1 D is a circuit diagram of an amplifier circuit, in accordance with another embodiment of the present disclosure;

FIG. 1 E is a circuit diagram of an amplifier circuit, in accordance with yet another embodiment of the present disclosure;

FIG. 1 F is a circuit diagram of an amplifier circuit, in accordance with yet another embodiment of the present disclosure;

FIGs. 2A-2B illustrate an advantage of an amplifier circuit when compared to a conventional amplifier, in accordance with an embodiment of the present disclosure;

FIGs. 3A-3B illustrate another advantage of an amplifier circuit when compared to a conventional amplifier, in accordance with an embodiment of the present disclosure;

FIGs. 4A-4B illustrate yet another advantage of an amplifier circuit when compared to a conventional amplifier, in accordance with an embodiment of the present disclosure;

FIG. 5 depicts a graphical representation that illustrates a differential insertion loss of an amplifier circuit, in accordance with an exemplary scenario of the present disclosure; and

FIG. 6 is a block diagram that illustrates various exemplary components of a transmitter, in accordance with an embodiment of the present disclosure.

In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the nonunderlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.

DETAILED DESCRIPTION OF EMBODIMENTS

The following detailed description illustrates embodiments of the present disclosure and ways in which they can be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practicing the present disclosure are also possible. FIG. 1 A is a circuit diagram of an amplifier circuit in accordance with an embodiment of the present disclosure. With reference to FIG. 1A, there is shown a circuit architecture of an amplifier circuit 100A that includes a first cascode circuit 102A and a second cascode circuit 102B. The first cascode circuit 102A includes a first input transistor 104 (also represented by Q1) and a first output transistor 106 (also represented by Q3). The second cascode circuit 102B includes a second input transistor 108 (also represented by Q2) and a second output transistor 110 (also represented by Q4). Each of the first input transistor 104 (i.e. Q1), the first output transistor 106 (i.e. Q3), the second input transistor 108 (i.e. Q2) and the second output transistor 110 (i.e. Q4) includes a gate 104A, 106A, 108A and 110A, respectively, a source 104B, 106B, 108B and 110B, respectively and a drain 104C, 106C, 108C and 110C, respectively. The amplifier circuit 100A further includes a first signal 111 (also represented by Vin+), a first node 112 and a first output signal 114 (also represented by Vout-) in the first cascode circuit 102A. The amplifier circuit 100A further includes a second signal 116 (also represented by Vin-), a second node 118, and a second output signal 120 (also represented by Vout+) in the second cascode circuit 102B. The amplifier circuit 100A further includes a first resistor-inductor circuit 122 (also represented by RL1 , L1), a second resistor-inductor circuit 124 (also represented by RL2, L2), a variable resistor 126 (also represented by Rvar), a capacitor 128 (also represented by C), a resistor 130 (also represented by Rs), a second voltage source 132 (also represented by VGG) and a first voltage source 134 (also represented by VDD). The first resistor-inductor circuit 122 (i.e. RL1, L1) includes a first resistor 122A (i.e. RL1) and a first inductor 122B (i.e. L1). The second resistor-inductor circuit 124 (i.e. RL2, L2) includes a second resistor 124A (i.e. RL2) and second inductor 124B (i.e. L2). Each of first cascode circuit 102A, the second cascode circuit 102B, the first and second input and output transistors 104-110 (i.e. Q1-Q4), the first resistor-inductor circuit 122 (i.e. RL1, L1), the second resistor-inductor circuit 124 (i.e. RL2, L2), the second voltage source 132, and the first voltage source 134 is represented by a dashed rectangular box, which is used for illustration purpose only and do not form a part of circuitry.

The amplifier circuit 100A comprises the first cascode circuit 102A comprising the first input transistor 104 (i.e. Q1) having the gate 104A, the source 104B and the drain 104C, and configured to be driven by the first signal 111 (i.e. Vin+) applied at its gate 104A. The first cascode circuit 102A further comprises the first output transistor 106 (i.e. Q3) having the gate 106A, the source 106B and the drain 106C, and connected in series through its source 106B with the drain 104C of the first input transistor 104 (i.e. Q1) via the first node 112 so as to be driven by the first input transistor 104 (i.e. Q1) and to deliver the first output signal 114 (i.e. Vout-) through the drain 106C of the first output transistor 106 (i.e. Q3). The amplifier circuit 100A further comprises the second cascode circuit 102B that comprises the second input transistor 108 (i.e. Q2) having the gate 108A, the source 108B and the drain 108C, and configured to be driven by the second signal 116 (i.e. Vin-) applied at its gate 108A and the second output transistor 110 (i.e. Q4) having the gate 110A, the source 110B and the drain 110C, and connected in series through its source 110B with the drain 108C of the second input transistor 108 (i.e. Q2) via the second node 118 so as to be driven by the second input transistor 108 (i.e. Q2) and to deliver the second output signal 120 (i.e. Vout+) through the drain 110C of the second output transistor 110 (i.e. Q4).

The gate 106A of the first output transistor 106 (i.e. Q3) and the gate 110A of the second output transistor 110 (i.e. Q4) are connected together, the drain 106C of the first output transistor 106 (i.e. Q3) and the drain 110C of the second output transistor 110 (i.e. Q4) are connected together through the first resistor-inductor circuit 122 (i.e. RL1 , L1) and the second resistorinductor circuit 124 (i.e. RL2, L2), and the source 104B of the first input transistor 104 (i.e. Q1) and the source 108B of the second input transistor 108 (i.e. Q2) are connected together. The first and second input transistors 104 and 108 (i.e. Q1, Q2), the first and second output transistors 106 and 110 (i.e. Q3, Q4) and the first and second resistor-inductor circuits 122 and 124 (i.e. (RL1 , L1) and (RL2, L2)) together form a cascode differential pair.

The amplifier circuit 100A further comprises the variable resistor 126 (i.e. Rvar) and the capacitor 128 (i.e. C) connected in series between the first node 112 and the second node 118. The gate terminals 106A and 110A of the first output transistor 106 (i.e. Q3) and the second output transistor 110 (i.e. Q4), respectively, are powered by the second voltage source 132 (i.e. VGG) which is connected at the second voltage source connecting point in the amplifier circuit 100A. The drain terminals 106C and 110C of the first output transistor 106 (i.e. Q3) and the second output transistor 110 (i.e. Q4), respectively, are powered by the first voltage source 134 (i.e. VDD) which is connected at the first voltage source connecting point in the amplifier circuit 100A. The variable resistor 126 (i.e. Rvar) may also be denoted as RVAR.

In accordance with an embodiment, each of the first and second input and output transistors 104 -110 (i.e. Q1 to Q4) and each of the first and second controllable transistors (e.g. Q5, Q5i, Q6, Q6i) are Gallium-Arsenide field effect transistors. The reason is that the GaAs field effect transistors are relatively insensitive to overheating, owing to wider energy band gap, and also tend to create less noise, especially at high frequencies due to high carrier mobilities and low resistive device parasitics, thereby enabling tunable peaking function with low noise at higher frequencies. In this embodiment, a high frequency peaking generated by the first and second resistorinductor circuits 122 (i.e. RL1 , L1), and 124 (i.e. RL2, L2) can be varied by varying the resistance value of the variable resistor 126 (i.e. Rvar). A simplified gain function (i.e. G) of the amplifier circuit 100A is given by the equation (equation 1) where gm is a measure of the transconductance of the amplifier circuit 100A and w is the angular frequency.

In accordance with an embodiment, the variable resistor 126 (i.e. Rvar) comprises one or more first controllable transistors (Q5, Q5i) each having a drain connected to the capacitor 128 (i.e. C), a source connected to the first node 112, and a gate controllable by a control voltage signal (VT, VTi) distinct of the control voltage signals to control the gates of the other first controllable transistors (Q5i). The one or more first controllable transistors (Q5, Q5i) are used to implement the variable resistor 126 (i.e. Rvar) in order to attenuate the high frequency peaking and hence, to achieve a tunable peaking effect. The high frequency peaking generated by the inductors (e.g. L1 , L2) can be attenuated by reducing the value of the variable resistor 126 (i.e. Rvar). This is further described in detail, for example, in FIGs. 1 E and 1 F.

In accordance with an embodiment, the variable resistor 126 (i.e. Rvar) comprises one or more second controllable transistors (Q6, Q6i) each having a drain connected to the capacitor 128 (i.e. C), a source connected to the second node 118, and a gate controllable by a control voltage signal (VT) distinct of the control voltage signals to control the gates of the other second controllable transistors (Q6i). Similar to the one or more first controllable transisotrs (Q5, Q5i), the one or more second controllable transistors (Q6, Q6i) are included to vary the resistance of the variable resistor 126 (i.e. Rvar) to achieve the tunable peaking effect. Additionally, the one or more second controllable transistors (Q6, Q6i) are digitally controlled by the control voltage signals.

In accordance with an embodiment, the respective gates of at least one of the first controllable transistors (Q5) and at least one of the second controllable transistors (Q6) are connected together so as to be controllable by the same control voltage signal (VT). The variable resistor 126 (i.e. Rvar) can be implemented by use of the at least one first controllable transistor (i.e. Q5) and the at least one second controllable transistor (i.e. Q6) in order to control the high frequency peaking. A lower value of the variable resistor 126 (i.e. Rvar) results in a lower peaking. This is further described in detail, for example, in FIG. 1 E. In accordance with an embodiment, the amplifier circuit 100A comprises the first voltage source connecting point (VDD), to be connected to the first voltage source 134, between the first and the second resistor-inductor circuits 122 (i.e. RL1 , L1), 124 (i.e. RL2, L2). The first voltage source 134 (i.e. VDD) is used to drive the amplifier circuit 100A. The drain terminals 106C and 110C of the first output transistor 106 (i.e. Q3) and the second output transistor 110 (i.e. Q4), respectively, are powered by the first voltage source 134 (i.e. VDD).

In accordance with an embodiment, the amplifier circuit 100A comprises the second voltage source connecting point (VGG), to be connected to the second voltage source 132, between the respective gates of the first and second output transistors 106 and 110 (i.e. Q3, Q4). The gate terminals 106A and 110A of the first output transistor 106 (i.e. Q3) and the second output transistor 110 (i.e. Q4), respectively, are powered by the second voltage source 132 (i.e. VGG) which is connected at the second voltage source connecting point in the amplifier circuit 100A.

In accordance with an embodiment, the amplifier circuit 100A comprises the resistor 130 (i.e. Rs) connected to the ground and between the respective sources of the first and second input transistors 104 and 108 (i.e. Q1, Q2). The resistor 130 (i.e. Rs) is connected to the ground to maintain a reference (e.g. a reference voltage or a reference current) throughout the amplifier circuit 100A.

Thus, the amplifier circuit 100A of the present disclosure does not require variable capacitors, variable inductors or a variable feedback circuitry for achieving the tunable peaking function and thus can be easily implemented by use of the Gallium Arsenide (GaAs) technology. The amplifier circuit 100A of the present disclosure achieves a maximum available gain in a full operating frequency range which is described in detail, for example, in FIG. 2A. Further, the amplifier circuit 100A of the present disclosure does not require direct currents flowing on variable components and consequently does not affect a gain roll-off owing to the variable components being isolated from the output ports by the first and the second output transistors, that is described in detail, for example, in FIG. 3A. Additionally, the amplifier circuit 100A of the present disclosure does not increase DC power consumption with respect to the standard DC power consumption that is required to bias the differential cascode pair and also is not susceptible to instability as the amplifier circuit 100A of the present disclosure does not introduce closed loops in its circuit, described in detail, for example, in FIG. 4A. Moreover, the disclosed amplifier circuit 100A can be used for different electro-optical modulators such as indium phosphide (InP) mach-zehnder modulator (MZM) and silicon polymer (SiP) mach-zehnder modulator (MZM) because of the tunable peaking function and that is described in detail, for example, in FIG. 5. FIG. 1B depicts a low frequency equivalent circuit of an amplifier circuit such as the amplifier circuit 100A of FIG. 1A, in accordance with an embodiment. FIG. 1B is described in conjunction with elements from FIG. 1A. With reference to FIG. 1 B, there is shown a circuit architecture that depicts a low frequency equivalent circuit 100B of the amplifier circuit 100A of FIG. 1 A.

The low frequency equivalent circuit 100B corresponds to the amplifier circuit 100A except a few differences. At low frequency, the the capacitor 128 (i.e. C) of the amplifier circuit 100A behaves as an open circuit, while the inductors 122B and 124B (i.e. L1 and L2) behave as a short circuit, hence, are not shown in the low frequency equivalent circuit 100B. Since, the variable resistor 126 (i.e. Rvar) is connected in series with the capacitor 128 (i.e. C) therefore, the variable resistor 126 (i.e. Rvar) is also not shown in the low frequency equivalent circuit 100B.

At low frequency, by neglecting parasitics (e.g. parasitic capacitances and resistances) of the transistors 104, 106, 108, and 110 (i.e. Q1, Q3, Q2, Q4, respectively) a resulting voltage gain (i.e. G) of the low frequency equivalent circuit 100B is a typical voltage gain of the differential cascode pair. The voltage gain (i.e. G) of the low frequency equivalent circuit 100B is given by the equation (equation 2)

G = 2 x g m x R L (2)

Where, RL1 = RL2 = RL and all transistors (e.g. Q1, Q3, Q2, Q4) are equal.

Working and connections of the first and second input and output transistors 104, 106, 108 and 110 (i.e. Q1-Q4), the first and second resistor-inductor circuits 122 and 124 is same that has been described in detail, for example, in FIG. 1 A and hence omitted here for the sake of brevity.

FIG. 1C depicts a high frequency equivalent circuit of an amplifier circuit such as the amplifier circuit 100A of FIG. 1A, in accordance with an embodiment. FIG. 1C is described in conjunction with elements from FIG. 1A. With reference to FIG. 1 C, there is shown a circuit architecture that depicts a high frequency equivalent circuit 100C of the amplifier circuit 100A of FIG. 1A.

In the high frequency equivalent circuit 100C of the amplifier circuit 100A, the capacitor 128 (i.e. C) is not shown because at high frequency, the capacitor 128 (i.e. C) of the amplifier circuit 100A behaves as a short circuit. Neglecting parasitics (e.g. parasitic capacitances) of the transistors 104, 106, 108 and 110 (i.e. Q1-Q4) and based on the assumption that RL1 = RL2 = RL, L1 = L2 = L and all transistors 104, 106, 108 and 110 (i.e. Q1-Q4) are equal, a resulting voltage gain of the high frequency equivalent circuit 100C is given by the equation (equation 3)

The high frequency peaking generated by the inductance (e.g. L1 = L2 = L) can be attenuated by reducing the value of the variable resistor 126 (i.e. Rvar), such that lower the value of the variable resistor 126 (i.e. Rvar), lower is the peaking. Working and connections of the first and second input and output transistors 104, 106, 108 and 110 (i.e. Q1-Q4), the first and second resistor-inductor circuits 122 and 124 is same that has been described in detail, for example, in FIG. 1 A and hence omitted here for the sake of brevity.

FIG. 1 D is a circuit diagram of an amplifier circuit, in accordance with another embodiment of the present disclosure. FIG. 1 D is described in conjunction with elements from FIG. 1A. With reference to FIG. 1 D, there is shown a circuit architecture of an amplifier circuit 100D. The amplifier circuit 100D includes a first controllable transistor 136 and a voltage signal 138.

The amplifier circuit 100D corresponds to the amplifier circuit 100A (of FIG. 1A) except a difference. The difference is that, in the amplifier circuit 100D, the first controllable transistor 136 (also represented by Q5) is used to realize the variable resistor 126 (i.e. RVAR). The first controllable transistor 136 (i.e. Q5) is controlled by the voltage signal 138 (also represented by VT). The first controllable transistor 136 (i.e Q5) includes a gate 136A, a source 136B, and a drain 136C. The gate 136A is connected to the voltage signal 138 (i.e. VT), the source 136B is connected with the first node 112 and the drain 136C is connected to the capacitor 128 (i.e. C). The voltage signal 138 (i.e. VT) is applied at the gate 136A of the first controllable transistor 136 (i.e. Q5) therefore, a resistance offered by the first controllable transistor 136 (i.e. Q5) can be varied by varying the voltage signal 138 (i.e. VT) in order to achieve a tunable peaking frequency In this embodiment, the first controllable transistor 136 (i.e. Q5) is a GaAs transistor which is advantageous over the conventional amplifier that is based on the silicon-germanium (SiGe) technology. The amplifier circuit 100D is an alternative implementation of the amplifier circuit 100A. Working and connections of the first and second input and output transistors 104, 106, 108 and 110 (i.e. Q1-Q4), the first and second resistor-inductor circuits 122 and 124 is same that has been described in detail, for example, in FIG. 1A and hence omitted here for the sake of brevity.

FIG. 1 E is a circuit diagram of an amplifier circuit, in accordance with yet another embodiment of the present disclosure. FIG. 1 E is described in conjunction with elements from FIG. 1A. With reference to FIG. 1E, there is shown a circuit architecture of an amplifier circuit 100E. The amplifier circuit 100E includes a second controllable transistor 140. The amplifier circuit 100E corresponds to the amplifier circuit 100A (of FIG. 1A) except a difference. The difference is that, in the amplifier circuit 100E, the variable resistor 126 (i.e. Rvar) is realized using the first controllable transistor 136 (i.e. Q5) and a second controllable transistor 140 (also represented by Q6). Each of the first controllable transistor 136 (i.e. Q5) and the second controllable transistor 140 (i.e. Q6) is controlled by the voltage signal 138 (i.e. VT). The second controllable transistor 140 (i.e. Q6) include a gate 140A, a source 140B, and a drain 140C. The drains 136C and 140C of each of the first controllable transistor 136 (i.e. Q5) and second controllable transistor 140 (i.e. Q6) are connected to the capacitor 128. The source 136B of the first controllable transistor 136 (i.e. Q5) is connected to the first node 112 and the source 140B of the second controllable transistor 140 (i.e. Q6) is connected to the second node 118. The gates 136A and 140A of the first and the second controllable transistors 136 (i.e. Q5) and 140 (i.e. Q6), respectively, are connected to the voltage signal 138 (i.e. VT). The voltage signal 138 (i.e. VT) is used to vary the resistance offered by the first and the second controllable transistors 136 (i.e. Q5) and 140 (i.e. Q6), respectively, in order to achieve the tunale peaking. The first and the second controllable transistors 136 (i.e. Q5) and 140 (i.e. Q6), respectively, are connected in a way to maintain a differential symmetry. Each of the first and the second controllable transistors 136 (i.e. Q5) and 140 (i.e. Q6), respectively, are GaAs field effect transistors

Working and connections of the first and second input and output transistors 104, 106, 108 and 110 (i.e. Q1-Q4), the first and second resistor-inductor circuits 122 and 124 is same that has been described in detail, for example, in FIG. 1A and hence omitted here for the sake of brevity.

FIG. 1 F is a circuit diagram of an amplifier circuit, in accordance with yet another embodiment of the present disclosure. FIG. 1F is described in conjunction with elements from FIGs. 1A, 1D, and 1 E. With reference to FIG. 1 F, there is shown a circuit architecture of an amplifier circuit 100F that includes one or more first controllable transistors such as a first controllable transistor 142A, up to N-th first controllable transistor 142N. The amplifier circuit 100F further includes one or more voltage signals such as a first voltage signal 144A, upto M-th voltage signal 144M.

The amplifier circuit 100F corresponds to the amplifier circuit 100A (of FIG. 1A) except a difference. The difference is that, in the amplifier circuit 100F, the variable resistor 126 (i.e. Rvar) is realized using the one or more first controllable transistors such as the first controllable transistor 142A (also represented by Q5), upto the N-th first controllable transistor 142N (also represented by QN or Q5i, where N or i is a whole number). Each of the one or more first controllable transistors (i.e. Q5-Q5i or Q5-QN) is controlled by each of the one or more voltage signals. For example, the first controllable transistor 142A (i.e. Q5) is controlled by the first voltage signal 144A (also represented by VT1). Similarly, the N-th first controllable transistor 142N (i.e. QN or Q5i) is controlled by the M-th voltage signal 144M (also represented by VTM or VTi, where M or i is a whole number)). Each of the one or more first controllable transistors (i.e. Q5-Q5i or Q5-QN) having a source connected to the capacitor 128 (i.e. C), a drain connected to the first node 112, and a gate controllable by a distinct control voltage signal (i.e. VT1-VTi or VT1-VTM) distinct of the control voltage signals to control the gates of the other first controllable transistors (Q5i or QN). In this way, the variable resistance is obtained by varying the one or more voltage signals (i.e. VT1-VTi or VT1-VTM) applied at respective gates of each of the one or more first controllable transistors (i.e. Q5-Q5i or Q5-QN). In this embodiment, each of the one or more first controllable transistors 142A-144N (i.e. Q5-Q5i or Q5-QN) is a Gallium Arsenide (GaAs) field effect transistor and is a digitally controlled transistor.

Working and connections of the first and second input and output transistors 104, 106, 108 and 110 (i.e. Q1-Q4), and the first and second resistor-inductor circuits 122 and 124 is same that has been described in detail, for example, in FIG. 1 A and hence omitted here for the sake of brevity.

In another embodiment, the variable resistor 126 (i.e. Rvar) is realized using one or more second controllable transistors (Q6, Q6i) each having a drain connected to the capacitor 128 (i.e. C), a source connected to the second node 118, and a gate controllable by a control voltage signal (VT) distinct of the control voltage signals to control the gates of the other second controllable transistors (Q6i).

FIGs. 2A-2B illustrate an exemplary advantageous characteristic of an amplifier circuit when compared to a conventional amplifier, in accordance with an embodiment of the present disclosure. FIG. 2A is a graphical representation that illustrates a frequency versus gain curve 200A of an amplifier circuit such as the amplifier circuits 100A-100F (of FIGs. 1A-1 F) at low and high voltages. FIG. 2B is a graphical representation that illustrates a frequency versus gain curve 200B of a conventional amplifier (e.g. variable resistor/capacitor (R/C) on a differential ground), in accordance with an exemplary scenario. FIG. 2A is described in conjunction with elements from FIGs. 1A to 1 F. In the frequency versus gain curves 200A and 200B, X-axes 202A and 202B represent frequency axes and Y-axes 204A and 204B represents gain values achieved by the amplifier circuit 100A-100F and the conventional amplifier (e.g. variable R/C on a differential ground), respectively. In the frequency versus gain curve 200A, a first curve 206A represents a frequency response of the amplifier circuits 100A-100F at low values of a control voltage signal VT (such as the control voltage signal 138 of FIG. 1D and not shown here) and a second curve 208A (represented by a dashed curve) represents a frequency response of the amplifier circuits 100A-100F at high values of the control voltage signal VT (such as the control voltage signal 138). In the frequency versus gain curve 200B, a first curve 206B represents a frequency response of the conventional amplifier (e.g. variable R/C on a differential ground) at low values of a control voltage signal and a second curve 208B (represented by dashed curve) represents a frequency response of the conventional amplifier (e.g. variable R/C on a differential ground) at high values of the control voltage signal. Also shown in the frequency versus gain curves 200A and 200B, there are dotted lines 210A and 21 OB, respectively, which represent a maximum available gain (or a reference gain) that can be achieved.

The frequency versus gain curves 200A and 200B also depict a first region 212A and a second region 212B those depict an overlapping region of frequency responses at low and high values of the control voltage signal VT (such as the control voltage signal 138). As indicated in the frequency versus gain curves 200A and 200B, in the first region 212A, the first and second curves 206A and 208A overlap and intersect at the maximum available gain 210A of the amplifier circuit, whereas in the second region 212B, the first and the second curves 206B and 208B are apart and below the maximum available gain 21 OB of the conventional amplifier (e.g. variable R/C on a differential ground). More particularly, the first region 212A indicates achieving a maximum available gain 210A at low frequency and the second region 212B indicates a gain reduction (i.e. below the maximum gain 210B of the conventional amplifier) at low frequencies. Accordingly, the amplifier circuit 100A-100F of the present technology do not affect a low frequency gain when compared to the conventional amplifier (e.g. variable R/C on a differential ground).

FIGs. 3A-3B illustrate another advantage of an amplifier circuit when compared to a conventional amplifier, in accordance with an embodiment of the present disclosure. FIG. 3A is a graphical representation that illustrates a frequency versus gain curve 300A of an amplifier circuit such as the amplifier circuits 100A-100F (of FIGs. 1A-1 F). FIG. 3B is a graphical representation that illustrates a frequency versus gain curve 300B of a conventional amplifier (e.g. variable R/L/C on an output side), in accordance with an exemplary scenario. FIG. 3A is described in conjunction with elements from FIGs. 1A to 1 F. In the frequency versus gain curves 300A and 300B, X-axes 302A and 302B represent frequency axes and Y-axes 304A and 304B represent gain values achieved by the amplifier circuits 100A-100F and the conventional amplifier (e.g. variable R/L/C on output side), respectively. In the frequency versus gain curve 300A, a first curve 306A represents a frequency response of the amplifier circuit 100A-100F at low values of a control voltage signal VT (such as the control voltage signal 138 of FIG. 1 D and not shown here) and a second curve 308A (represented by dashed curve) represents a frequency response of the amplifier circuits 100A-100F at high values of the control voltage signal VT (such as the control voltage signal 138). In the frequency versus gain curve 300B, a first curve 306B represents a frequency response of the conventional amplifier (e.g. variable R/L/C on output side) at low values of a control voltage signal and a second curve 308B (represented by dashed curve) represents a frequency response of the conventional amplifier (e.g. variable R/L/C on output side) at high values of the control voltage signal.

In the frequency versus gain curve 300A, a horizontal dotted line 310A represents a maximum available gain of the amplifier circuits 100A-100F. In the frequency versus gain curve 300B, a horizontal dotted line 310B represents a maximum available gain of the conventional amplifier (e.g. variable R/L/C on output side). The frequency versus gain curves 300A and 300B also depict a first region 312A and a second region 312B. As indicated in the frequency versus gain curves 300A and 300B, in the first region 312A, the first and second curves 306A and 308A overlap, indicating a same rate of roll-off for the first and the second curves 306A and 308A, respectively. The term “roll-off” refers to the steepness or rate of fall of amplification gain with respect to frequency. As depicted in FIG. 3B, in the second region 312B, the first and the second curves 306B and 308B are apart, indicating different rates of roll-off of the first and the second curves 306B and 308B respectively, at high frequencies. This further indicates a roll-off being affected at different voltages and at higher frequencies, in the case of the conventional amplifier (e.g. variable R/L/C at output side). The different rates of roll-off may be caused by direct currents flowing through the variable components, such as variable R/L/C at the output side of the conventional amplifier (e.g. variable R/L/C on the output side). In the amplifier circuits 100A-100F of the present disclosure, the variable components (e.g. the first resistor-inductor circuit 122 (i.e. RL1 , L1) and the second resistor-inductor circuit 124) (i.e. RL2, L2) are isolated from the output ports by the first and second output transistors 106 (i.e. Q3) and 110 (i.e. Q4). Moreover, the amplifier circuits 100A-100F do not require a direct current flowing through the variable components (e.g. the first resistor-inductor circuit 122 (i.e. RL1 , L1) and the second resistor-inductor circuit 124 (i.e. RL2, L2)) and accordingly the amplifier circuits 100A-100F does not affect the rate of roll-off (particularly at higher frequencies) as indicated by the first region 312A in the FIG. 3A.

FIGs. 4A-4B illustrate yet another advantage of an amplifier circuit when compared to a conventional amplifier, in accordance with an embodiment of the present disclosure. FIG. 4A is a graphical representation that illustrates a frequency versus gain curve 400A of an amplifier circuit such as the amplifier circuits 100A-100F (of FIGs. 1A-1 F). FIG. 4B is a graphical representation that illustrates a frequency versus gain curve 400B of a conventional amplifier (e.g. variable feedback), in accordance with an exemplary scenario. FIGs. 4A-4B is described in conjunction with elements from FIGs. 1A to 1F. In the frequency versus gain curves 400A and 400B, X-axes 402A and 402B represents frequency axes and Y-axes 404A and 404B represent gain values achieved by the amplifier circuits 100A-100F and the conventional amplifier (e.g. variable feedback), respectively. In the frequency versus gain curve 400A, a first curve 406A represents a frequency response of the amplifier circuits 100A-100F at low values of a control voltage signal VT (such as the control voltage signal 138) and a second curve 408A (represented by dashed curve) represents a frequency response of the amplifier circuits 100A- 100F at high values of the control voltage signal VT (such as the control voltage signal 138). In the frequency versus gain curve 400B, a first curve 406B represents a frequency response of the conventional amplifier (e.g. variable feedback) at low values of a control voltage signal and a second curve 408B (represented by dashed curve) represents a frequency response of the conventional amplifier (e.g. variable feedback) at high values of the control voltage signal. In frequency versus gain curve 400A, a horizontal dotted line 410A represents a maximum available gain of the amplifier circuits 100A-100F. In frequency versus gain curve 400B, a horizontal dotted line 410B represents a maximum available gain of the conventional amplifier (e.g. variable feedback).

The frequency versus gain curves 400A and 400B also depict a first region 412A and a second region 412B. As indicated in the frequency versus gain curves 400A and 400B, in the first region 412A, the first and second curves 406A and 408A overlap and do not depict any out of band spurs, whereas in the second region 412B the first and the second curves 406B and 408B are apart and the second curve 408B has a spike 414B indicative of out of band spurs at high voltage values and at high frequencies, in turn indicative of instability due to a positive feedback loop generated by the variable feedback in the conventional amplifier (e.g. variable feedback). Moreover, the conventional amplifier (e.g. variable feedback) increases a direct current (DC) power consumption in order to bias the variable feedback and leads to stability issues due to limitation in a stability phase margin. On the contrary, the amplifier circuits 100A- 100F of the present disclosure do not increase DC power consumption owing to a standard DC power consumption being required to bias the differential cascode pair and also is not susceptible to instability being devoid of any closed loops.

Accordingly, the amplifier circuits 100A-100F offer several advantages when compared to the conventional amplifier circuits as explained above along with FIGs. 2A-4B.

Typically, electro-optical modulators, for example, indium phosphide coherent driver modulator (e.g. 800G - InPCDM), silicon polymer inter cluster trunk (e.g. 800G - SiPICT) modulator, indium phosphide mach zehnder modulator (InP-MZM), and silicon polymer mach zehnder modulator (SiP-MZM) require different peaking level at different frequencies. The amplifier circuits 100A-100F of the present disclosure simultaneously supports different electro- optical modulators by providing tunable peaking at different frequencies as described further along with FIG. 5. The amplifier circuits 100A-100F of the present disclosure also facilitate optimization of a final module frequency response owing to tunable peaking, that enables usability of the amplifier circuits 100A-100F with different platforms and modules.

FIG. 5 depicts a graphical representation that illustrates a differential insertion loss of an amplifier circuit, in accordance with an exemplary scenario of the present disclosure. With reference to FIG. 5, there is shown a graphical representation 500 that includes an X-axis 502 that represents frequency in giga hertz (GHz) and a Y-axis 504 that represents differential insertion loss in decibels (dB) of an amplifier circuit such as the amplifier circuits 100A-100F when used with an indium phosphide mach zehnder modulator (InP-MZM) and an silicon polymer mach zehnder modulator (SiP-MZM). In the graphical representation 500, a first curve 506 represents a first plot of differential insertion loss versus frequency for the amplifier circuits 100A-100F when used with the InP-MZM modulator and the second curve 508 represents a second plot of the differential insertion loss versus frequency for the amplifier circuits 100A- 100F when used with the SiP-MZM modulator. As used herein the term “differential insertion loss” refers to a ratio of the power in radio frequency over that available from a voltage source. As depicted in the graphical representation 500, a point 510 corresponds to a differential insertion loss of 12.369 decibels (db) corresponding to a frequency of 1 gigahertz (GHz) for both the InP-MZM modulator and SiP-MZM modulator implementations. As depicted in the graphical representation 500, the differential insertion loss remains almost equal for both the InP-MZM modulator and SiP-MZM modulator upto about 20 GHz as indicated by vertical dotted line 512. Accordingly, the amplifier circuits 100A-100F facilitate variable peaking for both InP-MZM modulator and SiP-MZM modulator while maintaining the differential insertion loss and supports both the InP-MZM modulator as well as SiP-MZM modulator.

FIG. 6 is a block diagram that illustrates various exemplary components of a transmitter, in accordance with an embodiment of the present disclosure. FIG. 6 is described in conjunction with elements from FIGs. 1 A-1 F. With reference to FIG. 6, there is shown a block diagram of a transmitter 600 that includes a digital source 602, an amplifier circuit 604, and an electro-optical modulator 606.

The transmitter 600 includes suitable logic, circuitry, and/or interfaces that is configured to have a transmit path comprising the amplifier circuit 604. The amplifier circuit 604 corresponds to the amplifier circuit 100A (of FIG. 1A) and its various alternative implementation forms 100B-100F (of FIGs. 1 B-1 F). Thus, all the operations executed by the amplifier circuit 604 are part of the operations executed by the transmitter 600. The transmitter 600 may also be referred to as a transmitting device or a transmitter circuit. Examples of the transmitter 600 includes, but is not limited to, a broad band monolithic integrated circuit, a broad band driver amplifier, a customized hardware for the high data rate optical communication system, or any other portable or non-portable optical device.

The digital source 602 includes suitable logic, circuitry, and/or interfaces that is configured for signal generation. The digital source 602 is used to generate a digital signal 608. Examples of the digital source 602 includes, but is not limited to, an arbitrary waveform generator, a digitizer, a digital waveform generator and the like.

The amplifier circuit 604 includes suitable logic, circuitry, and/or interfaces that is configured for providing sufficient signal amplification as required to generate an amplified signal 610 to drive the electro-optical modulator 606.

The electro-optical modulator 606 includes suitable logic, circuitry, and/or interfaces that is configured to transduce the amplified signal 610 to an optical signal 612 to be transferred through an optical fiber. Examples of the electro-optical modulator 606 includes, but is not limited to an amplitude modulator, phase modulator, polarization modulator, spatial light modulator, indium phosphide coherent driver modulator (800G-lnP CDM), silicon polymer inter Cluster trunk (800G-SiP ICT) modulator, indium phosphide mach zehnder modulator (InP-MZM ), and silicon polymer mach zehnder (SiP-MZM) modulator and many alike.

In the transmit path of the transmitter 600, the amplifier circuit 604 acts as an ultra wideband amplifier. The amplifier circuit 604 operates in collaboration with the digital source 602 and provides a collective amplification gain that is required to drive the electro-optical modulator 606.

Thus, the transmitter 600 provides a high bandwidth and a high amplification gain required for a high data rate optical communication system by use of the amplifier circuit 604. The requirement of wide bandwidth is fulfilled by the amplifier circuit 604 in the transmitter 600. The transmitter 600 has a high amplification gain that is required to drive the electro-optical modulator 606 because of the amplifier circuit 604.

Modifications to embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as "including", "comprising", "incorporating", "have", "is" used to describe and claim the present disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and/or to exclude the incorporation of features from other embodiments. The word "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments". It is appreciated that certain features of the present disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the present disclosure, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure.