Title:
ANALOG-TO-DIGITAL CONVERTER CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2022/044588
Kind Code:
A1
Abstract:
There is provided an analog-to-digital converter circuit including: a first converter circuit generating a first digital code by performing analog-to-digital conversion on the basis of an input voltage; a second converter circuit generating a second digital code by performing, on the basis of the input voltage and the first digital code, analog-to-digital conversion over a voltage range wider than that of a least significant bit of the first converter circuit; an error detector detecting a conversion error of the analog-to-digital conversion on the basis of the first and second digital codes, thereby generating error data indicating a bit having a conversion error and the kind of the conversion error; and a calibration circuit estimating an error factor on the basis of the first and second digital codes and the error data, and performing calibration of a circuit relevant to the estimated error factor on the basis of an estimation result.
Inventors:
BUNSEN KEIGO (JP)
MARTENS EWOUT (BE)
DERMIT DAVIDE (BE)
CRANINCKX JAN (BE)
MARTENS EWOUT (BE)
DERMIT DAVIDE (BE)
CRANINCKX JAN (BE)
Application Number:
PCT/JP2021/026350
Publication Date:
March 03, 2022
Filing Date:
July 13, 2021
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
IMEC VZW (BE)
IMEC VZW (BE)
International Classes:
H03M1/10; H03M1/14; H03M1/12; H03M1/36; H03M1/42; H03M1/46
Foreign References:
| JP2010109937A | 2010-05-13 | |||
| US203962630717P |
Other References:
VERBRUGGEN BOB ET AL: "C268 978-4-86348-348-4 2013 Symposium on VLSI Circuits Digest of Technical Papers A 2.1 mW 11b 410 MS/s Dynamic Pipelined SAR ADC with Background Calibration in 28nm Digital CMOS", 12 June 2013 (2013-06-12), pages C268 - C269, XP055844561, Retrieved from the Internet [retrieved on 20210924]
BOB VERBRUGGEN ET AL: "A 1.7mW 11b 250MS/s 2x interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS", SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2012 IEEE INTERNATIONAL, IEEE, 19 February 2012 (2012-02-19), pages 466 - 468, XP032154545, ISBN: 978-1-4673-0376-7, DOI: 10.1109/ISSCC.2012.6177093
SHIN SOON-KYUN ET AL: "A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 49, no. 6, June 2014 (2014-06-01), pages 1366 - 1382, XP011549317, ISSN: 0018-9200, [retrieved on 20140528], DOI: 10.1109/JSSC.2014.2322853
SIRAGUSA E J ET AL: "Gain error correction technique for pipelined analogue-to-digital converters", ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 36, no. 7, 30 March 2000 (2000-03-30), pages 617 - 618, XP006015054, ISSN: 0013-5194, DOI: 10.1049/EL:20000501
D. DERMITM. SHRIVASK. BUNSENJ. L. BENITESJ. CRANINCKXE. MARTENS: "A 1.67-GSps TI 10-Bit Ping-Pong SAR ADC With 51-dB SNDR in 16-nm FinFET", IEEE SOLID-STATE CIRCUITS LETTERS, vol. 3, 2020, pages 150 - 153, XP011801923, DOI: 10.1109/LSSC.2020.3008264
MARTENS, E.HERSHBERG, B.CRANINCKX, J.: "Wide-tuning range programmable threshold comparator using capacitive source-voltage shifting", ELECTRON. LETT., vol. 54, 2018, pages 1417 - 1418, XP006075415, DOI: 10.1049/el.2018.6121
BOB VERBRUGGEN ET AL: "A 1.7mW 11b 250MS/s 2x interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS", SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2012 IEEE INTERNATIONAL, IEEE, 19 February 2012 (2012-02-19), pages 466 - 468, XP032154545, ISBN: 978-1-4673-0376-7, DOI: 10.1109/ISSCC.2012.6177093
SHIN SOON-KYUN ET AL: "A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 49, no. 6, June 2014 (2014-06-01), pages 1366 - 1382, XP011549317, ISSN: 0018-9200, [retrieved on 20140528], DOI: 10.1109/JSSC.2014.2322853
SIRAGUSA E J ET AL: "Gain error correction technique for pipelined analogue-to-digital converters", ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 36, no. 7, 30 March 2000 (2000-03-30), pages 617 - 618, XP006015054, ISSN: 0013-5194, DOI: 10.1049/EL:20000501
D. DERMITM. SHRIVASK. BUNSENJ. L. BENITESJ. CRANINCKXE. MARTENS: "A 1.67-GSps TI 10-Bit Ping-Pong SAR ADC With 51-dB SNDR in 16-nm FinFET", IEEE SOLID-STATE CIRCUITS LETTERS, vol. 3, 2020, pages 150 - 153, XP011801923, DOI: 10.1109/LSSC.2020.3008264
MARTENS, E.HERSHBERG, B.CRANINCKX, J.: "Wide-tuning range programmable threshold comparator using capacitive source-voltage shifting", ELECTRON. LETT., vol. 54, 2018, pages 1417 - 1418, XP006075415, DOI: 10.1049/el.2018.6121
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
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