COMPOSITING

TECHNICAL FIELD

[0001] The aspects of the disclosed embodiments relate generally to a computer display apparatus and, more particularly, to rendering and compositing of digital video data.

BACKGROUND

[0002] Many modern devices include multiple computing systems to satisfy different user needs. For example, an automobile may have an instrument cluster, a navigation system, and passenger entertainment systems, where each system or device directs its visual content to a spatially separate display. To reduce cost, a single hardware computing platform, such as a system on chip (SoC), may be used to host several virtual machines (VM) to support multiple applications and display devices. Each VM can drive a spatially separate display.

[0003] Processing of display data is computationally intensive and can overwhelm a processor. For this reason many SoC include hardware support, such as a graphics processing unit (GPU) and a hardware compositor (HWC), for rendering and compositing video images. However, using conventional techniques, the GPU and HWC can still become a bottleneck when driving multiple separate displays from a single SoC, resulting in substandard and inadequate video quality.

[0004] Thus, there is a need for improved methods and apparatuses that can efficiently process video data when running multiple applications driving multiple display devices on a single SoC. Accordingly, it would be desirable to provide methods and apparatuses that address at least some of the problems described above. SUMMARY

[0005] The aspects of the disclosed embodiments are directed to efficient multi-display two-dimensional (2D) compositing in virtualized environments executing within a single system-on-chip (SoC). The disclosed embodiments allow a single SoC to run an application that would otherwise require multiple SoC using a conventional apparatus. This and other objectives are solved by the subject matter of the independent claims. Further advantageous embodiments can be found in the dependent claims.

[0006] According to a first aspect, the above and further objectives and advantages are obtained by an apparatus. In one embodiment, the apparatus includes a processor, a hardware compositor, a display controller, and a plurality of display devices. The processor is configured to process a plurality of virtual display bitmaps and map each virtual display bitmap of the plurality of virtual display bitmaps with a corresponding hardware layer of a plurality of hardware layers to form a plurality of mapped bitmaps. Each hardware layer of the plurality of hardware layers is associated with a corresponding display of the plurality of display devices. The plurality of mapped bitmaps are sent to the hardware compositor. The hardware compositor is configured to composite the plurality of mapped bitmaps and populate a framebuffer. The framebuffer comprises a plurality of pixel regions and each mapped bitmap of the plurality of mapped bitmaps is composited within a corresponding pixel region of the plurality of pixel regions. The display controller is configured to process the framebuffer and present each pixel region of the plurality of pixel regions on a corresponding display device of the plurality of display devices. The apparatus of the disclosed embodiments is configured for efficiently displaying graphics on a plurality of displays generated from multiple computer applications executing on one or more virtual machines. [0007] In a possible implementation form of the apparatus according to the first aspect, the hardware compositor is further configured to composite at least two hardware layers of the plurality of hardware layers onto a single pixel region of the plurality of pixel regions. Mapping the output from multiple virtual machines or virtual display bitmaps to the same hardware layer provides support for a variety of beneficial features to be presented to an end user. For example, mapping the output from one virtual machine to a first hardware layer, and mapping the output from a second virtual machine to a small portion of the first hardware layer, such as the upper corner portion of the first hardware layer, provides a picture-in-picture feature.

[0008] In a possible implementation form of the apparatus, the apparatus includes a graphics processing unit. The processor is further configured to execute a hypervisor, host a plurality of virtual machines based on the hypervisor and send rendering commands from each virtual machine of the plurality of virtual machines to the graphics processing unit. The graphics processing unit is configured to generate the plurality of virtual display bitmaps and the processor is further configured to receive the plurality of virtual display bitmaps from the graphics processing unit. Each virtual display bitmap of the plurality of virtual display bitmaps corresponds to a different virtual machine of the plurality of virtual machines. Including a graphics processing unit and sending rendering commands to the graphics processing unit avoids saturating the processor with rendering tasks thereby allowing additional virtual machines to be executed on a single SoC. [0009] In a possible implementation form of the apparatus, the processor is further configured to process the plurality of virtual display bitmaps based on geometrical and visual properties of the plurality of virtual display bitmaps. Incorporating geometrical and visual properties while processing the virtual display bitmaps improves image quality and supports additional visual features in the mapped bitmaps. [0010] In a possible implementation form of the apparatus, the hardware compositor is configured to perform data operations on the plurality of mapped bitmaps. The data operations include one or more of a bit-blitting, alpha blending, translating, scaling, and rotating. Supporting a variety of data operations within the hardware compositor provides additional visual effects and features without overloading the processor.

[0011] In a possible implementation form of the apparatus, the processor is configured to execute a display manager in a hypervisor context. Executing the display manager in the hypervisor context allows a single display manager to be shared among all virtual displays thereby allowing coordination of display resources and adding opportunity for additional visual features to be supported.

[0012] In a possible implementation form of the apparatus, the apparatus is configured to be incorporated into a mobile communication device. Mobile communication devices include limited processing resources and are very sensitive to power consumption. Thus, the disclosed embodiments can provide significant advantage in mobile communication devices especially when more than one display is included in the device.

[0013] In a possible implementation form of the apparatus, the apparatus is configured to be incorporated into an automobile. Modem automobiles include many different subsystems, such as instrument consoles, navigation, and infotainment systems. It is common for automobiles to have several infotainment systems such as one for the front seat passenger and more for the rear seat passengers. The savings in processing resources provided by the apparatus of the disclosed embodiments can significantly reduce the number of SoC devices required to drive all the spatially separate displays.

[0014] According to a second aspect, the above and further objectives and advantages are obtained by a method. In one embodiment, the method includes processing a plurality of virtual display bitmaps and mapping each virtual display bitmap of the plurality of virtual display bitmaps with a corresponding hardware layer of a plurality of hardware layers to form a plurality of mapped bitmaps. Each hardware layer of the plurality of hardware layers is associated with a corresponding display device of a plurality of display devices. The plurality of mapped bitmaps are sent to a hardware compositor. The hardware compositor composites the plurality of mapped bitmaps and populates a framebuffer. The framebuffer incudes a plurality of pixel regions and each mapped bitmap of the plurality of mapped bitmaps is composited and stored in a corresponding pixel region of the plurality of pixel regions. The framebuffer is processed and each pixel region of the plurality of pixel regions is presented on a corresponding display device of the plurality of display devices. The aspects of the disclosed embodiments are directed to efficiently displaying graphics on a plurality of displays generated from multiple computer applications executing on one or more virtual machines.

[0015] In a possible implementation form of the method, the compositing comprises compositing at least two hardware layers of the plurality of hardware layers onto a single pixel region of the plurality of pixel regions. A corresponding mapped bitmap in the plurality of mapped bitmaps includes data from the at least two virtual display bitmaps. Mapping the output from multiple virtual machines or virtual display bitmaps to the same hardware layer provides support for a variety of beneficial features to be presented to an end user. For example, mapping the output from one virtual machine to a first hardware layer, and mapping the output from a second virtual machine to a small portion of the first hardware layer, such as the upper corner portion of the first hardware layer, provides a picture-in-picture feature.

[0016] In a possible implementation form of the method, the method further includes executing a hypervisor, hosting a plurality of virtual machines based on the hypervisor, sending rendering commands from each virtual machine of the plurality of virtual machines to a graphics processing unit, generating, using the graphics processing unit the plurality of virtual display bitmaps and receiving the plurality of virtual display bitmaps from the graphics processing unit. Each virtual display bitmap of the plurality of virtual display bitmaps corresponds to a different one of the virtual machines of the plurality of virtual machines. Including a graphics processing unit and sending rendering commands to the graphics processing unit avoids saturating the processor with rendering tasks, thereby allowing additional virtual machines to be executed on a single SoC.

[0017] In a possible implementation form of the method, the method further includes processing the plurality of virtual display bitmaps based on geometrical and visual properties of the plurality of virtual display bitmaps. Incorporating geometrical and visual properties while processing the virtual display bitmaps improves image quality and supports additional visual features in the mapped bitmaps.

[0018] In a possible implementation form of the method, the compositing further includes performing data operations on the plurality of mapped bitmaps. The data operations include one or more of a bit-blitting, alpha blending, translating, scaling, and rotating. Supporting a variety of data operations within the hardware compositor provides additional visual effects and features without overloading the processor.

[0019] In a possible implementation form of the method, the display manager is executed in a hypervisor context. Executing the display manager in the hypervisor context allows a single display manager to be shared among all virtual displays thereby allowing coordination of display resources and adding opportunity for additional visual features to be supported.

[0020] According to a third aspect, the above and further objectives and advantages are obtained by a non-transitory computer readable medium having stored thereon program instructions. The program instructions, when executed by a processor, are configured to cause the processor to perform the method according to any one or more of the possible implementation forms of the method described herein. Storing program instructions on a non- transitory computer readable medium provides a convenient means to distribute or incorporate the objects and advantages of the disclosed embodiments onto a device such as an automobile or mobile communications device.

[0021] These and other aspects, implementation forms, and advantages of the exemplary embodiments will become apparent from the embodiments described herein considered in conjunction with the accompanying drawings. It is to be understood, however, that the description and drawings are designed solely for purposes of illustration and not as a definition of the limits of the disclosed invention, for which reference should be made to the appended claims. Additional aspects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. Moreover, the aspects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In the following detailed portion of the present disclosure, the invention will be explained in more detail with reference to the example embodiments shown in the drawings, in which:

[0023] Figure 1 illustrates a block diagram of an exemplary computing apparatus configured to display visual content from multiple virtual machines incorporating aspects of the disclosed embodiments; and [0024] Figure 2 illustrates a flow diagram of an exemplary method for displaying visual content incorporating aspects of the disclosed embodiments.

DETAILED DESCRIPTION OF THE DISCLOSED EMBODIMENTS

[0025] Referring to Figure 1, a schematic block diagram of an exemplary apparatus 100 incorporating aspects of the disclosed embodiments is illustrated. The aspects of the disclosed embodiments are directed to efficient rendering, compositing, and displaying of digital video information within computing apparatus. When multiple virtual machines are used to execute a variety of different software applications, each of which is configured to display information on spatially separated display devices, hardware-based graphics acceleration hardware, such as graphics processing units (GPU), and hardware compositors (HWC), can become saturated, resulting in degraded video quality. The apparatus 100 is configured for efficiently displaying graphics on a plurality of displays generated from multiple computer applications executing on one or more virtual machines.

[0026] As shown in Figure 1, the apparatus 100 includes a processor 102, a memory 104, a hardware compositor 108, a display controller 110, and a plurality of display devices

112-1, 112-2, 112-3. Although only three display devices will be referred to herein, it will be understood that the apparatus 100 can include any suitable number of display devices, other than including three. For example, in one embodiment, the apparatus 100 can include more or less than three display devices 112-1, 112-2, 112-3, such as two or five or seven display devices.

[0027] In the example of Figure 1, the processor 102 is coupled to the memory 104.

Although only one memory 104 is illustrated in Figure 1, it will be understood that the memory 104 can comprise one or more memory blocks or modules. The memory 104 may be a combination of various types of volatile and non-volatile computer memory such as for example read only memory (ROM), random access memory (RAM), magnetic or optical disk, flash, or other appropriate types of computer memory.

[0028] The processor 102 can include any suitable type of computer processing apparatus. For example the processor 102 may be a single processing device or may comprise a plurality of processing devices including special purpose devices, such as digital signal processing (DSP) devices, microprocessors, specialized processing devices, parallel processing cores, or general purpose computer processors. In certain embodiments the processor 102 and memory 104 may be incorporated into a system on a chip (SoC) device or chipset. The processor 102 is configured to read non-transient program instructions from the memory 104 and perform any of the methods and processes described herein.

[0029] In the example of Figure 1, the processor 102 is configured to process a plurality of virtual display bitmaps 116-1, 116-2, 116-3. Each virtual display bitmap in the plurality of virtual display bitmaps 116-1, 116-2, 116-3 is mapped with a corresponding hardware layer in a plurality of hardware layers 128-1, 128-2, 128-3. In this manner, a plurality of mapped bitmaps 120-1, 120-2, 120-3 is formed. As will be discussed further below, maintaining a one- to-one relationship between virtual display bitmaps 116-1, 116-2, 116-3 and hardware layers 128-1, 128-2, 128-3 will, in certain embodiments, yield the greatest benefit from the acceleration provided by the hardware compositor 108. In this example, three displays and three hardware layers are illustrated, it being understood, as described above, that the apparatus 100 can include more or less than three displays and more or less than three hardware layers.

[0030] In one embodiment, and in combination with the other embodiments described herein, the processor 102 is configured to send the plurality of mapped bitmaps 120-1, 120-2, 120-3 to the hardware compositor 108. The hardware compositor 108 is configured to composite the plurality of mapped bitmaps 120-1, 120-2, 120-3 and populate a framebuffer 122. In the example of Figure 1, the framebuffer 122 comprises a plurality of pixel regions 124-1, 124-2, 124-3. Each mapped bitmap in the plurality of mapped bitmaps 120-1, 120-2, 120-3 is composited within a corresponding pixel region in the plurality of pixel regions 124- 1, 124-2, 124-3. [0031] As used herein, the term “compositing” or “composites” refers to the combining of visual elements from separate sources or bitmaps into a single image or bitmap. For example the hardware compositor 108 composites the plurality of mapped bitmaps into the framebuffer 122

[0032] The processor 102 is further configured to process the framebuffer 122 within the display controller 110. Each pixel region in the plurality of pixel regions 124-1, 124-2, 124-3 is presented on a corresponding display device of the plurality of display devices 112-1, 112-2, 112-3. In this manner, the apparatus 100 provides efficient multi-display two- dimensional (2D) compositing in virtualized environments using single system-on-chip (SoC), where virtual machines running under control of a hypervisor can efficiently send multiple streams of visual content to a plurality of spatially separated physical display devices.

[0033] Referring to Figure 1, the processor 102 is configured to execute a hypervisor

126 and a plurality of virtual machines 114-1, 114-2, 114-3. A hypervisor 126, also referred to as a virtual machine manager, or virtual machine monitor, is a computer program implemented as one or more of a computer software, firmware, and hardware, which manages execution of virtual machines 114-1, 114-2, 114-3. The hypervisor 126 allocates computing resources and presents a virtual operating platform to guest operating systems running within each virtual machine 114-1, 114-2, 114-3. While three virtual machines are shown in the apparatus 100 illustrated in Figure 1, those skilled in the art will readily recognize that more or less than three virtual machines may be hosted by the hypervisor 126 within the computing apparatus 100 without straying from the spirit and scope of the disclosed embodiments.

[0034] Many modern apparatus incorporate multiple computing devices where each device solves a particular problem or provides its own feature set and presents its output on a separate display. For example, an automobile may incorporate a navigation system, entertainment system, and an instrument cluster, each displaying output on spatially separate displays. To conserve cost, these separate computer applications may be executed on a single computing apparatus, such as the computing apparatus 100, with each application being executed on a different virtual machine 114-1, 114-2, 114-3, and sending its output to a corresponding virtual display 116-1, 116-2, 116-3. The virtual display bitmaps 116-1, 116-2, 116-3 can then, as will be discussed in more detail below, be mapped onto and presented on a plurality of physical display devices 112-1, 112-2, 112-3.

[0035] In the illustrated embodiment, the plurality of virtual machines 114-2, 114-2,

114-3 may be configured to run distinct and possibly independent computer applications. Some of these virtual machines will produce visual content and the produced visual content is to be displayed on corresponding display devices. To offload graphics processing tasks from the processor 102, a graphics processing unit 106 is included in the exemplary apparatus 100 to perform rendering functions and generate bitmaps. A graphics processing unit, such as the graphics processing unit 106, is a hardware based graphics accelerator designed to efficiently create digital images or bitmaps intended for output on a computer display device. Each virtual machine 114-1, 114-2, 114-3 is configured to send rendering commands 130 to the graphics processing unit 106.

[0036] The graphics processing unit 106 generates bitmaps based on received rendering commands 130 and returns 132 the bitmaps, referred to herein as virtual display bitmaps 116- 1, 116-2, 116-3, to the processor 102. As illustrated in Figure 1, each virtual display bitmap 116-1, 16-2, 116-3 is associated with the corresponding virtual machine 114-2, 114-2, 114-3 for which it was generated.

[0037] The apparatus 100 also includes a display manager 118. In the example of Figure 1, the display manager 118 is incorporated within the hypervisor 126 and configured to process the virtual display bitmaps 116-1, 116-2, 116-3 on behalf of each virtual machine 114-

2, 114-2, 114-3. The display manager 118 is configured to map the processed virtual display bitmaps to a desired hardware layer of the plurality of hardware layers 128-1, 128-2, 128-3. The display manager 118 is configured to execute in the context of the hypervisor 126, and produces a set of mapped bitmaps 120-1, 120-2, 120-3. The set of mapped bitmaps 120-1, 120- 2 and 120-3 may be composited and presented on a corresponding one(s) of the display devices 112-1, 112-2, 112-3.

[0038] In certain embodiments, the exemplary display manager 118 is configured to process the virtual display bitmaps 116-1, 116-2, 116-3, taking into account geometrical and visual properties of each virtual display bitmap 116-1, 116-2, 116-3. Geometrical and visual properties include, but are not limited to, properties such as position, scale rotation, and transparency, as well as other desired properties.

[0039] In one embodiment, a single virtual display bitmap such as virtual display bitmap 116-3 corresponds to single mapped bitmap such as mapped bitmap 120-3. In this example, the mapped bitmap 120-3 is mapped 148 to a single hardware layer, which in this example is shown as hardware layer 128-3. In certain embodiments, mapping a single virtual display, such as virtual display 116-1, to a single hardware layer, such as hardware layer 128- 1, may improve advantages provided by the hardware compositor 108. As will be discussed further below, multiple hardware layers may be blended onto the same pixel region and displayed on the same display device. Blending multiple hardware layers onto the same pixel region is useful for example to support features such as picture in picture.

[0040] The processor 102 is configured to send 138 each mapped bitmap 120-1, 120-

2, 120-3 to the hardware compositor 108. A hardware compositor, such as the hardware compositor 108, is configured to accelerate basic data operations with multiple bitmap overlays in real time. The data operations performed by the hardware compositor 108 include operations such as bit-blitting, alpha blending, translating, scaling, rotating, etc. The use of the hardware compositor 108 is configured to result in better performance and lower power consumption than solutions based on a graphics processing unit, a processor, or a CPU. [0041] The hardware compositor 108 is configured to composite 140 an output of each virtual machine 114-1, 114-2, 114-3 to create a final image in a framebuffer 122. Predetermined pixel regions 124-1, 124-2, 124-3 of the framebuffer 122 are associated with a corresponding hardware layer 128-1, 128-2, 128-3. The hardware compositor 108 is configured to composite each mapped bitmap 120-1, 120-2, 120-3 into the corresponding pixel region 124-1, 124-2, 124-3.

[0042] The exemplary embodiments include a hardware based display controller 110 configured to process 142 video content from the framebuffer 122 and present the video content on a plurality of displays 112-1, 112-2, 112-3. The display controller 110 is configured to read 142 the frame buffer 122, along with the included pixel regions 124-1, 124-2, 124-3, process the framebuffer 122 information, and present the processed framebuffer 122 data on the plurality of display devices 112-1, 112-2, 112-3, where the data from each pixel region 112124- 1, 124-2, 124-3 is displayed on a corresponding display device in the plurality of display devices 112-1, 112-2, 112-3. [0043] In the illustrated embodiment, the hardware compositor 108 is configured to composite a final image within a single framebuffer 122. The display controller 110 maps each pixel region 124-1, 124-2, 124-3 in the framebuffer 122 to relevant screen space on each display device 112-1, 112-2, 112-3 and signals each display device 112-1, 112-2, 112-3 to present their part of the final image.

[0044] Offloading of compositing of the framebuffer 122 to a dedicated hardware compositor 108 increases availability of the graphics processing unit 106 for rendering and other generic purpose computations. Employing the hardware compositor 108 and a single framebuffer 122 as described above can reduce the number of processors or SoC devices required in large systems based on multiple SoC devices.

[0045] In certain embodiments, it is desirable to combine multiple virtual display bitmaps 116-1, 116-2, 116-3 onto a single display device, such as display device 112-1, to support features such as picture in picture. Each virtual display bitmap 116-1, 116-2, 116-3 is mapped to a corresponding one hardware layer 128-1, 128-2, 128-3 then one or more hardware layers may be blended or composited onto a single pixel region 124-1. The pixel region 124- 1 is then displayed on a corresponding display device 112-1. In the exemplary embodiment, blending or compositing of multiple hardware layers onto a single pixel region may be efficiently accelerated by the hardware compositor 108.

[0046] It is instructive to consider how the exemplary embodiment described above may, for example, display a full sized virtual display bitmap 116-1 along with a reduced size virtual display bitmap 116-1, on a single pixel region 124-1 or a single display device 112-1. The first virtual display bitmap 116-1 is mapped to a first hardware layer 128-1, and the first virtual display bitmap 116-1 is also mapped to a second hardware layer 128-2. The hardware compositor 108 is used to apply hardware accelerated down scaling and translation to the second hardware layer 128-2 to create a reduced size and re-positioned image. Down scaling reduces the size, as measured in pixels, of the second hardware layer 128-2. Translation is used to locate the down scaled image within a desired portion of the first pixel region 124-1. The foregoing described mapping and blending or compositing results in a reduced size versions of the first virtual display bitmap 116-1 begin superimposed on the same physical display as a full size version of the first virtual display bitmap 116-1. In this fashion, any desired combination of virtual display bitmaps 116-2, 116-2, 116-3, may be blended onto one or more pixel regions 124-1, 124-2, 124-4, to be displayed on one or more display devices 112- 1, 112-2, 112-3. The computing apparatus 100 may be advantageously employed in many modern devices that incorporate multiple software applications that generate visual content to drive multiple computer displays. Apparatus that may gain advantage from the use of the apparatus 100 include but are not limited to automobiles and mobile communication devices.

[0047] In one embodiment, it is beneficial to blend a plurality of hardware layers 128-

1, 128-2, 128-3 where each hardware layer is associated with a different virtual display bitmap 116-1, 116-2, 116-3 onto plurality of pixel regions 124-1, 124-2, 124-3 each of which correspond to a different display device in the plurality of display devices 112-1, 112-2, 112- 3. This is useful for mixing video content of different virtual machines onto different physical displays in different combinations.

[0048] Referring to Figure 2, there can be seen a flow chart illustrating an exemplary method 250 for processing and displaying video content from multiple virtual machines in accordance with the aspects of the disclosed embodiments. The exemplary method 250 may be used to efficiently display video content from multiple applications, while reducing the overall cost of the necessary computing hardware. [0049] In one embodiment, the exemplary method 250 includes executing, at 200, a hypervisor by a processor or general purpose processing device. The hypervisor is configured to host, at 202, a plurality of virtual machines on a single computing platform or apparatus. One or more of the virtual machines will produce visual content that can be displayed on a corresponding display device.

[0050] To prepare visual content for display, the exemplary method 250 further includes each virtual machine sending, at 204, rendering commands to a graphics processing unit. The graphics processing unit may be any suitable graphics processing unit, such as the graphics processing unit 106 described above and with respect to Figure 1, configured to efficiently generate bitmaps from rendering commands.

[0051] The exemplary method 250 further includes the graphics processing unit generating, at 206, or rendering, virtual display bitmaps based on the received rendering commands and returning the generated virtual display bitmaps where it is received, at 208, by the associated virtual machine. In this way, the exemplary method 250 creates a plurality of virtual display bitmaps corresponding to each virtual machine in a plurality of virtual machines.

It is instructive to view each virtual machine as having its own virtual display where a virtual display bitmap represents one frame of video for the associated virtual display.

[0052] In one embodiment, the method 250 includes processing each virtual display bitmap of a plurality of virtual display bitmaps. Each virtual display bitmap is mapped with a desired hardware layer of a plurality of hardware layers where each hardware layer corresponds to a pixel region in a plurality of pixel regions. Processing, at 210, the virtual display bitmaps takes into account geometrical and visual properties of each virtual display bitmap. The geometrical and visual properties may include properties such as position, scale, rotation, and transparency of each virtual display bitmap as well as other suitable properties as desired. [0053] As described herein, the processing 210 and mapping of the virtual display bitmaps produces a plurality of mapped bitmaps. In one embodiment, there is a one to one correspondence between virtual display bitmaps and hardware layers. Alternatively, it may be desirable to map two or more virtual display bitmaps to one hardware layer. Mapping two or more virtual display bitmaps to one hardware layer may be desirable, for example, when supporting features such as picture in picture. As discussed above, any desired mapping of virtual display to hardware layer may be advantageously employed, and multiple hardware layers may be blended or composited onto the same pixel region and displayed on the same display device. Blending multiple hardware layers onto the same pixel region is useful, for example, to support features such as picture in picture.

[0054] The plurality of mapped bitmaps is sent, at 212, to a hardware compositor. The exemplary method 250 further includes the hardware compositor compositing, at 214, the plurality of mapped bitmaps to create a final image and populating, at 216, the final image into a framebuffer. The framebuffer includes a plurality of pixel regions, where each pixel region corresponds to a display device in a plurality of display devices. Each pixel region is populated based on the mapping, at 210, between virtual display bitmaps and hardware layers. The final image is populated, at 216, in the framebuffer and is processed, at 218, by a display manager which presents each pixel region in the framebuffer on a corresponding display device of a plurality of display devices. [0055] In one embodiment, the compositing, at 214, of the mapped bitmaps includes performing data operations on the plurality of mapped bitmaps. The data operations may include operations such as bit-blitting, alpha blending, translating, scaling, and rotating, or other suitable data operations as desired. [0056] In certain embodiments, it is advantageous to execute the display manager within the computing context of the hypervisor. Executing the display manager within a hypervisor context allows the display manager to coordinate processing of visual content from multiple virtual machines to create a consistent mapping of visual content to the actual display devices.

[0057] The aspects of the disclosed embodiments are directed to efficient multi-display two-dimensional compositing in virtualized environments using a single system-on-chip. The aspects of the disclosed embodiments significantly reduce the amount of graphics processing that virtual machines running under hypervisor control might require when displaying visual content on a plurality of dedicated physical display devices. The computing apparatus of the disclosed embodiments is configured for efficiently displaying graphics on a plurality of displays generated from multiple computer applications executing on one or more virtual machines.

[0058] Thus, while there have been shown, described and pointed out, fundamental novel features of the invention as applied to the exemplary embodiments thereof, it will be understood that various omissions, substitutions and changes in the form and details of devices and methods illustrated, and in their operation, may be made by those skilled in the art without departing from the spirit and scope of the presently disclosed invention. Further, it is expressly intended that all combinations of those elements, which perform substantially the same function in substantially the same way to achieve the same results, are within the scope of the invention. Moreover, it should be recognized that structures and/or elements shown and/or described in connection with any disclosed form or embodiment of the invention may be incorporated in any other disclosed or described or suggested form or embodiment as a general matter of design choice. It is the intention, therefore, to be limited only as indicated by the scope of the claims appended hereto.