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Title:
ARCITECTURE, STRUCTURE, METHOD AND MEMORY ARRAY FOR 3D FeFET TO ENABLE 3D FERROELETRIC NONVOLATILE DATA STORAGE
Document Type and Number:
WIPO Patent Application WO/2022/082743
Kind Code:
A1
Abstract:
A new cell structure to implement 3D ferroelectric field effect transistor (FeFET) to enable 3D ferroelectric nonvolatile data storage is presented to increase data storage density and reduce memory bit cost. The 3D FeFET is a vertical gate all around transistor with recessed ferroelectric gate oxide to achieve nonvolatility in a 4F2 cell footprint, where F is the minimum processing size. In the new cell structure, cross point array is employed with perpendicular bit lines (BL) (101a, 101b, 101c) and perpendicular word lines (WL) (102a, 102b, 102c), and can be stacked in two or more decks (111, 112, 113) with the 3D FeFET memory cells to enable an effective cell size of 2F2 in two decks and 1F2 in four decks.

Inventors:
LIU JUN (CN)
Application Number:
PCT/CN2020/123293
Publication Date:
April 28, 2022
Filing Date:
October 23, 2020
Export Citation:
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Assignee:
YANGTZE ADVANCED MEMORY IND INNOVATION CENTER CO LTD (CN)
International Classes:
G11C11/22
Foreign References:
CN111758171A2020-10-09
CN111048521A2020-04-21
JP2008066603A2008-03-21
Attorney, Agent or Firm:
NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD. (CN)
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