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Title:
ARITHMETIC DEVICE AND PRODUCT-SUM ARITHMETIC SYSTEM
Document Type and Number:
WIPO Patent Application WO/2020/255599
Kind Code:
A1
Abstract:
This arithmetic device has first and second arithmetic circuit units. A product-sum signal output from a plurality of output lines of the first arithmetic circuit unit or a signal generated on the basis of the product-sum signal is input to a plurality of input lines of the second arithmetic circuit unit. The extending directions of the plurality of input lines of the first arithmetic circuit unit and the extending directions of the plurality of output lines of the second arithmetic circuit unit are parallel to each other. Assuming that ends on the second arithmetic circuit unit side of two farthest-end output lines of the first arithmetic circuit unit are defined as first and second ends, and ends on the first arithmetic circuit unit side of two farthest-end input lines of the second arithmetic circuit unit are defined as third and fourth ends, the position of at least one of the first end or the second end in a first direction is the position between the position of the third end and the position of the fourth end. Alternatively, the position of at least one of the third end or the fourth end in the first direction is the position between the position of the first end and the position of the second end.

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Inventors:
FUJINAMI YASUSHI (JP)
Application Number:
PCT/JP2020/019388
Publication Date:
December 24, 2020
Filing Date:
May 15, 2020
Export Citation:
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Assignee:
SONY CORP (JP)
International Classes:
G06G7/14; G06G7/16; G06G7/60; G06N3/063
Domestic Patent References:
WO2018034163A12018-02-22
Foreign References:
JPH0451382A1992-02-19
JPH06251176A1994-09-09
Attorney, Agent or Firm:
OMORI, Junichi (JP)
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