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Patent Searching and Data


Title:
ASYNCHRONOUS SAMPLING ARCHITECTURE AND CHIP
Document Type and Number:
WIPO Patent Application WO/2021/042266
Kind Code:
A1
Abstract:
An asynchronous sampling architecture (100) and a chip. The asynchronous sampling architecture (100) is used for receiving a first input data string (dl) from the opposite end, and comprises: a first register (102) used for caching the first input data string (dl), the first input data string (dl) being written into the first register (102) according to an opposite clock (CLK_P) on the opposite end; and a gated clock generation unit (106) used for generating a gated clock (CLK_G), wherein the frequency of the gated clock (CLK_G) is the same as that of the opposite clock (CLK_P); the first input data string (dl) is read from the first register (102) as a first output data string (d1ff) according to the gated clock (CLK_G).

Inventors:
WANG WEN-CHI (CN)
WANG HSIN-MIN (CN)
LIU JU-CHIEH (CN)
Application Number:
PCT/CN2019/104220
Publication Date:
March 11, 2021
Filing Date:
September 03, 2019
Export Citation:
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Assignee:
SHENZHEN GOODIX TECH CO LTD (CN)
International Classes:
H03L7/00
Foreign References:
CN103425614A2013-12-04
CN103425614A2013-12-04
CN103427835A2013-12-04
CN101303643A2008-11-12
CN102347830A2012-02-08
CN101329589A2008-12-24
Other References:
See also references of EP 3809597A4
Attorney, Agent or Firm:
TIANTAI LAW FIRM (CN)
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