[0001] This relates generally to modulation for data transmission, and more particularly to binary frequency shift keying modulation.

BACKGROUND

[0002] Binary frequency shift keying (BFSK) is a form of data modulation commonly used in communications technologies. For example, transmit architectures for implementing the USB Power Delivery (USBPD) specification must use low power BFSK, and must comply with requirements including an eye diagram for frequency switching, an FCC transmit frequency spectrum, and a current budget for average transmit power. Such compliance may necessitate excessive architectural complexity, excessive circuit area and burdensome test, debug and validation requirements. FIGS. 1-3 (prior art) illustrate conventional approaches to implementation of the USBPD specification.

[0003] The architecture of FIG. 1 (square wave-to-triangle wave-to-class A driver) is conceptually simple, but introduces harmonics that require complex on-chip filtering, has high operating current requirements, and imposes difficulties in output amplifier control across PVT (process, voltage, temperature). The FIG. 2 architecture (direct digital synthesis) has a simple implementation and facilitates testing, but is less attractive with respect to power consumption and circuit area. The FIG. 3 architecture (PLL loop modulation) is conceptually simple, and is well-suited for low data rate switching, but imposes difficulty in meeting the eye diagram at a USBPD-compliant data rate (e.g., 320 kbps), and requires a considerable amount of time for design, test and calibration, especially with respect to controlling the PLL (phase locked loop) bandwidth.

SUMMARY

[0004] In described examples, binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency, and M is an integer. Depending on the binary data "1" or "0" to be transmitted, "M" or "M+l" clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used for generating N pulse width modulated phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize a sine waveform whose lower harmonics are substantially suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIGS. 1-3 (prior art) illustrate conventional transmit architectures.

[0006] FIG. 4 illustrates transmit architecture according to example embodiments.

[0007] FIG. 5 is a timing diagram that illustrates operation of the digital rate converter of FIG.

4 according to example embodiments.

[0008] FIG. 6 illustrates the digital rate converter of FIGS. 4 and 5 in more detail according to example embodiments.

[0009] FIG. 7 illustrates the transmit architecture of FIGS. 4-6 in more detail according to example embodiments.

[0010] FIG. 8 summarizes in tabular format frequency planning for the transmit architecture embodiments of FIGS. 4-7 according to example embodiments.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0011] Example embodiments implement BFSK modulation (such as to implement the USBPD specification) by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. Depending on the binary data "1" or "0" to be transmitted, "M" or "M+l" clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used for generating N pulse width modulated (PWM) phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize an output sine waveform. In some embodiments, significant harmonic content exists in the output sine waveform only at the (2*N-1) ^th harmonic and upwards, and this content can be attenuated using an external RC filter.

[0012] FIG. 4 illustrates transmit architecture according to example embodiments. In some embodiments, the components shown at 40-49 are provided on a single integrated circuit chip. A reference clock 41 drives a PLL 42 (a static integer divider PLL in some embodiments), which provides a high frequency clock 40 at (M+0.5)*fc. The clock 40 is input to a digital rate converter (DRC) 43 that converts M or M+l clock phases from the clock 40 to an intermediate clock 44 that is 2*N times faster than fc. The DRC 43 also receives (at 45) the data to be transmitted. M phases or clock edges from the clock 40 are converted to transmit a 1 , whereas M+l phases or clock edges are converted to transmit a 0. The intermediate clock 44, having the necessary modulation in it, is input to a digital phase generator 46 that uses the clock 44 to generate N pulse width modulated phases 47 of waveforms operating at the carrier frequency fc. The phases 47 are input to a driver 48 that performs harmonic rejection mixing, weighting the phases appropriately to synthesize an output sine waveform 49 whose only significant harmonics are at the (2*N-l)th and upward. These harmonics are attenuated by a filter 400. In some embodiments, the filter 400 is on-chip, whereas other embodiments use an external (off-chip) filter. In some embodiments, the filter 400 is a single pole RC filter. Some embodiments use the output impedance of the driver 48 as the R for the RC filter, such that C is the only extra passive component needed for the filter. Some embodiments use higher order filters for better harmonic rejection.

[0013] FIG. 5 is a timing diagram that illustrates operation of the DRC 43 of FIG. 4, with M=23 and N=8, according to example embodiments. The aforementioned conversion of M+l =24 phases from clock 40 (for data = 0, also referred to herein as Space) corresponds to clock signal clk f 1 , and the aforementioned conversion of M=23 phases from clock 40 (for data = 1, also refereed to herein as Mark) corresponds to clock signal clk_f2. The signal clk fl is produced by triggering pulses on the alternate rising and falling edges of clock 40, as shown at 51 in FIG. 5. The signal clk_f2 is produced in the same manner, with the exception of selected instances 50 when two consecutive pulses are triggered on consecutive rising edges of clock 40. Adjacent ones of the instances 50 are separated in time from one another by five of the aforementioned alternately triggered pulses.

[0014] With fc = 23.2 MHz for USBPD, clock 40 has a frequency of (23 + 0.5) x 23.2 = 545.2 MHz. For clk fl, M+l =24 pulses of clock 40 are converted to 16 (2N = 2 x 8) pulses. For clk_f2, M=23 pulses of clock 40 are converted to 16 pulses. Thus, clk fl has 16 pulses every 545.2/24 = 22.717 MHz, and clk_f2 has 16 pulses every 545.2/23 = 23.704 MHz. Noting that the deviation frequency, fd, of the USBPD specification has a range of 450-600KHz, the aforementioned 22.717 MHz (associated with clk fl) and 23.704 MHz (associated with clk_f2) rates respectively comply with the USBPD specification for Space (fc - fd) and Mark (fc + fd). The signal clk fl has 16 pulses within the time period l/(fc - fd), and the signal clk_f2 has 16 pulses within the time period l/(fc + fd). Thus, clk fl and clk_f2 are also referred to herein as "16x clocks." Solely for convenience of exposition, FIG. 5 shows only a single period length of each signal clk_fl and clk_f2. The frequency of clk fl is (545/24) x 16 = 363.4 MHz, and the frequency of clk_f2 is (545/23) x 16 = 379.3 MHz.

[0015] FIG. 6 illustrates the DRC 43 of FIGS. 4 and 5 in more detail according to example embodiments. As shown, clk fl and clk_f2 are produced by respectively corresponding logic portions 61 and 62 driven by the high frequency clock 40. A selector 63 selects clk fl or clk_f2 in response, respectively, to a Space (data = 0) or Mark (data = 1) indication received at 45.

[0016] FIG. 7 illustrates the transmit architecture of FIGS. 4-6 in more detail according to example embodiments. As shown, the digital phase generator 46 includes a 3-bit binary up/down counter 71 driven by the clock 44 provided by the selector 63 of the DRC 43. The output of the counter 71 drives a binary-to-thermometer code converter 72. The counter 71 counts pulses of the clock 44, and its 3 -bit binary count output 74 proceeds alternately upwardly and downwardly through a count range extending between 000 and 111, inclusive. The converter 72 converts each digital binary count value at 74 to a corresponding digital thermometer code representation at 47. This thermometer code representation corresponds to the aforementioned N (= 8 in the FIG. 7 example) PWM phases.

[0017] As shown in FIG. 7, some embodiments implement the driver 48 (see also FIG. 4) with a sine weighted digital-to-analog converter (DAC) 73 that performs harmonic rejection mixing, weighting the PWM phase signals at 47 appropriately to synthesize the sine waveform 49. The sine waveform 49 is configured as shown graphically in FIG. 7, irrespective of whether clk fl or clk_f2 is selected at 63. However, the positive and negative peaks have shorter time duration when (higher frequency) clk_f2 is selected than when (lower frequency) clk_fl is selected. This is so because: (a) the time spacing between each pair of consecutive pulses associated with each instance 50 (see FIG. 5) is smaller than the time spacing between any other pair of consecutive pulses in clk fl or clk_f2, and (b) the architecture is configured such that the consecutive pulses of alternate instances 50 correspond to consecutive downwardly proceeding binary count values 111 and 110 at 74, and the consecutive pulses of the remaining alternate instances 50 correspond to consecutive upwardly proceeding binary count values 000 and 001 at 74. In some embodiments, this correspondence between binary count values and the consecutive pulses of instances 50 is achieved by suitably initializing the binary count value 74.

[0018] Some embodiments apply dithering in the clk_f2 logic 62 (see FIG. 6) to vary the binary count values at 74 (see FIG. 7), to which the consecutive pulses of the instances 50 (see FIG. 5) correspond. Different dithering sequences result in different harmonic content in the output spectrum, which provides the advantageous capability of spreading the harmonics across the output frequency range. In some embodiments, the aforementioned dithering is provided as a selectable option, as indicated by broken line in FIG. 6, such that dithering may either be implemented or not as desired.

[0019] FIG. 7 further shows graphically the smoothed sine waveform produced by the filter 400, which attenuates the (2*N-l)th and higher harmonics, such as the 15 ^th and higher harmonics for the example of N = 8. In some embodiments, the frequency content of lower harmonics is less than -40dB (well within the USBPD specification requirement of less than -30dB). In some embodiments, the filter 400 provides extra -12dB at the 15 ^th harmonic.

[0020] FIG. 8 summarizes in tabular format the above-described transmit architecture frequency planning, for a reference clock example of 11.6 MHz and the example 545.2 MHz frequency for clock 40 (see also FIGS. 4-6).

[0021] The above-described transmit architecture (according to example embodiments) provides, among others, the following example advantages. Because the DRC 43 achieves the desired data modulation, with the required frequency deviation, entirely in the digital domain: complicated analog circuitry is avoided; test, debug and validation are facilitated; the modulation is resistant to PVT variation; and trim is limited to the PLL and driver. In some embodiments, the PLL is a conventional design that is easily implemented. Because the carrier is generated from the intermediate clock 44 (i.e., one of the 16x clocks), the architecture is simplified, avoiding high bandwidth on-chip filters and driver amplifiers, thereby helping to meet the required current budget and transmit spectrum mask. Clean transitions between symbols easily meet the required USBPD eye diagram. The architecture is open loop except for the PLL, which (as noted above) may be conventional (and thus a well-defined closed loop system). The open loop characteristics make the architecture stable and robust. Some embodiments require: less than 400 digital logic gates running at 372 and 545 MHz, with worst case dynamic current around 1 mA; PLL current around 1 mA; and total driver current around 7 mA.

[0022] Although portions of the foregoing description relate to embodiments used in the context of a USBPD application, various embodiments are used in various applications other than USBPD.

[0023] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.