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Title:
BIT LINE AND COMPARE VOLTAGE MODULATION FOR SENSING NONVOLATILE STORAGE ELEMENTS
Document Type and Number:
WIPO Patent Application WO/2015/053919
Kind Code:
A4
Abstract:
In a block of non-volatile memory, bit line current increases with bit line voltage. For current sensing memory systems, average bit line current during a sensing operation need only exceed a certain threshold amount in order to produce a correct result. For the first word lines being programmed in a block, memory cells connected thereto see relatively low bit line resistances during verify operations. In the disclosed technology, verify operations are performed for these first programmed word lines with lower verify bit line voltages in order to reduce excess bit line current and save power. During read operations, this scheme can make threshold voltages of memory cells connected to the lower word lines appear lower. In order to compensate for this effect, various schemes are disclosed.

Inventors:
DUNGA MOHAN V (US)
HIGASHITANI MASAAKI (US)
Application Number:
PCT/US2014/056403
Publication Date:
June 18, 2015
Filing Date:
September 18, 2014
Export Citation:
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Assignee:
SANDISK TECHNOLOGIES INC (US)
International Classes:
G11C16/34; G11C5/14; G11C7/12; G11C11/56; G11C16/24; G11C16/26
Attorney, Agent or Firm:
MAGEN, BURT (575 Market Street Suite 375, San Francisco California, US)
Download PDF:
Claims:
64

AMENDED CLAIMS

received by the International Bureau on 03 March 2015 (03.03.15)

We claim:

Ϊ A method for operating non-volatile storage, comprising:

applying a first set of one or more bit line voltages to a plurality of bit lines;

verifying programming for non-volatile storage elements connected to a first set of word lines and the plurality of bit lines in response to the first set of one or more bit line voltages;

applying a second set of one or more bit line voltages to the plurality of bit lines, the first set of one or more bit line voltages are lower than the second set of one or more bit line voltages;

verifying programming for non-volatile storage elements connected to a second set of word lines and the plurality of bit lines in response to the second set of one or more bit line voltages, the non-volatile storage elements connected to the first set of word lines are programmed prior to the programming of the nonvolatile storage elements connected to the second set of word lines after a common erasing, the non-volatile storage elements connected to the first set of word lines and the non-volatile storage elements connected to the second set of word lines are in a common block;

applying one or more read bit line voltages to the plurality of bit lines; and

reading the non-volatile storage elements connected to the first set of word lines and the plurality of bit lines in response to the one or more read bit line voltages, either the verifying programming for non-volatile storage elements connected to the first set of word lines or the reading the non-volatile storage elements connected to the first set of word lines includes applying a compare voltage to a selected word line for a data state on the first set of word lines that is different than another compare voltage for the data state used, for non-volatile storage elements connected to the second set of word lines. 65

2. The method of claim 1, wherein:

the first set of word lines comprise a first zone of word lines in the common block;

the second set of word lines comprise a second zone of word lines in in the common block, the first zone is closer to a source line than the second zone; and

the one or more read bit line voltages are different than the first set of one or more bit line voltages.

3. The method of claim 2, further comprising:

re-applying the one or more read bit line voltages to the plurality of bit lines; and

reading the non-volatile storage elements connected to the second set of word lines and the plurality of bit lines in response to the re-applying the one or more read bit line voltages, the second set of one or more bit line voltages consists of one specific bit line voltage, the one or more read bit line voltages also consists of the one specific bit line voltage.

4. The method of claim 1, wherein.

the verifying programming for non-volatile storage elements connected to the first set of word includes applying the compare voltage for the data state, wherein the compare voltage is higher than the another compare voltage for the data state used for non-volatile storage elements connected to the second set of word lines; and

the one or more read bit line voltages are different that first set of one or more bit line voltages.

5. The method of claim 1, wherein: 66

the reading the non-volatile storage elements connected to the first set of word lines includes applying the compare voltage for the data state, wherein the compare voltage is lower than the another compare voltage for the data state used for non-volatile storage elements connected to the second set of word lines; and the one or more read bit line voltages are different that first set of one or more bit line voltages.

6. The method of claim 1, wherein:

the first set of one or more bit line voltages remain constant during the verifying prograniming for the non-volatile storage elements connected to the first set of word lines; and

the one or more read bit line voltages remain constant during the reading the non-volatile storage elements connected to the first set of word lines.

7. The method of claim 1 , further comprising:

applying a third set of one or more bit line voltages to the plurality of bit lines; and

verifying programming for non-volatile storage elements connected to a third set of word lines and the plurality of bit lines in response to the third set of one or more bit line voltages, the first set of one or more bit line voltages are lower than the third set of bit lines voltages, the third set of one or more bit line voltages are lower than the second set of bit lines voltages.

8. The method of claim 7, wherein:

the verifying programming for non-volatile storage elements connected to the second set of word lines includes applying a first verify compare voltage to the second set of word lines for a first state;

the verifying programming for non-volatile storage elements connected to the first set of word lines includes applying the first verify compare, voltage plus a first offset to the first set of word lines for the first state; and the verifying programming for non-volatile storage elements connected to the third set of word lines includes applying the first verify compare voltage plus a second offset to the third set of word lines for the first state.

9. The method of claim S, further comprising:

determining whether non-volatile storage elements connected to said first set of word lines, said second set of word lines and said third set of word lines are programmed; and

if non- olatile storage elements connected to said first set of word lines, said second set of word lines and said third set of word lines are programmed, then:

reading the non-volatile storage elements connected to the second set of word lines and the plurality of bit lines in response to the one or more read bit line voltages, and

reading the non-volatile storage elements connected to the third set of word lines and the plurality of bit lines in response to the one or more read bit line voltages, the one or more read bit line voltages are the second set of one or more bit line voltages.

10. The method of claim 8, further comprising:

determining whether non-volatile storage elements connected to said first set of word lines, said second set of word lines and said third set of word lines are programmed; and

if non-volatile storage elements connected to said first set of word lines and third set of word lines are programmed but non-volatile storage elements connected to said second set of word lines are not programmed, then:

reading the non-volatile storage elements connected to the third set of word lines and the plurality of bit lines in response to the one or more read bit line voltages, the one or more read bit line voltages are the third set of one or more bit line voltages, the reading of the non-volatile storage elements connected to the third set of word line and the reading of the non-volatile storage elements connected to the first set of word lines includes applying a read compare voltage to the selected word line for the first data state plus the second offset.

11. The method of claim 8, further comprising:

detenni ing whether non-volatile storage elements connected to said first set of word lines, said second set of word lines and said t ird set of word lines are programmed, if non- volatile storage elements connected to said first set of word lines are programmed but non- olatile storage elements connected to said second set of word lines and third set of word lines are not programmed, then the one or more read bit line voltages are the first set of one or more bit line voltages and the reading of the non-volatile storage elements connected to the first set of word lines includes applying a read compare voltage to the selected word line for the first data state plus the first offset

12. The method of claim 9, further comprising:

if non-volatile storage elements connected to said first set of word lines and third set of word lines are programmed but non-volatile storage elements connected to said second set of word lines are not programmed, then reading the non-volatile storage elements connected to the third set of word lines and the plurality of bit lines in response to applying one or more read bit line voltages, the one or more read bit line voltages are the third set of one or more bit line voltages, the reading of the non-volatile storage elements connected to the third set of word line and the reading of the non-volatile storage elements connected to the first set of word lines includes applying a read compare voltage to the selected word line for the first data state plus the second offset;

if non-volatile storage elements connected to said first set of word lines are programmed but non-volatile storage elements connected to said second set of word lines and third set of word lines are not programmed, then the one or more read bit line voltages are the first set of one or more bit line voltages and 69

the reading of the non-volatile storage elements connected to the first set of word lines includes applying a read compare voltage to the selected word line for the first data state plus the first offset.

13. A non-volatile storage apparatus, comprising:

a plurality of non-volatile storage elements,

a plurality of word lines including a first set of word lines and a second set of word lines, non-volatile storage elements connected to the first set of word lines and non-volatile storage elements connected to the second set of word lines are in a common block;

a plurality of bit lines connected to the non-volatile storage elements; and one or more managing circuits in communication with the plurality of bit lines and the plurality of word lines, the one or more managing circuits apply a first set of one or more bit line voltages to the plurality of bit lines, the one or more managing circuits verify programming for the non- volatile storage elements connected to the first set of word lines and the plurality of bit lines in response to the first set of one or more bit line voltages, the one or more managing circuits apply a second set of one or more bit line voltages to the plurality of bit lines, the first set of one or more bit line voltages are lower than the second set of one or more bit line voltages, the one or more managing circuits verify programming for the non-volatile storage elements connected to the second set of word lines and the plurality of bit lines in response to the second set of one or more bit line voltages, the non-volatile storage elements connected to the first set of word lines are programmed prior to the non-volatile storage elements connected to the second set of word lines after a common erasing, the one or more managing circuits apply one or more read bit line voltages to the plurality of bit lines, the one or more managing circuits read the non-volatile storage elements connected to the first set of word lines and the plurality of bit lines in response to the one or more read bit line voltages, either the verifying programming for non-volatile storage elements connected to the first set of word lines or the reading the non- 70

volatile storage elements connected to the first set of word lines includes applying a compare voltage to a selected word line for a data state on the first set of word lines that is different than another compare voltage for the data state used for nonvolatile storage elements connected to the second set of word lines,

14. The non-volatile storage apparatus of claim 13, wherein:

the one or more managing circuits re-apply the one or more read bit line voltages to the plurality of bit lines and read the non-volatile storage elements connected to the second set of word lines and the plurality of bit lines in response to the re-applying the one or more read bit line voltages, the second set of one or more bit line voltages consists of one specific bit line voltage, the one or more read bit line voltages also consists of the one specific bit line voltage.

15. The non-volatile storage apparatus of claim 13, wherein:

the verifying programming for non-volatile storage elements connected to the first set of word includes the one or more managing circuits applying the compare voltage for the data state, wherein the compare voltage is higher than the another compare voltage for the data state used for non-volatile storage elements connected to the second set of word lines, the one or more read bit line voltages are different that first set of one or more bit line voltages.

16. The non-volatile storage apparatus of claim 13, wherein:

the reading the non-volatile storage elements connected to the first set of word lines includes the one or more managing circuits applying the compare voltage for the data state, wherein the compare voltage is lower than the another compare voltage for the data state used for non-volatile storage elements connected to the second set of word lines, the one or more read bit line voltages are different that first set of one or more bit line voltages.

17. The non-volatile storage apparatus of claim 13, wherein: 71

the plurality of word lines including a third set of word lines; and the one or more managing circuits apply a third set of one or more bit line voltages to the plurality of bit lines and verify programming for non-volatile storage elements connected to the third set of word lines and the plurality of bit lines in response to the third set of one or more bit line voltages, the first set of one or more bit line voltages are lower than the third set of bit lines voltages, the third set of one or more bit line voltages are lower than the second set of bit lines voltages.

18. The non-volatile storage apparatus of claim 17, wherein:

the verifying programming for non- volatile storage elements connected to the second set of word lines includes the one or more managing circuits applying a first verify compare voltage to the second set of word lines for a first state;

the verifying programming for non-volatile storage elements connected to the first set of word lines includes the one or more managing circuits applying the first verify compare voltage plus a first offset to the first set of word lines for the first state; and

the verifying programming for non-volatile storage elements connected to the third set of word lines includes the one or more managing circuits applying the first verify compare voltage plus a second offset to the second set of word lines for the first state.

1 . The non-volatile storage apparatus of claim 18, wherein:

the one or more managing circuits detennine whether non-volatile storage elements connected to said first set of word lines, said second set of word lines and said third set of word lines are programmed; and

if non-volatile storage elements connected to said first set of word lines, said second set of word lines and said third set of word lines are programmed, then; 72

the one or more managing circuits read the non-volatile storage elements connected to the second set of word lines and the plurality of bit lines in response to the one or more read bit line voltages and read the non-volatile storage elements connected to the third set of word lines and the plurality of bit lines in response to the one or more read bit line voltages, the one or more read bit line voltages are the second set of one or more bit line voltages.

20. The non-volatile storage apparatus of claim 18, wherein:

the one or more managing circuits determine whether non-volatile storage elements connected to said first set of word lines, said second set of word lines and said third set of word lines are programmed; and

if non-volatile storage elements connected to said first set of word lines and third set of word lines are programmed but non-volatile storage elements connected to said second set of word lines are not programmed, then the one or more managing circuits read the non-volatile storage elements connected to the third set of word lines and the plurality of bit lines in response to the one or more read bit line voltages, the one or more read bit line voltages are the third set of one or more bit line voltages, the reading of the non- volatile storage elements connected to the third set of word line and the reading of the non-volatile storage elements connected to the first set of word lines includes applying a read compare voltage for the first data state plus the second offset.

21. The non-volatile storage apparatus of claim 18, wherein:

the one or more managing circuits determine whether non-volatile storage elements connected to said first set of word lines, said second set of word lines and said third set of word lines are programmed, if non-volatile storage elements connected to said first set of word lines are programmed but non-volatile storage elements connected to said second set of word lines and third set of word lines are not programmed, then the one or more read bit line voltages are the first set of one or more bit line voltages and the reading of the non-volatile storage 73

elements connected to the first set of word lines includes the one or more managing circuits applying a read compare voltage for the first data state plus the first offset.

22 , The non-volatile storage apparatus of claim 18, wherein:

the one or more managing circuits determine whether non-volatile storage elements connected to said first set of word lines, said second set of word lines and said third set of word lines are programmed;

if non-volatile storage elements connected to said first set of word lines and third set of word lines are programmed but non-volatile storage elements connected to said second set of word lines are not programmed, then the one or more managing circuits read the non-volatile storage elements connected to the third set of word lines in response to applying the one or more read bit line voltages, the one or more read bit line voltages are the third set of one or more bit line voltages, the reading of the non-volatile storage elements connected to the third set of word line and the reading of the non-volatile storage elements connected to the first set of word lines includes applying a read compare voltage for the first data state plus the second offset; and

if non-volatile storage elements connected to said first set of word lines are programmed but non-volatile storage elements connected to said second set of word lines and third set of word lines are not programmed, then the one or more read bit line voltages are the first set of one or more bit line voltages and the reading of the non-volatile storage elements connected to the first set of word lines includes applying a read compare voltage for the first data state plus the first offset.