TECHNICAL FIELD

The present disclosure relates generally to the field of communication involving a user equipment served by a cell of a communication network. More particularly, it relates to generation of a bit sequence to be used in such communication.

BACKGROUND

Various bit sequences may be used for communication involving a user equipment served by a cell of a communication network. For example, a bit sequence may be used for scrambling in a transmitter and de-scrambling in a receiver. Possible example purposes of bit scrambling include that transmitted signals are not to disturb unintended receivers more than random noise would, and making it more difficult for an unintended receiver to discern the transmitted message.

Bit scrambling may be applied, for example, in communication compliant with Third Generation Partnership Project (3GPP) third generation (3G), fourth generation (4G), or fifth generation (5G; e.g., new radio - NR).

An example scrambling sequence for 5G NR is described in Third Generation Partnership Project (3GPP) Technical Specification (TS) 38.211 Section 5.2.1. This scrambling sequence is typically calculated by both the transmitter (e.g., for scrambling before the signal is mapped to the modulation constellation) and the receiver (e.g., for un-scrambling, or de-scrambling, of the received sequence after soft constellation de-mapping).

The scrambling sequence c(n) of 3GPP TS 38.211 is a Gold sequence; defined as the bit-wise modulo two sum of two m-sequences, x ₁ and x ₂ : c(n) = (x ₁ (n + 1600) + x ₂ (n + 1600)) mod 2,

X ₁ (n + 31) = (x ₁ (n + 3) + x1(n) mod 2, n > 30, and x ₂ (n + 31) = (x ₂ (n + 3) + x ₂ (n + 2) + x ₂ (n + 1) + x ₂ (n)) mod 2, n > 30, with initial conditions

The scrambling seed c _init is derived from parameters that are known to both the transmitter and the receiver and typically results in that different transmissions use different scrambling sequences. In the case of the physical downlink shared channel (PDSCH), it is defined as ^c init = ⁿ RNTi ’ 2 ¹⁵ + q ^. 2 ¹⁴ + n _ID , where n _RNTI is a 16-bit Radio Network Temporary Identifier (RNTI) that is typically different for different user equipments (UEs), q G {0,1}, and n _ID G {0, ... ,1023} is typically a value shared by at least some UEs (e.g., all UEs in a same area; such as a cell). The notation x ₂ is used herein for the x ₂ sequence generated by the seed value c _init .

The length of the scrambling sequence c(n) depends on the kind of transmission it is applied to. In 5G NR, the longest required sequence is for transmission on PDSCH when using the maximum number of spatial layers and the largest modulation constellation. Thus, in a typical scenario, an upper limit of the length of the scrambling sequence can be obtained by assuming 256-QAM (quadrature amplitude modulation), four spatial layers, 273 PRBs (physical resource blocks, e.g., 12 carriers over one slot), and 14 data OFDM (orthogonal frequency division multiplexing) symbols with no DMRS (demodulation reference symbol) overhead; resulting in an upper limit of the length of the scrambling sequence of (log ₂ (256)) x 4 x 12 x 273 x 14 = 1467648 bits.

The amount of processing required for sequence generation in general typically increases with the length of the sequence. Thus, for relatively long sequences, the amount of processing may be substantial. For example, when the amount of processing is manifested in terms of required time for sequence generation, the sequence generation may introduce substantial and/or unacceptable processing latency.

Therefore, there is a need for alternative approaches to sequence generation in general (and preferably suitable for the scrambling sequences of 3GPP TS 38.211 Section 5.2.1). Preferably, the alternative approaches provide improvement compared to other sequence generation approaches. Improvement may, for example, be in terms of reduced required time and/or reduced latency for sequence generation.

SUMMARY

It should be emphasized that the term "comprises/comprising" (replaceable by "includes/including") when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Generally, when an arrangement is referred to herein, it is to be understood as a physical product; e.g., an apparatus. The physical product may comprise one or more parts, such as controlling circuitry in the form of one or more controllers, one or more processors, or the like.

It is an object of some embodiments to solve or mitigate, alleviate, or eliminate at least some of the above or other disadvantages.

A first aspect is a method for generation of a resulting bit sequence for use in communication involving a user equipment served by a cell of a communication network. The resulting bit sequence is based on a first constituent sequence, the first constituent sequence being defined by recursion based on a seed with dynamic value.

The method comprises (for a relevant seed value comprising first and second constituent seed values, and for each desired bit position of the resulting bit sequence) acquiring a first bit value for a corresponding bit position of a pre-stored intermediate sequence, acquiring a second bit value for each of one or more shifted positions of a pre-stored version of the first constituent sequence, and determining a bit value of the desired bit position of the resulting bit sequence as a sum of the first bit value and the one or more second bit values.

The pre-stored intermediate sequence is based on the first constituent sequence for the first constituent seed value. The pre-stored version of the first constituent sequence is for a single-bit seed value which has a single non-zero bit.

Each of the one or more shifted positions is determined by the desired bit position, the position of the non-zero bit of the single-bit seed value, and the position of a non-zero bit of the second constituent seed value.

In some embodiments, the method further comprises using the resulting bit sequence in communication involving the user equipment.

In some embodiments, the use of the resulting bit sequence comprises one or more of: scrambling and/or descrambling of data conveyed by the communication, cyclic redundancy checking of data conveyed by the communication, and generating demodulation reference signals conveyed by the communication.

In some embodiments, the method further comprises organizing the desired bit positions into two or more disjunct groups, and the generation of the resulting bit sequence is performed in parallel for the groups.

In some embodiments, the method further comprises - for at least one group - pre-acquiring a corresponding portion of the pre-stored version of the first constituent sequence for the single-bit seed value, and the second bit values are acquired from the pre-acquired portion of the pre-stored version of the first constituent sequence for the single-bit seed value.

In some embodiments, the desired bit positions correspond to a collection of adjacent bits of the resulting bit sequence, and the method further comprises (for each further bit position of the resulting bit sequence) recursively determining a further bit value of the first constituent sequence, and determining the bit value of the further bit position of the resulting bit sequence based on the further bit value of the first constituent sequence.

A second aspect is a method for preparation of generation of a resulting bit sequence for use in communication involving a user equipment served by a cell of a communication network. The resulting bit sequence is based on a first constituent sequence, the first constituent sequence being defined by recursion based on a seed with dynamic value. A seed value comprises first and second constituent seed values. The method comprises determining (for each of one or more first constituent seed values) an intermediate sequence which is based on the first constituent seed value, determining (for a single-bit seed value, wherein the single-bit seed value has a single non-zero bit) a version of the first constituent sequence, and causing storage of the one or more intermediate sequences and of the version of the first constituent sequence, for subsequent generation of the resulting bit sequence.

In some embodiments, the method further comprises repeating the determination and the causing of storage of the intermediate sequence when a change of the first constituent seed value is detected.

In some embodiments, the method further comprises the method of the first aspect.

In some embodiments of the first and/or second aspects, the first constituent sequence is compliant with one or more of: a superposition principle according to which a sum of first constituent sequences of first and second seed values is equal to the first constituent sequence of a sum of the first and second seed values, and a shift principle according to which first constituent sequences of first and second single-bit seed values are shifted versions of each other, the shift corresponding to a difference between positions of the non-zero bit of the first and second single-bit seed values.

In some embodiments of the first and/or second aspects, the resulting bit sequence is a Gold sequence and/or the first constituent sequence is an m-sequence.

In some embodiments of the first and/or second aspects, the resulting bit sequence is a bitwise sum of the first constituent sequence and a second constituent sequence, the second constituent sequence being fixed, and the intermediate sequence is a bit-wise sum of the second constituent sequence and the first constituent sequence for the first constituent seed value.

In some embodiments of the first and/or second aspects, the n ^th position of the resulting bit sequence is defined by c(n) = + 1600) + x ₂ (n + 1600)) modulo 2, the second constituent sequence x ₁ complies with x ₁ (0) = 1, x1(n) = 0 for n = 1,2, ...,30, and x ₁ (n + 31) = ( x ₁ (n + 3) + x1(n) modulo 2 for n > 30, and the first constituent sequence x ₂ complies with where c _init denotes the seed value, and x ₂ (n + 31) = (x ₂ (n + 3) + x ₂ (n + 2) + x ₂ (n + 1) + x1(n) modulo 2 for n > 30.

In some embodiments of the first and/or second aspects, the first constituent seed value has zero-valued bits in all positions corresponding to a first set of adjacent bits and/or is based on a cell identifier.

In some embodiments of the first and/or second aspects, the second constituent seed value has zero-valued bits in all positions corresponding to a second set of adjacent bits and/or is based on one or more of a user equipment identifier and a transport block identifier.

A third aspect is a computer program product comprising a non-transitory computer readable medium, having thereon a computer program comprising program instructions. The computer program is loadable into a data processing unit and configured to cause execution of the method according to any of the first and second aspects when the computer program is run by the data processing unit.

A fourth aspect is an apparatus for generation of a resulting bit sequence for use in communication involving a user equipment served by a cell of a communication network. The resulting bit sequence is based on a first constituent sequence, the first constituent sequence being defined by recursion based on a seed with dynamic value.

The apparatus comprises controlling circuitry configured to cause (for a relevant seed value comprising first and second constituent seed values, and for each desired bit position of the resulting bit sequence) acquisition of a first bit value for a corresponding bit position of a prestored intermediate sequence, acquisition of a second bit value for each of one or more shifted positions of a pre-stored version of the first constituent sequence, and determination of a bit value of the desired bit position of the resulting bit sequence as a sum of the first bit value and the one or more second bit values.

The pre-stored intermediate sequence is based on the first constituent sequence for the first constituent seed value.

The pre-stored version of the first constituent sequence is for a single-bit seed value which has a single non-zero bit. Each of the one or more shifted positions is determined by the desired bit position, the position of the non-zero bit of the single-bit seed value, and the position of a non-zero bit of the second constituent seed value.

In some embodiments, the apparatus further comprises parallel processing circuitry configured to perform the generation of the resulting bit sequence in parallel for two or more disjunct groups of desired bit positions.

In some embodiments, the parallel processing circuitry comprises a plurality of hardware processors, wherein each hardware processor is configured to perform generation of bits of the resulting bit sequence corresponding to the desired bit positions of one of the groups.

In some embodiments, the apparatus further comprises local storage associated with at least one of the hardware processors, wherein the local storage is configured to store the preacquired portion of the pre-stored version of the first constituent sequence for the single-bit seed value.

A fifth aspect is an apparatus for preparation of generation of a resulting bit sequence for use in communication involving a user equipment served by a cell of a communication network. The resulting bit sequence is based on a first constituent sequence, the first constituent sequence being defined by recursion based on a seed with dynamic value, wherein a seed value comprises first and second constituent seed values.

The apparatus comprises controlling circuitry configured to cause determination (for each of one or more first constituent seed values) of an intermediate sequence which is based on the first constituent seed value, determination (for a single-bit seed value, wherein the single-bit seed value has a single non-zero bit) of a version of the first constituent sequence, and storage of the one or more intermediate sequences and of the version of the first constituent sequence, for subsequent generation of the resulting bit sequence.

In some embodiments, the apparatus of the fifth aspect further comprises the apparatus of the fourth aspect.

A sixth aspect is a storage unit for generation of a resulting bit sequence for use in communication involving a user equipment served by a cell of a communication network. The resulting bit sequence is based on a first constituent sequence, the first constituent sequence being defined by recursion based on a seed with dynamic value, wherein a seed value comprises first and second constituent seed values.

The storage device is carrying (for each of one or more first constituent seed values) an intermediate sequence which is based on the first constituent seed value, and (for a single-bit seed value, wherein the single-bit seed value has a single non-zero bit) a version of the first constituent sequence.

A seventh aspect is a transmitter comprising the apparatus of any of the fourth and fifth aspects and/or the storage unit of the sixth aspect.

An eighth aspect is a receiver comprising the apparatus of any of the fourth and fifth aspects and/or the storage unit of the sixth aspect.

A ninth aspect is a communication device comprising one or more of: the apparatus of any of the fourth and fifth aspects, the storage unit of the sixth aspect, the transmitter of the seventh aspect, and the receiver of the eighth aspect.

In some embodiments, any of the above aspects may additionally have features identical with or corresponding to any of the various features as explained above for any of the other aspects.

An advantage of some embodiments is that alternative approaches to bit sequence generation are provided.

An advantage of some embodiments is that improvement is achieved compared to other bit sequence generation approaches, e.g., in terms of reduced required time for the bit sequence generation.

An advantage of some embodiments is that efficient parallelization of the bit sequence generation is enabled. Thereby, efficient hardware utilization may be achieved and/or the required time for sequence generation may be reduced compared to other bit sequence generation approaches. BRIEF DESCRIPTION OF THE DRAWINGS

Further objects, features and advantages will appear from the following detailed description of embodiments, with reference being made to the accompanying drawings. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the example embodiments.

Figure 1 is a flowchart illustrating example method steps according to some embodiments;

Figure 2 is a flowchart illustrating example method steps according to some embodiments;

Figure 3 is a schematic block diagram illustrating an example apparatus according to some embodiments;

Figure 4 is a schematic block diagram illustrating an example apparatus according to some embodiments;

Figure 5 is a schematic block diagram illustrating an example apparatus according to some embodiments; and

Figure 6 is a schematic drawing illustrating an example computer readable medium according to some embodiments.

DETAILED DESCRIPTION

As already mentioned above, it should be emphasized that the term "comprises/comprising" (replaceable by "includes/including") when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

Embodiments of the present disclosure will be described and exemplified more fully hereinafter with reference to the accompanying drawings. The solutions disclosed herein can, however, be realized in many different forms and should not be construed as being limited to the embodiments set forth herein. In the following, embodiments will be described for enabling and/or performing bit sequence generation; the bit sequence being a resulting bit sequence. The generated/resulting bit sequence is termed as "final bit sequence" in the following. The term "final" is not to be understood as if it is not possible that the bit sequence is further used and/or modified. In fact, the bit sequence is for use in communication, and it may typically be applied for processing of communication data/signals. Rather, the term "final" may be seen as a label; distinguishing the generated/resulting bit sequence from other sequences referred to (e.g., intermediate sequence and first/second constituent sequences).

Some embodiments provide improvement compared to other bit sequence generation approaches, e.g., in terms of reduced required time for the sequence generation.

Alternatively or additionally, some embodiments enable efficient parallelization of the sequence generation.

Some embodiments comprise performing the bit sequence generation, at least partly, in parallel.

Generally, the final bit sequence is based on a first constituent sequence, which is defined by recursion based on a primary seed (hereinafter denoted the seed) with dynamic value. Thus, the first constituent sequence may be a shift register sequence and/or as an m-sequence.

A dynamic value may, for example, be a value which may differ depending on the circumstances at hand (e.g., a value that may differ between one or more of: different transport blocks, different user equipments, different cells, etc.).

In some embodiments, the final bit sequence is a bit-wise sum of the first constituent sequence and a second constituent sequence, wherein the second constituent sequence is fixed. For example, the second constituent sequence may be defined by recursion based on a secondary seed with fixed value. Thus, the second constituent sequence may be a shift register sequence and/or as an m-sequence.

In some embodiments, the final bit sequence is a Gold sequence. For example, the final bit sequence may be the scrambling sequence c(n) of 3GPP TS 38.211 described above wherein the n ^th position of the final bit sequence is defined by c(n) 1600) + x ₂ (n + 1600)) modulo 2. Then, x ₂ may be considered as the first constituent sequence, wherein is the seed with dynamic value, and x ₁ may be considered as the second constituent sequence, wherein the fixed value of the secondary seed is defined by X1(0) = 1, x ₁ (n) = 0 for n = 1,2, ...,30.

Generally, a recursive expression for determining a value for a certain bit position of the first constituent sequence (or any other recursively defined sequence) may be seen as an interrelationship between values of a set of bit positions. The set of bit positions has two edge positions; the bit positions with highest and lowest indices in the set. In the example of the scrambling sequence c(n) of 3GPP TS 38.211, a recursive expression of determining a value for a certain bit position n + 31 of the first constituent sequence is x ₂ (n + 31) = (x ₂ (n + 3) + x ₂ (n + 2) + x ₂ (n + 1) + x ₁ (n)) modulo 2 for n > 30, a recursive expression of determining a value for a certain bit position n + 31 of the second constituent sequence is x ₁ (n + 31) = (x ₁ (n + 3) + x ₁ (n)) modulo 2 for n > 30, and the two edge positions are n and n + 31.

Some embodiments may be particularly suitable when the first constituent sequence is a so called jump sequence. It should be noted, however, that this is not a necessary condition for the first constituent sequence.

A possible definition of a jump sequence is that the recursive expression for determining a value for a certain bit position of the sequence excludes at least one collection of consecutive bit positions between the two edge positions, wherein the size of the excluded collection of consecutive bit positions exceeds a jump sequence threshold value. For example, the jump sequence threshold value may be defined in terms of a relation to the distance between the two edge positions. The relation to the distance between the two edge positions may, for example, be a fraction (such as 0.5, 0.75, 0.9, or any scaling value between 0.5 and 1) of the distance between the two edge positions. In the example of the scrambling sequence c(n) of 3GPP TS 38.211, the collection of consecutive bit positions is n + 4, ... , n + 30 for the first and second constituent sequences. This excluded collection has a size of 27, which is a substantial fraction of the distance 31 between the two edge positions.

In some embodiments, the first constituent sequence is compliant with a superposition principle according to which a sum of first constituent sequences of first and second seed values is equal to the first constituent sequence of a sum of the first and second seed values. Thus, for two different seed values a and b, the sum (modulo 2) of the corresponding first constituent sequences can be acquired as the first constituent sequence generated from a seed value c = a © b, wherein © denotes bit-wise exclusive-or. In the example of the scrambling sequence c(n) of 3GPP TS 38.211, this may be expressed by modulo 2.

Alternatively or additionally, the first constituent sequence is compliant with a shift principle in some embodiments, according to which first constituent sequences of first and second single-bit seed values are shifted versions of each other, the shift corresponding to a difference between positions of the non-zero bit of the first and second single-bit seed values. Thus, for two single-bit seed values 2 ^k and 2 ^m (each having a single non-zero element in position k and m, respectively), the corresponding first constituent sequences are shifted versions of each other. This means that the first constituent sequence corresponding to a single-bit seed value with non-zero element in position k can be acquired by shifting the first constituent sequence corresponding to a single-bit seed value with non-zero element in position m by k — m. In the example of the scrambling sequence c(n) of 3GPP TS 38.211, this may be expressed by or, equivalently, where k, m ∈ {{, ...,30}.

The seed value (i.e., a value for the seed with dynamic value) comprises first and second constituent seed values. The first constituent seed value may be a static or semi-static portion of the seed value, and the second constituent seed value may be a dynamic part of the seed value.

In some examples, the first constituent seed value may have zero-valued bits in all positions corresponding to a first set of adjacent bits and the second constituent seed value may have zero-valued bits in all positions corresponding to a second set of adjacent bits. The first and second sets of adjacent bits may be non-overlapping and together making up the seed value. In one example, the first set of adjacent bits comprise all bits of the seed value up to a bit index (least significant bits of the seed value) and the second set of adjacent bits comprise all bits of the seed value above index value (most significant bits of the seed value). In the example of the scrambling sequence c(n) of 3GPP TS 38.211, this may be expressed by c ^init = C _low + ^c high, the first constituent seed value being c _low ∈ {0, z > 7, and the second constituent seed value being c _high .

In some examples, the first constituent seed value may be based on a cell identifier and the second constituent seed value may be based on one or more of a user equipment identifier and a transport block identifier. The first and second sets of adjacent bits may be nonoverlapping and together making up the seed value. In the example of the scrambling sequence c(n) of 3GPP TS 38.211, this may be expressed by ^c init - ⁿ RNTI . 2 ¹⁵ + q .22 ¹⁴ + n _ID ; the first constituent seed value being n _ID and the second constituent seed value being n _RNTI . 2 ¹⁵ + q . 2 ¹⁴ , where n _ID is an example of a cell identifier, n _RNTI is an example of a user equipment identifier, and q is an example of a transport block identifier.

Generally, it should be appreciated that n _ID (or other cell identifiers) may be a same value for all user equipments in a cell, or a cell may have two or more n _ID wherein each n _ID can be shared by two or more user equipments.

Also generally, it should be appreciated that n _RNTI (a general term for several Radio Network Temporary Identifiers, RNTIs) is only one example of a user equipment identifier. Other examples include cell RNTI (C-RNTI), system information RNTI (SI-RNTI), paging RNTI (P-RNTI) and random access RNTI (RA-RNTI).

Also generally, it should be appreciated that - in an example using the transport block identifier q G {0,1} - the value is always set to 0 for single transport block transmissions and, for dual transport block transmissions, the value is set to 0 for the first block and to 1 for the second block. In some cells, only single transport block transmissions are allowed and the value is fixed at 0.

Figure 1 illustrates an example method 100 for generation of a final bit sequence according to some embodiments, and Figure 2 illustrates an example method 200 for preparation of generation of a final bit sequence according to some embodiments. Figures 1 and 2 will be described together in the following.

The methods 100 and 200 may be performed in association with each other (e.g., by a same apparatus). Alternatively, any of the methods 100 and 200 may be performed in isolation (e.g., by different apparatuses). The method 200 is a method for preparation of generation of the final bit sequence and the method 100 is a method for generation of the final bit sequence. In some embodiments, the method 100 is performed after performance of the method 200. The following description will commence by describing the method 200 of Figure 1, and thereafter continue by describing the method 100 of Figure 1.

In step 210 of the method 200, an intermediate sequence is determined for each of one or more first constituent seed values, wherein the intermediate sequence is based on the first constituent seed value. In some embodiments, the intermediate sequence is a bit-wise sum (modulo 2) of the second constituent sequence and the first constituent sequence for the first constituent seed value. In the example of the scrambling sequence c(n) of 3GPP TS 38.211, the intermediate sequence c _common = x ₁ + x ₂ ^ID is the bit sequence c achived by using the seed value c ^init = n _ID according to a first variant, and the intermediate sequence is the bit sequence c achieved by using a seed value c ^init = c _low according to a second variant.

In step 220 of the method 200, a version of the first constituent sequence is determined for a single-bit seed value (a hypothetical value for the seed with dynamic value), wherein the single-bit seed value has a single non-zero bit. In the example of the scrambling sequence c(n) of 3GPP TS 38.211, the version of the first constituent sequence may be the sequence for the single-bit seed value of 2 ^m with a single non-zero bit in position m, for any one m G {3, ...30}.

In step 230 of the method 200, the one or more intermediate sequences and of the version of the first constituent sequence are caused to be stored for subsequent generation of the final bit sequence. Causing storage may comprise performing storing (e.g., in the apparatus performing the method 200) or sending the one or more intermediate sequences and the version of the first constituent sequence for storage (e.g., in another apparatus than the one performing the method 200, such as the apparatus performing the method 100).

The method 200 may typically be performed more seldom than the method 100. For example, the determination of the intermediate sequence (and corresponding causing of storage) may be repeated when a change of the first constituent seed value is detected. In the example of the scrambling sequence c(n) of 3GPP TS 38.211, the repetition may occur when n _ID changes (e.g., when the user equipment changes cell and/or when the cell is restarted).

The method 100 may typically be performed each time the final bit sequence is needed for a relevant seed value (i.e., a value for the seed with dynamic value), as indicated by 105. In analogy with the elaboration above the relevant seed value comprises first and second constituent seed values.

In some embodiments, the method may comprise determining the first and second constituent seed values of the relevant seed value (not shown in Figure 1). In the example of the scrambling sequence c(n) of 3GPP TS 38.211 when the first constituent seed value is c _low G {0, ...,z}, z > 7, and the second constituent seed value is c _high , determining the first and second constituent seed values for a relevant seed value may comprise finding a value of c _low G {0, ...,z}, z > 7, which corresponds to the log ₂ z least significant bits of the relevant seed value.

The chain of steps 130, 140, and 150 is performed for each desired bit position of the final bit sequence, as illustrated by 125.

In step 130 of the method 100, a first bit value is acquired for a bit position (corresponding to the desired bit position under consideration) of the pre-stored intermediate sequence. The pre-stored intermediate sequence may, for example, be generated and stored as explained above in connection with steps 210 and 230 of Figure 2.

When there are more than one intermediate sequences (determined for each of more than one first constituent seed values), step 130 comprises acquiring the first bit value from the intermediate sequence that corresponds to the first constituent seed value of the relevant seed value.

The acquisition in step 130 may, for example, comprise reading the first bit value from a storage unit carrying the intermediate sequence, or a part thereof.

In step 140 of the method 100, a second bit value is acquired for each of one or more shifted positions of the pre-stored version of the first constituent sequence for a single-bit seed value. The pre-stored version of the first sequence may, for example, be generated and stored as explained above in connection with steps 220 and 230 of Figure 2.

Each of the one or more shifted positions is determined by the desired bit position under consideration, the position of the non-zero bit of the single-bit seed value, and the position of a non-zero bit of the second constituent seed value of the relevant seed value. Thus, the number of shifted positions correspond to the number of non-zero bits of the second constituent seed value of the relevant seed value.

For example, when the desired bit position under consideration is denoted n, the position of the non-zero bit of the single-bit seed value is denoted m, and the position of a non-zero bit of the second constituent seed value of the relevant seed value is denoted k, the corresponding shifted position may be determined as n — m + k.

The acquisition in step 140 may, for example, comprise reading the second bit value(s) from a storage unit carrying the version of the first constituent sequence, or a part thereof.

In step 150 of the method 100, a bit value of the final bit sequence (for the desired bit position under consideration) is determined as a sum of the first bit value and the one or more second bit values.

In the first variant of the example of the scrambling sequence c(n) of 3GPP TS 38.211, the final bit sequence value c(n) for desired bit position n may be determined as a sum of the first bit value c _common (n) and mod 2, where 2 represents the non-zero bit positions of the second constituent seed value of the relevant seed value, and are the second bit values.

In the second variant of the example of the scrambling sequence c(n) of 3GPP TS 38.211, the final bit sequence value c(n) for desired bit position n may be determined as a sum of the first bit value mod 2, where Y represents the non-zero bit positions of the second constituent seed value c _high of the relevant seed value, and are the second bit values.

In a sequential execution (for each desired bit position of the final bit sequence) of the chain of steps 130, 140, and 150, an optional step 160 may comprise determining whether all desired bit positions have been processed. When all desired bit positions have not been processed (N-path out of step 160), the method may return to step 125 to continue processing of the desired bit positions. When all desired bit positions have been processed (Y-path out of step 160), the method proceeds to any of the steps 170, 180, 190; as applicable.

Alternatively, the chain of steps 130, 140, and 150 may be executed in parallel for each desired bit position of the final bit sequence. Then, the method proceeds to any of the steps 170, 180, 190; as applicable.

In some embodiments, semi-parallel processing of the desired bit positions of the final bit sequence may be applied, in which the desired bit positions are organized into two or more disjunct (non-overlapping) groups (processing portions), as illustrated by optional step 110. Then, the processing portions may be handled in parallel as illustrated by optional step 115 (e.g., with sequential execution of the chain of steps 130, 140, and 150 for the desired bit positions within each processing portion), or the processing portions may be handled in sequence (e.g., with parallel execution of the chain of steps 130, 140, and 150 for the desired bit positions within each processing portion). Then, the method proceeds to any of the steps 170, 180, 190; as applicable.

Generally, parallel, or semi-parallel, processing may be achieved by a plurality of parallel processing devices each handling a processing portion of the desired bit positions. Alternatively or additionally, parallel processing may be achieved by using an operating instruction addressing an entire processing portion (e.g., a word or vector) of the desired bit positions. The former may be seen as a hardware approach to parallelization and the latter may be seen as a software approach to parallelization. Combinations are also possible, in which each of a plurality of parallel processing devices uses word/vector based operating instructions.

In some scenarios, the acquisition from the storage unit carrying the pre-stored version of the first constituent sequence may be inefficient in some sense (e.g. time consuming). For example, the storage unit may be a global storage unit shared by several processing devices and/or the storage unit may be accessible only via a relatively slow interface. In such (and other) situations, the method 100 may also comprise pre-acquiring relevant portion(s) of pre-stored version of the first constituent sequence and store (e.g., temporarily) the relevant portion(s) in one or more respective other storage units, as illustrated by optional step 120. For example, another storage unit may be a local storage unit specifically associated with one or more processing devices (or a local storage unit, such as a register, comprised in a processing device) and/or another storage unit may be accessible via a relatively fast interface.

Then, the second bit values may be acquired (in step 140) from the other storage unit(s), i.e., from the pre-acquired portion of the pre-stored version of the first constituent sequence for the single-bit seed value.

The pre-acquisition approach is particularly useful in the context of parallel, or semi-parallel, processing. Then, the portion of pre-stored version of the first constituent sequence that will be used by a particular processing device may be stored in a local storage unit specifically associated with, or comprised in, that processing device. Thereby, the second bit values may be efficiently acquired during processing by reading from the local storage unit.

In some scenarios, the methods 100 and 200 described above are applied for the entire final bit sequence.

In other scenarios, the methods 100 and 200 described above may be applied only for part of the entire final bit sequence. Thus, the desired bit positions correspond to a collection of adjacent bits of the final bit sequence. The collection of adjacent bits may correspond to the bit positions which lowest indices (least significant bits, initial bits), to the bit positions which highest indices (most significant bits), or to any sequence of bit positions there between. In the example of the scrambling sequence c(n) of 3GPP TS 38.211, the number of desired bit positions are typically at least 31.

In the scenarios where the methods 100 and 200 described above are applied only for part of the entire final bit sequence, the method 100 may further comprise (for each further bit position of the final bit sequence) recursively determining a further bit value(s) of the first (and/or second) constituent sequence, as illustrated by optional step 170, and determining the bit value of the further bit position of the final bit sequence based on the further bit value of the first constituent sequence, as illustrated by optional step 180 (compare with step 150).

The recursion in step 170 may be forward recursion, backward recursion, or both (as applicable).

The final bit sequence is for use in communication involving a user equipment served by a cell of a communication network. Thus, in some embodiments, the method 100 further comprises using the final bit sequence in communication involving the user equipment, as illustrated by optional step 190. Some examples of use of the final bit sequence include scrambling and/or descrambling of data conveyed by the communication (compare with the example of the scrambling sequence c(n) of 3GPP TS 38.211), cyclic redundancy checking (CRC) of data conveyed by the communication, and generating demodulation reference symbols (DMRS) conveyed by the communication.

Figure 3 schematically illustrates an example apparatus 310 according to some embodiments. The apparatus 310 may, for example, be comprisable (or comprised) in a transmitter and/or receiver configured for communication involving a user equipment served by a cell of a communication network. Alternatively or additionally, the apparatus 310 may be comprisable (or comprised) in a communication device (e.g., a wireless communication device such as a user equipment, or a network node such as a radio access node, a base station).

In some embodiments, the apparatus 310 may be configured to perform the method 100 as described above in connection with Figure 1 and/or the method 200 as described above in connection with Figure 2.

The apparatus 310 comprises a controller (CNTR; e.g., controlling circuitry or a control module) 300.

According to a first example, the apparatus 310 is for preparation of generation of a final bit sequence for use in communication involving a user equipment served by a cell of a communication network (compare with Figure 2). Various characteristics of the final bit sequence are exemplified above in connection to Figures 1 and 2.

In this example, the controller 300 is configured to cause determination - for each of one or more first constituent seed values - of an intermediate sequence which is based on the first constituent seed value (compare with step 210 of Figure 2). To this end, the controller may comprise or be otherwise associated with (e.g., connectable, or connected, to) a first determiner (DET; e.g., determining circuitry or a determination module) 301. The first determiner 301 may be configured to determine the intermediate sequence for each of the one or more first constituent seed values.

In this example, the controller 300 is also configured to cause determination - for a single-bit seed value, wherein the single-bit seed value has a single non-zero bit - of a version of the first constituent sequence (compare with step 220 of Figure 2). To this end, the controller may comprise or be otherwise associated with (e.g., connectable, or connected, to) a second determiner (DET; e.g., determining circuitry or a determination module) 302. The second determiner 302 may be configured to determine the version of the first constituent sequence for the single-bit seed value. The first and second determiners 301, 302 may be separate as illustrated in Figure 3, or may constitute a single determiner.

In this example, the controller 300 is also configured to cause storage of the one or more intermediate sequences and of the version of the first constituent sequence, for subsequent generation of the final bit sequence (compare with step 230 of Figure 2). For example, the controller 300 may be configured to store the one or more intermediate sequences and of the version of the first constituent sequence in a storage unit, such as a memory (MEM; e.g., memory circuitry or a memory module) 320, comprised in the apparatus 310. Alternatively or additionally, the controller 300 may be configured to transmit the one or more intermediate sequences and of the version of the first constituent sequence for storage in a storage unit, such as a memory (MEM; e.g., memory circuitry or a memory module) 321, external to the apparatus 310.

In some embodiments, the controller is further configured to cause repetition of the determination and the storage of the intermediate sequence responsive to detection of a change of the first constituent seed value.

According to a second example (which may, or may not, be combined with the first example), the apparatus 310 is for generation of a final bit sequence for use in communication involving a user equipment served by a cell of a communication network (compare with Figure 1). Various characteristics of the final bit sequence are exemplified above in connection to Figures 1 and 2.

In this example, the controller 300 is configured to cause acquisition of a first bit value for a corresponding bit position of a pre-stored intermediate sequence (compare with step 130 of Figure 1), and acquisition of a second bit value for each of one or more shifted positions of a pre-stored version of the first constituent sequence for a single-bit seed value (compare with step 140 of Figure 1). To this end, the controller may comprise or be otherwise associated with (e.g., connectable, or connected, to) an acquirer (ACQ; e.g., acquiring circuitry or an acquisition module) 303. The acquirer 303 may be configured to acquire the first bit value for the corresponding bit position of the pre-stored intermediate sequence; e.g., by reading from a storage unit, such as a memory (MEM; e.g., memory circuitry or a memory module) comprised in the apparatus 310 as illustrated by 320 or external to the apparatus 310 as illustrated by 321.

In this example, the controller 300 is also configured to cause determination of a bit value of the desired bit position of the final bit sequence as a sum of the first bit value and the one or more second bit values (compare with step 150 of Figure 1). To this end, the controller may comprise or be otherwise associated with (e.g., connectable, or connected, to) a generation determiner (DET; e.g., determining circuitry or a determination module) 304. The generation determiner 304 may be configured to determine the bit value of the desired bit position of the final bit sequence.

In some embodiments, the acquisition (of the first bit value the one or more second bit value(s)) and/or the determination of the bit value of the desired bit position of the final bit sequence may be performed by a processor (PROC; e.g., processing circuitry or a process module) 330.

In this example, the controller 300 may be further configured to cause use of the final bit sequence in communication involving the user equipment (compare with step 190 of Figure 1). To this end the controller may be associated with (e.g., connectable, or connected, to) a transmitter and/or receiver, for example a transceiver (TX/RX; e.g., transceiving circuitry or a transceiver module) 340. The transceiver 340 may be configured to use of the final bit sequence in communication involving the user equipment. It should be noted that, even if not explicitly repeated for Figure 3, the controller 300 may be further configured to cause any other method step(s) as described above in connection with any of Figures 1 and 2.

Figure 4 schematically illustrates an example apparatus 410 according to some embodiments. The apparatus 410 may, for example, be comprisable (or comprised) in a communication device (e.g., a central processing node).

In some embodiments, the apparatus 410 may be configured to perform the method as described above in connection with Figure 2.

The apparatus 410 comprises a controller (CNTR; e.g., controlling circuitry or a control module) 400.

The apparatus 410 is for preparation of generation of a final bit sequence for use in communication involving a user equipment served by a cell of a communication network (compare with Figure 2). Various characteristics of the final bit sequence are exemplified above in connection to Figures 1 and 2.

The controller 400 is configured to cause determination - for each of one or more first constituent seed values - of an intermediate sequence which is based on the first constituent seed value (compare with step 210 of Figure 2). To this end, the controller may comprise or be otherwise associated with (e.g., connectable, or connected, to) a first determiner (DET; e.g., determining circuitry or a determination module) 401. The first determiner 401 may be configured to determine the intermediate sequence for each of the one or more first constituent seed values.

The controller 400 is also configured to cause determination - for a single-bit seed value, wherein the single-bit seed value has a single non-zero bit - of a version of the first constituent sequence (compare with step 220 of Figure 2). To this end, the controller may comprise or be otherwise associated with (e.g., connectable, or connected, to) a second determiner (DET; e.g., determining circuitry or a determination module) 402. The second determiner 402 may be configured to determine the version of the first constituent sequence for the single-bit seed value. The first and second determiners 401, 402 may be separate as illustrated in Figure 4, or may constitute a single determiner. The controller 400 is also configured to cause storage of the one or more intermediate sequences and of the version of the first constituent sequence, for subsequent generation of the final bit sequence (compare with step 230 of Figure 2). For example, the controller 400 may be configured to store the one or more intermediate sequences and of the version of the first constituent sequence in a storage unit, such as a memory (MEM; e.g., memory circuitry or a memory module) 420, comprised in the apparatus 410. Alternatively or additionally, the controller 400 may be configured to transmit the one or more intermediate sequences and of the version of the first constituent sequence for storage in a storage unit, such as a memory (MEM; e.g., memory circuitry or a memory module) 421, external to the apparatus 410.

The memory 421 which is external to the apparatus 410 may be configured to be comprised in or otherwise associated with (e.g., connectable or connected, to) an apparatus for generation of the final bit sequence; e.g., the apparatus 310 of Figure 3.

In some embodiments, the controller is further configured to cause repetition of the determination and the storage of the intermediate sequence responsive to detection of a change of the first constituent seed value.

It should be noted that, even if not explicitly repeated for Figure 4, the controller 400 may be further configured to cause any other method step(s) as described above in connection with Figure 2.

Figure 5 schematically illustrates an example apparatus 510 according to some embodiments. The apparatus 510 may, for example, be comprisable (or comprised) in a transmitter and/or receiver configured for communication involving a user equipment served by a cell of a communication network. Alternatively or additionally, the apparatus 510 may be comprisable (or comprised) in a communication device (e.g., a wireless communication device such as a user equipment, or a network node such as a radio access node, a base station). For example, the apparatus 510 may be seen as a variant of the apparatus 310 of Figure 3.

In some embodiments, the apparatus 510 may be configured to perform the method 100 as described above in connection with Figure 1 and/or the method 200 as described above in connection with Figure 2. The apparatus 510 is for generation of a final bit sequence for use in communication involving a user equipment served by a cell of a communication network (compare with Figure 1). Various characteristics of the final bit sequence are exemplified above in connection to Figures 1 and 2.

The apparatus 510 comprises a controller (CNTR; e.g., controlling circuitry or a control module) 500, a plurality of processors (PROC; e.g., processing circuitries or processor modules) 531, 532, 533, and a global storage unit (G_MEIVI; compare with 320, 321, 420, 421) 520 carrying an intermediate sequence for each of one or more first constituent seed values and a version of the first constituent sequence for a single-bit seed value. The plurality of processors 531, 532, 533 may be considered as parallel processing circuitry.

The controller 500 may be configured to cause organization of desired bit positions of the final bit sequence into two or more disjunct groups, and parallel performance of the generation of the final bit sequence using two or more of the processors 531, 532, 533.

In some embodiments, the controller 500 is further configured to cause pre-acquisition of portions of the pre-stored version of the first constituent sequence from the global storage unit 520 and storage of the pre-acquired portions in respective local storage units; such that a pre-acquired portion is stored in a local storage associated with a processor where it will be used for generation of the final bit sequence.

Example local storage units are illustrated as respective registers (REG) 541, 542, 543 comprised in the processors 531, 532, 533, and as local memory 521, 522, 523 external to, but easily accessible by, the processors 531, 532, 533. It should be noted that there may be one- to-one correspondence between a local memory and a processor, or a local memory may be shared by two or more processors as illustrated by 525.

The controller 500 is configured to cause acquisition of a first bit value for a corresponding bit position of a pre-stored intermediate sequence (compare with step 130 of Figure 1); typically by causing the processors 531, 532, 533 to read from the global storage unit 520.

The controller 500 is configured to cause acquisition of a second bit value for each of one or more shifted positions of a pre-stored version of the first constituent sequence for a single-bit seed value (compare with step 140 of Figure 1); typically by causing the processors 531, 532, 533 to read from the global storage unit 520, or from respective local storage units 541, 542, 543, 521, 522, 523, as applicable.

The controller 500 is also configured to cause determination - by respective ones of the processors 531, 532, 533 - of a bit value of the desired bit position of the final bit sequence as a sum of the first bit value and the one or more second bit values (compare with step 150 of Figure 1).

It should be noted that, even if not explicitly repeated for Figure 5, the controller 500 may be further configured to cause any other method step(s) as described above in connection with any of Figures 1 or 2.

It should be noted that some embodiments presented herein fit particularly well for implementation in a cloud environment. One reason therefore is that no dedicated hardware is required for bit scrambling, and bit scrambling can rely on general-purpose hardware with parallel computation cores.

Exemplifying using the scrambling sequence c(n) of 3GPP TS 38.211, such sequences are typically generated in a serial fashion (e.g., one bit position at a time) using recurrence relations. There are also approaches where several bits are generated at a time using recurrence relations, and/or where parts of the sequence generation is parallelized (e.g., using multiple processors). For example, subsections of the sequence may be handled in parallel, where each subsection is generated in a serial fashion. In the latter case, it may be necessary to compute initial conditions for each subsection, which may become relatively complicated.

Scrambling may be implemented in software running on general-purpose processors but is often implemented in specialized hardware to achieve high efficiency.

Since the amount of processing typically increases with the length of the message to be scrambled, the time required for sequence generation may be substantial for relatively long messages (especially prominent for software implementations). Thus, it may be problematic to implement scrambling using general-purpose processors.

The serial nature of recursion processing makes it cumbersome to generate the scrambling sequence efficiently on parallel hardware (e.g., graphics processing units, GPUs). Previously known techniques for parallelization are still based on serial computation for each subsection, and initial conditions need to be computed for each subsection.

Some embodiments address one or more of these issues, as realized from the above description. In short, the sequence generation can be made more efficient in that a relatively small number of pre-computed values are added to compute each bit of the scrambling sequence; an approach which is well suited for parallelization. This enables efficiently using hardware with a large number of processing cores; even in cases where each core is relatively slow.

For the example of the scrambling sequence c(n) of 3GPP TS 38.211, the x ₁ -sequence is fixed and can be pre-computed and stored in memory (requiring no more than about 180 kbytes of storage). The x ₂ -sequence ' ^s fully determined by the 31-bit seed c _init (resulting in 2 ³¹ different sequences, each with a length of about 180 kbytes). Therefore, pre-computing and storing of all x ₂ -sequences would typically not be feasible (or even possible). According to some embodiments, only a few different x ₂ -sequences are pre-computed based on corresponding selected seed values, and the scrambling sequence is determined based on the Xi-sequence and the few different x ₂ -sequences, using the superposition and shift principles.

In a first example, the scrambling sequence is generated as a sum of a common sequence and a UE-specific sequence:

The common sequence c _common (n) is the scrambling sequence with c _init = n _ID (n _RNTI and q set to zero).

The UE-specific sequence c _UE (n) is the x ₂ -sequence with This seed value has no non-zero bits at positions i < 14. This seed value may be seen as the bitwise exclusive-or of a number of seed values, each with a single non-zero bit, and the corresponding x ₂ -sequence may be formed based on the superposition principle, as a sum of the corresponding sequences: where the notation bits(c _init ) denotes the positions in c _init with non-zero bits; i.e., Due to the shift principle, this may be equivalently expressed as mod 2, where k > 14.

The first example in summary:

• Pre-computation (typically once for all UEs with common n _ID , e.g., once per cell): o Precompute the sequence c _common with c _init = n _ID and store in memory. o Precompute the sequence for one m G {3, ... ,30} and store in memory.

• Generation of the scrambling sequence for a relevant c _init : o For each desired position n:

■ Read the precomputed element c _common (n) from memory.

■ Generate the element c _UE (n) by reading the precomputed elements from memory and using the above summation based on the shift principle.

■ Compute c(n) = c _common (n) + c _UE (n).

Because the elements c(n) are generated independently of each other, the generation can be easily parallelized.

In a second example, c _init is split into two parts c _init = c _low + c _high , where c _low G {0, ... ,7}. Thus, c _low consists of the bits with indices 0,1,2 of c _init and c _high consists of the bits with indices 3, ... ,30. (It should be noted that any other collection of at least three bits from c _init may be used instead of c _low .) The corresponding x ₂ -sequences ^{a re} denoted as and and due to the superposition principle, the scrambling sequence can be expressed as

Similarly to the first example, can be computed based on a number of pre-computed x ₂ -sequences corresponding to seed values with a single non-zero bit using a combination of the superposition and shift principles:

The second example in summary:

Pre-computation (typically once): o Precompute the ^-sequence. o For each value of c _low ∈ {0, precompute and store in memory. o Precompute the sequence for one m G {3, ...,30} and store in memory.

• Generation of the scrambling sequence for a relevant c _init : o Find Cl _ow ∈ {0, ...,7} and such that Cl _nR C _low 3” Chigh o For each desired position n

■ Read the precomputed element from memory.

■ Generate the element by reading the precomputed elements from memory and using the above summation based on the shift and superposition principles.

■ Compute

Because the elements c(n) are generated independently of each other, the generation can be easily parallelized.

Since the generation of each element requires reading a number of elements from memory (up to 18 for the first example; one read for c _common (n) and one read for each of the nonzero elements in n _RNTI . 2 ¹⁵ + q . 2 ¹⁴ ), the efficiency may be further improved by storing at least relevant portions of the sequence in memory that is easily accessible by the device(s) performing the generation of the scrambling sequence.

For example, the scrambling sequence to be generated may be divided into subsequences (e.g., one subsequence per available processor) and each processor generates the scrambling sequence elements c(n) for n = n _start , n _start + 1, ... ,n _stop , for some n _start and n _stop . Then, a corresponding subsequence of the precomputed sequence may be read into local memory of the processor before starting the sequence generation. The corresponding subsequence includes all elements required by as applicable; namely elements from n _start — m + 14 to n _stop — m + 30 in the former case and elements from nstart — m + 4 to n _stop — m + 30 in the latter case. As mentioned before, a processor may generate multiple elements of the scrambling sequence simultaneously. For example, the number of simultaneously generated elements may be equal to the number of bits in a processor word (some commonly used processor word lengths are 16, 32, 64, 128, 256, and 512 bits), or other unit for processing. In such approaches, shift operations and/or addition operations required for the summation of the elements x ₂ (n — m + k) can be implemented by shifting and/or adding an entire multi-bit word in one operation.

In some embodiments, the scrambling sequence to be generated is divided into subsequences (e.g., one subsequence per available processor) and each processor generates the scrambling sequence elements c(n) for n = n _start , n _start + 1, ... , n _stop , as described above for the first or second example. However, each processor uses the precomputed and stored sequences to calculate c(n) only for a collection of adjacent bits (e.g., the initial 31 bits) of subsequence, and calculates the remaining bits of its subsequence in a serial fashion. This approach may reduce the number of memory reads compared to the first and second examples above.

The described embodiments and their equivalents may be realized in software or hardware or a combination thereof. The embodiments may be performed by general purpose circuitry. Examples of general purpose circuitry include digital signal processors (DSP), central processing units (CPU), co-processor units, field programmable gate arrays (FPGA) and other programmable hardware. Alternatively or additionally, the embodiments may be performed by specialized circuitry, such as application specific integrated circuits (ASIC). The general purpose circuitry and/or the specialized circuitry may, for example, be associated with or comprised in an apparatus such as a wireless communication device (e.g., a user equipment, UE) or a network node (e.g., a radio access node, a base station, or a central processing node).

Embodiments may appear within an electronic apparatus (such as a wireless communication device or a network node) comprising arrangements, circuitry, and/or logic according to any of the embodiments described herein. Alternatively or additionally, an electronic apparatus (such as a wireless communication device or a network node) may be configured to perform methods according to any of the embodiments described herein.

According to some embodiments, a computer program product comprises a tangible, or nontangible, computer readable medium such as, for example a universal serial bus (USB) memory, a plug-in card, an embedded drive or a read only memory (ROM). Figure 6 illustrates an example computer readable medium in the form of a compact disc (CD) ROM 600. The computer readable medium has stored thereon a computer program comprising program instructions. The computer program is loadable into a data processor (PROC; e.g., data processing circuitry or a data processing unit) 620, which may, for example, be comprised in a wireless communication device or a network node Z10. When loaded into the data processor, the computer program may be stored in a memory (MEM) 630 associated with or comprised in the data processor. According to some embodiments, the computer program may, when loaded into and run by the data processor, cause execution of method steps according to, for example, any of the methods illustrated in Figures 1 and 2; or otherwise described herein.

Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and/or is implied from the context in which it is used.

Reference has been made herein to various embodiments. However, a person skilled in the art would recognize numerous variations to the described embodiments that would still fall within the scope of the claims.

For example, the method embodiments described herein discloses example methods through steps being performed in a certain order. However, it is recognized that these sequences of events may take place in another order without departing from the scope of the claims. Furthermore, some method steps may be performed in parallel even though they have been described as being performed in sequence. Thus, the steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and/or where it is implicit that a step must follow or precede another step.

In the same manner, it should be noted that in the description of embodiments, the partition of functional blocks into particular units is by no means intended as limiting. Contra rily, these partitions are merely examples. Functional blocks described herein as one unit may be split into two or more units. Furthermore, functional blocks described herein as being implemented as two or more units may be merged into fewer (e.g. a single) unit. Any feature of any of the embodiments disclosed herein may be applied to any other embodiment, wherever suitable. Likewise, any advantage of any of the embodiments may apply to any other embodiments, and vice versa.

Hence, it should be understood that the details of the described embodiments are merely examples brought forward for illustrative purposes, and that all variations that fall within the scope of the claims are intended to be embraced therein.