CHARGE RECYCLING CIRCUIT AND METHOD FOR DC-DC CONVERTERS PRIORITY CLAIM AND REFERENCE TO RELATED APPLICATION [001] The application claims priority under 35 U.S.C. §119 and all applicable statutes and treaties from prior United States provisional application serial number 63/115,240 which was filed November 18, 2020. FIELD [002] Fields of the invention are DC-DC converters and integrated circuits. Methods and circuits of the invention are applicable to any product that utilizes an inductive DC-DC converter, which essentially covers a wide- range of applications starting from personal electronics to automotive and industrial electronics. BACKGROUND [003] The losses related to the power MOSFETs in inductive DC-DC and other DC-DC converters are a main contributor to the total converter losses and play an important role in determining the power conversion efficiency. Each power MOSFET has its intrinsic on-resistance R _ON causing conduction loss that is inversely proportional to the MOSFET width ( W). In addition, each power MOSFET has also switching loss related to the charging/discharging of its gate capacitance (C _GATE ) and this loss increases linearly withW . For a given load current, there is an optimum W that results in minimum losses but this optimum W changes as the load current (A) changes. There is no certain design choice of W that can give minimum losses for a wide range of load cur-rents. Therefore, the design of inductive DC-DC converters is fundamentally limited by this trade-off between conduction losses and switching losses.

[004] Miniaturized converters used in applications such as mobile devices suffer badly from this trade off, as a small inductor has a large DCR (DC resistance), which contributes larger I ² _L DCR conduction losses, while a small inductance desires high frequency operation, which implies higher C _GATE V ² F _SW hard charging switching losses from the power MOSFET gate drivers. The rise/fall time of such drivers cannot be too rapid, regardless of switching frequency, due to inductive ringing causing potential voltage stresses. See, K. Wei et al., “A Direct 12V/24V-to-lV 3W 91.2%- Efficiency Tri-State DSD Power Converter with Online VCF Rebalancing and In-Situ Precharge Rate Regulation,” ISSCC, 2020; W. Liu et al., “A 94.2%-peak-efficiency 1.53 A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65 nm CMOS,” ISSCC, 2017. One hard- switching 3 ^rd order buck converter used two power transistors M1; and AA, with the gates of M1 and M2 switching with amplitude V _lN above and below V _0UT , respectively. M1 and M2 are hard-switched through flying inverter-based drivers. See, A. Abdulslam et al., “A Continuous-Input-Current Passive-Stacked Third-Order Buck Converter Achieving 0.7W/mm ² Power Density and 94% Peak Efficiency,” ISSCC, 2019. [005] To ease the conduction/switching loss trade-off, it is possible to exploit the requirement for finite rise/fall time by replacing conventionally hard- switching gate drivers with adiabatic charge-recycling (CR) gate drivers. Charge recycling can, through the help of an inductor, recycle the charge stored on a gate capacitor of the power transistor to an additional storage capacitor (and vice-versa), theoretically with 100% efficiency.

[006] This approach was demonstrated in M. Mulligan et al., “A 3MHz Low- Voltage Buck Converter with Improved Light Load Efficiency,” ISSCC, 2007. In the converter described in that paper, charge on the power MOSFET gates is recycled to two auxiliary capacitors through two separate inductors. One downside is the overhead of two inductors. Another drawback is that recycling with separate storage capacitors introduces indirect losses, while the separated duty-cycled resonate gate drivers makes non-overlap timing control between power MOSFETs difficult.

[007] AC-coupling the power NMOS to the resonant gate driver can reduce the number of resonant inductors to 1. Jia, J. Gu, “A 0.3 -0.86V Fully Integrated Buck Regulator with 2GHz Resonant Switching for Ultra-Low Power Applications,” VLSI, 2017. However, the non-overlap time cannot be precisely controlled, leading to potentially large overlap losses, and limited duty-cycle control through driver slope modulation prevents robust regulation across a wide output range.

SUMMARY OF THE INVENTION

[008] A preferred embodiment provides charge recycling circuit in an integrated circuit DC-DC converter having two power MOSFETs, the charge recycling circuit comprising a single inductor and recycling MOSFET switches arranged and sized such that when one of the two power MOSFETs is turning off, its gate capacitance charges are transferred to the single inductor, stored in the single inductor and then transferred directly to the gate of the other power MOSFET to turn it on.

[009] A preferred method for charge recycling in a DC-DC converter including two power MOSFETs connected to a converter output includes transferring gate capacitance charges from one of the two power MOSFETs when it is turning off to an inductor. When the gate capacitance charges of the one of the two power MOSFETs is depleted, transferring charge stored in the inductor to the gate of the other power MOSFET to turn it on. The charge transfer through the inductor is reveres when the other power MOSFET is turning off, wherein the charge transfers through the inductor are interspersed with normal operations of the converter to convert a DC input voltage to a DC output voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIGs. 1A and IB illustrate a preferred direct reciprocal charge recycling circuit and method applied to an inductor-first 3 ^rd order buck converter, with FIG. 1A showing a conceptual circuit diagram and FIG. IB showing waveforms of the circuit;

[0011] FIG. 1C shows a preferred schematic circuit for the direct reciprocal charge recycling circuit and method applied to an inductor-first 3 ^rd order buck converter of FIG. 1 A;

[0012] FIGs. 2A-2F illustrate six states of operation for the converter with direct reciprocal charge recycling circuit;

[0013] FIG. 2G shows wave forms of the FIGs. 2A-2F operational states of the converter with the reciprocal charge recycling circuit;

[0014] FIG. 3 A illustrates parasitics of the charge recycling loop;

[0015] FIG. 3B shows a curve of charge recycling efficiency versus recycling inductor size; [0016] FIG. 3C illustrates trade-offs between gate driver losses and V-I overlap losses for a representative light load current showing a shallow optimum;

[0017] FIG 4A is a detailed schematic circuit diagram of a preferred charge- recycling inductor-first buck converter with exemplary component sizes;

[0018] FIGs. 4B and 4C show a preferred implementation of the charge recycling drivers in FIG. 4A;

[0019] FIGs. 5A and 5B are schematic cross-sectional views of the preferred bootstrapping capacitors implemented in deep N-well technology;

[0020] FIGs. 6A-6C respectively show a tunable delay line for PWM control signals, a recycling driver control circuit and a normal driver control circuit;

[0021] FIG. 6D shows a level shifter used for all of the control signals in the driver control circuits;

[0022] FIG. 7 shows a block diagram of the charge recycling technique applied to an inductor-first buck converter;

[0023] FIGs. 8A-8C show the present charge recycling circuit applied to a buck converter; and

[0024] FIGs. 9A-9C show the present charge recycling circuit applied to two power MOSFETS in DC-DC converters of any topology.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] A preferred embodiment provides a charge recycling circuit and method for inductive DC-DC converters that enables direct, reciprocal recycling of gate charge from one power MOSFET to another by the addition of only a single inductor and switches, all without affecting converter operation or control and while ensuring non-overlap conditions. The preferred circuit and method greatly relax the fundamental trade-off between conduction losses and switching losses in inductive DC-DC converters enabling overall higher power density and/or higher efficiencies specially at low load current range. An implemented prototype of a converter circuit of the invention achieves a peak efficiency of 98.2%, a peak power density of 0.72W/mm ² , and efficiency of 88.4% down to 1% of the maximum load current.

[0026] Compared to prior charge recycling approaches in DC-DC converters, the present recycling circuit and method requires only one inductor resulting in a smaller charge recycling circuit. The present circuit and method achieve direct reciprocal charge recycling between power MOSFETs themselves, resulting in a higher charge recycling efficiency, which does not interfere with normal operation or control of the converter. In preferred embodiments, when a power MOSFET is turning off, its gate capacitance charges are transferred to an inductor. These charges stored in the inductor are then transferred directly to the gate capacitance of the other power MOSFET to turn it on.

[0027] Preferred embodiments of the invention will now be discussed with respect to experiments and drawings. Broader aspects of the invention will be understood by artisans in view of the general knowledge in the art and the description of the experiments that follows.

[0028] FIGs. 1A and IB illustrate a preferred direct reciprocal charge recycling circuit 10 and method applied to an inductor-first 3 ^rd order buck converter 12. The reciprocal charge recycling circuit 10 consists of switches S1 and S2 and inductor LR connected as shown to gates of the power switches M1 and M2. VGATE1 of M1 switches with amplitude V _IN above V _OUT , and VGATE2 switches with amplitude V _IN below V _OUT , as shown in FIG. IB. Rather than hard switching M1 and M2 through flying inverter-based driver, the direct reciprocal charge recycling circuit 10 first asserts switch S1 to charge recycling inductor LR via gate charge stored on the gate of M1 until CGATE1 is fully depleted. This is the state when VGATE1 = V _OUT , VLR = 0 and ILR is at its maximum value. At this point, S1 turns off and S2 is asserted using energy stored in the inductor LR to charge CGATE2 , ' the reverse order of operation occurs when M ₂ is turned off, which provides direct reciprocal charge recycling between the power transistors M ₁ and M ₂ . [0029] FIG.1C shows a preferred detailed schematic of the direct reciprocal charge recycling circuit 10 and the inductor-first 3 ^rd order buck converter 12. During normal operation of the 3 ^rd order buck converter 12, M ₁ and M ₂ switch with duty cycle D, leading V _X1 to switch between V _OUT and (V _OUT +V _IN ), and V _X2 to switch between (V _OUT -V _IN ) and V _OUT . Inductor volt-second balancing then ensures that the flying capacitor is balanced at V _IN and that V _OUT = DV _IN . Two bootstrapping capacitors C _BOOT1,2 are used to internally generate two level- shifted rail voltages V _OUT +V _IN and V _OUT -V _IN that are used to drive M ₁ and M ₂ , which turn ON by connecting their gate terminals to C _BOOT1 and C _BOOT1 through charge-recycling transistors/switches M _1U and M _2U . They turn OFF by dumping their gate charges to the V _OUT node through M _1L and M _2L . Thus, there gates are nominally hard charged with a swing of V _IN . [0030] To instead recycle the gate charges of M ₁ and M ₂ , the inductor L _R is connected, and can be formed by a small PCB-trace placed between V _OUT and an internal node VR. As seen in FIG. 1C, this only requires a single additional pin on the power management integrated circuit that is the inductor-first 3 ^rd order buck converter 12. In FIG.1C, VR is connected to the gate of power MOSFETS M ₁ and M ₂ through charge recycling MOSFETS M _1R and M _2R to form a charge recycling loop including C _GATE1 and C _GATE2 , with M _R1 implemented as PMOS and M _Rs implemented as NMOS. Because there are a minimal number of passive and active components introduced by the charge recycling loop, which consist of the one inductor L _R and the switch/charge recycling transistors M _1R and M _2R , the total parasitic resistance of the direct reciprocal charge recycling circuit 10 is low and can provide a charge recycling efficiency on the order of 80%. [0031] FIGs.2A-2F illustrate six states of operation for the direct reciprocal charge recycling circuit with respect to converter operation, illustrating that the charge recycling can be applied on top of normal converter operations. FIG. 2G shows wave forms of the FIGs. 2A-2F operational states, which include 2 normal conversion states and two recycling states. When M1 is normally ON, its gate is tied to (V _OUT +V _IN ) through M1u. When M1 beings to turn off M1U is deactivated and M _1R is activated so that CGATE1 discharges completely into LR. Then the regular gate drivers are activated to tie the power MOSFET gate terminals to the appropriate voltages, while M _1R is turned on to discharge any residue charges in LR that might occur due to imperfect control timing. The same process can be applied when M2 turns OFF to recycle the charge back from C GATES to CGATE1. The charge recycling adds four phases of relatively small duration to the converter’s 12 basic operation phases without interfering with the converter’s 12 normal operation.

[0032] Charge recycling efficiency represents that percentage of the power MOSFET gate charges that was recycled and not dissipated when the power MOSFETs are changing states. The recycling efficiency (η _r ) can be defined as:

[0034] where P _{Sw, Recycle} is the total gate drive losses when recycling is applied, P _SW,Hard is the gate drive losses without recycling, i.e., hard charging/discharging of the gate capacitance. F _sw is the switching frequency, and C _GATE1 + C _GATE2 are the respective gate capacitances of the power transistors M1 and M2.

[0035] FIG. 3 A illustrates parasitics of the charge recycling loop (showing only the charge recycling loop portion of the circuit), which are introduced by the inductor LR and the switch/charge recycling transistors M _1R and M _2R . The parasitics primarily include the equivalent DCR the inductor and the switching, as well as the conduction losses of the recycling MOSFETs. These parasitics can degrade charge recycling efficiency. This can be mitigated by increasing the size of the inductor LR, with which increasing size recycles a larger amount of charge and provides lower RMS current in the recycle loop. This can reduce gate driver losses and improve CR efficiency.

[0036] FIG. 3B shows a curve of charge recycling efficiency versus recycling inductor size. As seen the curve, > 70% recycling efficiency is realized for >4 nH recycling inductors. The data is for 50mΩ DCR, CGATE1,2 = 200 pF. Including the conduction and switching losses of M _1R and M _2R (which are 3% of the size of M ₁ and M ₂ )(generally size is dependent on the specific design of the converter and how much charge-recycling is needed; 0.01% to 20% represents a practical acceptable range), 60-80% recycling efficiency is available with LR ranging from 1-10 nH as a result of relatively low losses in the charge recycling loop. A trade-off is that increasing the inductor size too much can produce too slow rise/fall times in the value of CGATE1,2, which leads to higher overlap losses in M ₁ and M ₂ .

[0037] FIG. 3C illustrates trade-offs between gate driver losses and V-I overlap losses for a representative light load current showing a shallow optimum. When combining the overlap losses with the gate drive losses (while charge recycling is applied) the total losses will have a shallow optimum illustrating reduced overall losses (even when overlap losses are increasing with the recycling inductor size). At higher load currents, partial charge recycling can be applied by reducing the pulse duration of the charge recycling signals. This minimum duration is consistent with the goal of minimum rise/fall time for gate signals to prevent ringing at the switching nodes.

[0038] FIG 4A is a detailed schematic circuit diagram of a preferred charge- recycling inductor-first buck converter with exemplary component sizes. Small-size passive components were used for the power inductors and capacitors. The charge recycling inductor was implemented via a PCT trace. The circuit includes a closed-loop controller with a type-III compensator to generate a PWM signal. The PWM signal was used to generate all eight control signals for eight drivers 40.

[0039] FIGs. 4B and 4C show a preferred implementation of the charge recycling drivers in FIG. 4A. Driving the charge recycling MOSFETS M _1R and M _2R can be challenging due to the varying voltage are their source and drain terminals. When M _1R is activated to charge/discharge CGATE1, it needs to bypass a voltage that varies between V _OUT and (V _OUT V _IN ), which is a voltage swing of V _IN . When M _2R is activated to charge/discharge CGATE2, it needs to bypass a voltage that varies between V _OUT and (V _OUT -V _IN ), which is a voltage swing of V _IN . M _1R and M _2R need to bypass these varying voltages while minimizing their on-resistance to minimize losses in the recycling loop. As seen in FIGs. 4B and 4C, preferred divers include local bootstrapping capacitors CBoot1R and CBoot2R connected to the gate terminals of their respective power MOSFETS VG1 and VG2 to generate appropriate internal flying rails.

[0040] These drivers provide several benefits. One is that the CR MOSFETs can be implemented using the low- voltage 1.8 V MOSFETS, while bypassing large varying voltages. Another is that the CR MOSFETs are always driven with the maximum overdrive voltage of V _IN , which minimizes losses in the recycling loop even when bypassing a varying voltage with a V _IN swing. V _IN is the main input voltage to the converter. V _IN is also the overdrive voltage (the gate-to-source voltage) that is used to drive the CR MOSFETs. An additional advantage is that the CR MOSFETs are driven from internal converter internal nodes with no need for external supplies to drive them.

[0041] FIGs. 5A and 5B are schematic cross-sectional views of the preferred bootstrapping capacitors implemented in deep N-well technology. By implementing the capacitors in deep N-well technology, their negative terminals can be freely connected to voltages that different from the chip bulk voltage. [0042] FIGs. 6A-6C respectively show a tunable delay line for PWM control signals, a recycling driver control circuit and a normal driver control circuit. The two PWM-input delay lines in FIG. 6A provide delayed version of the PWM signal as triggers for the SR registers in the drivers of FIGs. 6B and 6C. Some of the delay cells are tunable to control the duration of charge recycling pulses to best suit the value employed for LR. FIG. 6D shows a level shifter used for all of the control signals such that VHIGH and VLOW are always connected to the converter internal nodes. The eight control signals are level- shifted by capacitively coupling into the flying-domain latches. VHIGH and VLOW are self-generated from converter internal nodes without need for any additional external supply.

[0043] The preferred circuit of FIGs. 4A-6D was fabricated as a PMIC in 180 rnn CMOS with a total area of 4.6 mm ² . The PMIC was flip-chip bonded to an interposer where the passives (CF = 10 pF, L12 - 240 nH, C _OUT - 4.7 pF) were mounted on the backside. The total converter area, including all routing and the 4 nH PCB - trace recycling inductor occupied 5.7 mm ² .

[0044] When switched at 3 MHz, measurement results of efficiency versus load current revealed peak efficiencies of 98.2%, 95 %, and 89.2% for V _OUT = 1.5, 1, and 0.5 V, respectively. The converter had a high peak power density of 0.72 W/mm ² (or 0.4 W/mm ³ ) achieved at an efficiency of 91.8%. The charge recycling enabled a high measured peak efficiency of 88.4% even at only 1 % of the maximum load current. A peak efficiency of 95% was achieved at output voltage of IV and at 89% at an output voltage as low as 0.5V. Due to the charge recycling, efficiency is improved over a wide range of load currents, especially at light load currents with a demonstrated 88.4 % efficiency even at 1% of maximum load current.

[0045] FIG. 7 shows a block diagram of the charge recycling technique applied to an inductor-first buck converter 72. The charge-recycling circuit 10 is constructed as in FIG. 1 or FIGs. 9A-9C and consists of a single inductor and switches that perform a direct charge recycling process for the gate charges of switche Ss 1 and S2. The FIG. 1 example for the charge-recycling circuit construction applies when S1 is NMOS and S2 is PMOS. It can have a different configuration depending on S1 and S2 type as illustrated in FIGs. 9A-9C. The charge recycling circuit 10 is connected to the gate terminals of S1 and S2. In addition, the charge-recycling circuit 10 can also be coupled to Vx1, Vx2 and/or V _OUT nodes depending on whether S1 and S2 are implemented as NMOS or PMOS. If S1 is implemented as an NMOS, the charge recycling circuit 10 is coupled to V _OUT and if S1 is implemented as a PMOS, it will be coupled to Vx1. If S2 is implemented as a PMOS, the charge recycling circuit 10 will be coupled to V _OUT and if S2 is implemented as an NMOS, it will be coupled to Vx2.

[0046] FIGs. 8A-8C show the present charge recycling circuit 10 applied to a buck converter 82. The high-side switch implemented as either a PMOS (FIG. 8A) or an NMOS (FIG. 8B). In both cases, when one power MOSFET is turning off, its gate capacitance charges are transferred to LR by directly connecting LR across its gate capacitance. These charges stored in LR are then transferred directly to the gate capacitance of the other power MOSFET to turn it on by directly connecting LR across the gate capacitance of the other power MOSFET.

[0047] FIGs. 9A-9C show the present charge recycling circuit 10 applied to two power MOSFETS in DC-DC converters of any topology. In FIG. 9A, the charge recycling circuit 10 is applied to power MOSFETS when one is PMOS and the other is NMOS. FIG. 9B, the charge recycling circuit 10 is applied to power MOSFETS when both are NMOS. In FIG. 9C, the charge recycling circuit 10 is applied to power MOSFETS when both are NMOS.

[0048] While specific embodiments of the present invention have been shown and described, it should be understood that other modifications, substitutions and alternatives are apparent to one of ordinary skill in the art. Such modifications, substitutions and alternatives can be made without departing from the spirit and scope of the invention, which should be determined from the appended claims.

[0049] Various features of the invention are set forth in the appended claims.