Title:
CIRCUIT-BOARD LAYOUT EVALUATION APPARATUS, CIRCUIT-BOARD LAYOUT EVALUATION METHOD, AND CIRCUIT-BOARD LAYOUT DESIGNING SYSTEM
Document Type and Number:
WIPO Patent Application WO/2012/121293
Kind Code:
A1
Abstract:
The present invention searches for wiring that should be considered to be electrically connected via components, without complicated settings. Provided are: an evaluating object specifying unit that specifies the wiring to be evaluated; a passive component extraction unit that extracts passive components connected to the wiring; a two-terminal electrical-net searching unit and a multi-terminal electrical-net searching unit that search for wiring through which signals are propagated via the passive components; and an evaluating unit that evaluates a circuit-board layout, taking into consideration the wiring for which the search was executed. The multi-terminal electrical-net searching unit determines propagating candidate terminals from among terminals connected to the wiring to be evaluated, on the basis of the external shape of the multi-terminal electrical-net searching unit, evaluates a plurality of terminals, among the propagating candidate terminals, connected in common to another component via the wiring as a group of non-propagating terminals, removes the group of non-propagating terminals including the terminals connected to the wiring to be evaluated from the propagating candidate terminals, and adds wiring connected to the remaining terminals to the wiring to be evaluated.
Inventors:
MATSUMOTO TAKEHIDE
Application Number:
PCT/JP2012/055833
Publication Date:
September 13, 2012
Filing Date:
March 07, 2012
Export Citation:
Assignee:
SHARP KK (JP)
MATSUMOTO TAKEHIDE
MATSUMOTO TAKEHIDE
International Classes:
G06F17/50; H05K3/00
Foreign References:
| JP2008197862A | 2008-08-28 | |||
| JP2009069884A | 2009-04-02 | |||
| JPH07200651A | 1995-08-04 |
Attorney, Agent or Firm:
NOGAWA, Shintaro et al. (JP)
Shintaro Nogawa (JP)
Shintaro Nogawa (JP)
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Claims: