This invention relates to a controllable passive circuit element, in particular for use in a frequency regulator.

Increasingly as integrated circuits for systems such as mobile communications evolve, they accommodate more and more features (utilising both anologue and digital) and must support ever more diverse standards, features and operating ranges. One of the many consequences of this is the need to control analog blocks such as oscillators using digital tuning techniques rather than analog tuning because that provides a more natural alignment of the (e.g.) analog radio frequency systems with the central digital control systems with which they communicate.

Digitally controlled oscillators (DCOs) are known which rely on the creation of a digitally controlled component value. A first well known technique for creating a component, for example a capacitor, with a digitally-controlled value is the binary-weighted array, comprising a plurality of fixed-value capacitor segments, whose values are uniquely related to others in the array by a power of 2, which can be selectively connected in parallel into circuit using switches operating under digital control. However, this technique is limited in its programming resolution by the physical nature of the fixed-value capacitor array segments.

The problem of creating a DCO is also tackled in, for example, Staszewski et al, IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, Vol.40, No.1 1 , November 2003, 814-28 which deploys a component (in this case a capacitor) whose value can be varied by varying the voltage across its two terminals. In this case one or several varactors (voltage- dependent capacitors) are used. A specific feature of this arrangement focuses on the least significant bit (LSB) of the array. The varactor can be varied by continuously varying the analog voltage between two preset voltage levels, however this has a non-linear response to the digital code applied. An alternative is to "dither" between two states of a component, for example two preset voltage levels each with associated varactor capacitance values, with a duty cycle that can be varied using a digital signal thus creating an effective varactor capacitor value associated with the time-average of the two states. Such a duty cycle can be conveniently delivered by a sigma-delta (ΣΔ) modulator that converts a digital control number to a ΣΔ serial bit stream. The precision of this component's value is highly dependent on the precision of the preset voltage levels, and this is hard to maintain to high precision because of the difficulty of delivering a reliable analog voltage which will not vary with temperature, stress, noise and aging. Similarly, a variable resistor equivalent could be constructed using a MOS device whose gate voltage is similarly dithered between two preset voltage levels, according to a dither control. Again, this exhibits precision challenges due to the reliance on analog voltages which might vary with temperature, stress, noise and aging.

The present invention is derived from the realisation that there exists the need to provide an extremely precise digital control of the effective value of a passive component for use with, for example an oscillator, and which possesses a linear response to the digital code applied. Therefore, the present invention and its embodiments addresses the above described problems and desires.

According to a first aspect of the invention there is provided a controllable passive circuit element including:

a first terminal and a second terminal;

a passive circuit control input to which a control signal is applied;

a first passive circuit component having a first impedance type and a first impedance value;

a second passive circuit component of the same type as the first passive circuit component, the second passive circuit component having the same impedance type as the first passive circuit component and a second impedance value different to the first impedance value of the first passive circuit component; and a control means for dithering the first passive circuit component and the second passive circuit component over a period of time in accordance with a control state derived from the control signal so as to produce an impedance between the first and second terminals with an effective time-averaged impedance value which lies at the first impedance value or second impedance value, or between the first impedance value and the second impedance value, dependent upon the control signal applied to the control circuit input.

The passive circuit element exhibits a time-averaged equivalent value that can be controlled extremely accurately,which varies extremely linearly with the control signal value and which exhibits minimal uncompensated variation with temperature, stress and aging. Preferably, the control means includes a switching arrangement.

Preferably, the switching arrangement includes a first switch means to connect the first passive circuit component between the first and second terminals and a second switch means to connect the second passive circuit component between the first and second terminals, the first and second switch means being controllable by the control state derived from the control signal.

Beneficially, only one of the first or second passive circuit components may be connected between the first and second terminals for a given control state.

Preferably, the control means includes a dither generator for deriving the control state from the control signal and forwarding the control state to the switch arrangement. The dither generator ensures that a maximum of one passive circuit component is functionally connected into the first and second terminals of the passive circuit element at any one time, either by parallel combinations of passive circuit components each connected in series with a switch or by series combinations of passive circuit components each connected in parallel with a switch.

Preferably, there is included included or further included a digital-to-analog converter to convert a digital control code into a ΣΔ pulse stream to be inserted into the passive circuit input as the control signal.

In a first embodiment of the invention, the first and second passive circuit components are capacitors.

Preferably, the first and second passive circuit components are sampled- data switched capacitors. Use of the sampled-data switched capacitor pair in the controllable passive circuit makes the circuit behave in a similar manner to a switched resistor pair arrangement, and the precision can be made independent of the pulse width.

In a preferred embodiment of the invention, the passive circuit components are resistors. This enables a synthesised resistor value to be effected, whose value lies between that of each of the physical resistors, or at the value of one of the resistors.

In a further preferred embodiment of the invention the passive circuit components are inductors. This enables a synthesised inductor value to be effected whose value lies between that of each of the physical inductors, or at the value of one of the inductors.

Desirably, the passive circuit element includes a further control means including an external frequency source for providing a clock frequency. When the sampled-data switched capacitor is implemented, there is included a further control means to drive the switch control signals i.e. the control state.

In a further aspect of the invention there is provided a frequency regulator including the controllable passive circuit element of the invention. Use of the controllable passive circuit element provides a precise and accurately controllable frequency output from the frequency regulator.

In an alternative aspect of the invention there is provided an oscillator system including an oscillator and the above-mentioned controllable passive circuit element, for controlling the oscillator. Use of the controllable passive circuit element provides high precision control of the oscillator. Preferably, the controllable passive circuit element is monolithically intregated. This is desirable for use in small devices, for example mobile phones and tablet computers.

According to a further aspect of the invention there is provided a method of providing an impedance between a first and second terminal of the above- mentioned passive circuit element, the method including:

applying a control signal to the passive circuit control input;

dithering the first passive circuit component and the second passive circuit component over a period of time in accordance with a control state derived from the control signal, wherein the first and second passive circuit components have different impedance values;

producing an impedance between the first and second terminals with an effective time-averaged impedance value which lies at the first impedance value or second impedance value, or between the first impedance value and the second impedance value, dependent upon the control signal applied to the control circuit input.

Beneficially, the method includes inputting a control value into a ΣΔ digital-to analog-converter to create a ΣΔ bitstream to be applied to the passive circuit control input.

Preferably, in a first control state a first switch means connects the first passive circuit component between the first and second terminals.

Further, in a second control state a second switch means connects the second passive circuit component between the first and second terminals. Preferably, wherein only one of the first or second passive circuit components may be connected between the first and second terminals for a given control state.

Preferably, wherein the passive circuit components are sampled-data switched capacitors and the passive circuit fully charges and discharges each capacitor. The switching frequency of the switching arrangement is selected to allow each capacitor to be fully charged and discharged. This advantageously ensures that the charge flow can be made independent of the pulse width of the control signal.

Beneficially, wherein an external clock frequency is applied to the control signal. by an external frequency source.

Preferably, wherein the effective impedance can be varied in dependence on the control value input to the ΣΔ DAC (i.e. duty cycle) and/or the frequency of the clock signal F _D AC provided by the external frequency source.

Whilst the invention has been disclosed above it extends to any inventive combination of the features set out above, or in the following description, drawings or claims. The invention will now be decribed, by way of example only, with reference to the accompanying drawings in which:-

Figure 1 is a circuit diagram of an arrangement of similar capacitor pairs; Figure 2 is a circuit diagram of an arrangement of similar resistor pairs;

Figure 3 is a circuit diagram of an arrangement of similar inductor pairs;

Figure 4 is a circuit diagram of a first embodiment of a passive circuit element according to the invention; Figure 5 is a circuit diagram of a second embodiment of a passive circuit element according to the invention;

Figure 6 is the clock generator output specific to the circuit of Figure 5; and

Figure 7 is a frequency regulator incorporating a passive circuit element according to Figure 5.

Referring firstly to Figure 1 , there is shown a similar component pair 1 which is formed of a first capacitor 2a having a first capacitance value Ci arranged in parallel with a second capacitor 2b having a capacitor value C2 that is different to the value of the first capacitor 2a. A first and second switch means, for example a first and second switch 3a, 3b is arranged in series with the first capacitor 2a and second capacitor 2b respectively. The first capacitor 2a and first switch means 3a and the second capacitor 2b and second switch means are arranged between a first and second terminal of the passive circuit element. When the first switch 3a is closed the first capacitor 2a is connected between the first and second terminals 4a, 4b. Similarly, when the second switch 3b is closed, the second capacitor 2b is connected between the first and second terminals 4a, 4b. When the first and second switches 3a, 3b are opened respectively the first and second capacitors 2a, 2b are consequently disconnected from between the first and second terminals 4a, 4b. The components 2a, 2b need not be a capacitor and may instead be a first and second resistor 6a, 6b, with different resistance values Ri and R ₂ , as demonstrated in Figure 2. In an alternative embodiment of the invention, the components may be arranged in series each with a switch connected in parallel and the components 2a and 2b may instead be a first and second inductor 7a, 7b, with different inductance values, that are arranged in, whereby the switches 3a, 3b are arranged in parallel with the respective inductors 7a, 7b, as shown in Figure 3.

Impedance may be any of three different types including capacitance, resistance, or inductance. Therefore, regardless of whether the component used in the similar component pair 1 is a capacitor, resistor or inductor, it has an impedance type associated with it and therefore has an associated impedance value. For each component of a similar component pair 1 , the impedance types are the same and the impedance values are similar but not identical. Therefore, the impedance value of the first component, e.g. the first capacitor 2a, is different to the impedance value of the second component, e.g. the second capacitor 2b, of the similar element 1 of Figure 1 .

Capacitance, resistance and inductance all represent forms of impedance and the above principles would apply to any of these.

Switches associated with the similar pairs of components are driven by a selected one-bit control sequence, for example a ΣΔ bitstream. The value of the effective impedance observed between the first and second terminals of the similar element is in accordance with the input control sequence. Instead of dithering between two states associated with the component, for example a first and second voltage value on a varactor as described previously, the dithering occurs between the two states of the circuit, e.g. similar components having the same impedance type and two similar (but different) impedance values. The time-averaged impedance value is obtained between the first and second terminals 4a, 4b, and the time-averaged impedance value may either i) lie between the impedance values of the first and second components 2a, 2b or ii) lie at the first impedance value associated with the first passive circuit component 2a or iii) lie at the second impedance value associated with the second passive circuit component 2b. This time-averaged impedance corresponds to a single equivalent impedance across the first and second terminals. The dithering is controlled by the activation of each switch 3a, 3b in response to a control state derived from the control signal fed to the passive circuit control input 5. For example, the bitstream is a representation of a digital control word and by its very nature the values are either 0 or 1 . For example in the case that the control state is 1 the first switch is arranged to be closed while the second switch is arranged to be opened, however when the control state is 0, the first switch is arranged to be closed whilst the second switch is arranged to be opened. In this arrangement only one of the first or second passive components are permitted to be connected between the first an second terminals, and it is the control state derived from the control signal that controls the relative switching of the switch means 3a, 3b.

In each of the arrangements in Figure 1 , Figure 2 and Figure 3, the principle of determining the time-averaged impedance value between the first and second terminals 4a, 4b is the same and shall now be described using the similar capacitor pair example of Figure 1 .

Figure 4 shows a similar capacitor pair (Ci, C2) 1 with dissimilar values that are alternately connected into circuit using switches 3a, 3b driven by control state derived from a ΣΔ bitstream via a dither generator 9. The ΣΔ bitstream is generated by a digital-to-analog converter (DAC) 10, which takes an N-bit word representing a desired value which is then decoded by the ΣΔ DAC to a single- bit data sequence (whose time-average voltage value is an analog equivalent to the digital word). This bitstream drives the switches 3a, 3b via the dither generator 9, where (for example) a logic level "1 " closes the first switch 3a using a first clock signal and a logic level "0" closes the second switch 3b using a second clock signal, the clock signals being non-overlapping in order that switches 3a and 3b are not closed simultaneously. The logic level "1" defines the first control state and the logic level "0" defines the second control state. Therefore the control state derived from the control signal determines the arrangement of the switches which effects the time-averaged value of the impedence between the first and second terminals 4a, 4b.

The value of the resulting synthesized capacitance CEFF will be:

where DACFS is the full-scale output value of the DAC 10 and DAC is the instantaneous value of the DAC input at a given time. One limitation to the precision over time of the average value is the timing precision of the pulse- width of successive bits in the ΣΔ bitstream. However, this can be controlled far more accurately than the value of two analogue voltages as used in prior art.

An important benefit of this approach to deriving CEFF is that there is an optimally linear relationship between the value of the DAC code word and the synthesized value of CEFF- Furthermore, in an application where no time limit is imposed on the ΣΔ averaging sequence (e.g. where only DC signals are being considered) then there is no theoretical limit to the precision that CEFF can attain, therefore CEFF can, in theory, have infinite resolution. Therefore, by dithering between two components having the same impedance type with dissimilar impedance values a synthesized equivalent component value CEFF according to the above-mentioned dither algorithm can be obtained by time-averaging the impedance values. Since the circuit dithers between the first and second passive circuit components having the same impedance type and a first and second impedance value, the time averaged value will lie between the first component value and the second component value. Alternatively, the time-averaged value can lie at the impedance value of the first or second component. Importantly, there is no limit to the resolution of the effective component value, enabling CEFF to be controlled extremely accurately.

Figure 5 shows a second embodiment of the invention wherein the similar capacitor pair arrangement 1 of Figure 1 is replaced by a pair of sampled-data similar switched capacitors 13a, 13b, where for example an additional switch is arranged in parallel with respective capacitors and driven in the opposite phase to the series switch (though other arrangements for switches in sampled-data switched capacitors are well known). Such sampled- data switched capacitors are a known means of realising an analog sampled- data system. When a capacitor is successively charged and discharged at a frequency F _C LK then the time-averaged current that flows through the switched capacitor 13a, 13b is ^ ' ^½ , where C is the value of the capacitor and V is the voltage across the switched capacitor. Therefore, the sampled-data switched capacitor 13a, 13b behaves in a similar manner to a resistor when measured over time. The circuit of Figure 5 also includes an input F _D AC for a clock signal which can be provided by an oscillator or some other external frequency source.

A dither generator 9 generates non-overlapping clock pulses Φ1 and Φ2 to activate the first switch 3a or the second switch 3b respectively depending on the instantaneous control state of the 1 -bit ΣΔ bitstream, as illustrated in Figure

6, with complementary clock pulses or being routed to third and fourth switches 14a, 14b respectively. The clock pulses can be considered to provide the control state to the first and second switch 3a, 3b and to third and fourth switches 14a, 14b.

This similar sampled-data switched capacitor pair 13c is equivalent to a time-averaged resistor with conductance GEFF and is given by:

where F _D AC is the clock frequency of the 1 -bit ΣΔ bitstream provided by an external frequency generator (not shown). Therefore, this similar sampled-data switched capacitor pair arrangement 13c behaves in a similar manner to the switched resistor pair 6c, but has the advantage that its time-averaged value can be controlled by two independent control means, namely the control value input to the ΣΔ DAC (i.e. duty cycle) and the frequency of the clock signal F _D AC- This provides two independent means of varying the conductance. An advantage of the sampled-data switched capacitor pair compared to the switched resistor pair 6c is that the resulting conductance GEFF is no longer dependent on the ΣΔ bitstream pulsewidth because the capacitors fully charge and discharge on each cycle and so charge flow can be made independent of pulse width. In addition to the dual controls, the absolute accuracy of the final conductance value will be subject to the absolute values of Ci and C2 which may vary slightly over temperature, stress and aging; this can be controlled using other techniques as described in another of the applicant's co-pending applications.

The dual-control of the effective conductance of the switched capacitor pair 13c may be usefully deployed in a number of applications. One specific example is in a frequency regulator 12 as shown in Figure 7 and as described in the applicant's co-pending UK Patent application entitled "Frequency Regulator" filed on 28 March 2013, the entire contents of which are herein incorporated by reference.

The switched capacitor (SC) pair of Figure 7 implements a frequency controlled variable resistor (FCVR) 15. The value of the FCVR 15 is dependent both on the frequency F _D AC and on the value of the digital control word generated by the SAR analog-to-digital converter 16, D _S AR- The FCVR 15 can be placed in a bridge arrangement 20 as shown in Figure 7. An amplifier 17, low- pass filter (LPF) 18 and comparator arrangement 19 senses the difference in voltage between the "Sense node" and "Ref node" and delivers a logic signal back to the SAR analogue to digital converter 16, which generates an N-bit control word DSAR-

If a fixed, known frequency F _C AL is applied to F _D AC, then the feedback loop of the bridge will adjust DSAR which in turn will adjust the conductance of the FC VR 15. This process will continue until the "Sense node" and "Ref node" are equal in value. With this final value of D _S AR the bridge is balanced, and the frequency regulator 12 is calibrated.

Henceforth, the value of D _S AR, Balanced is maintained unchanged. Additional input frequencies F ₀ sc can be applied to the frequency regulator 12, and the bridge will only balance if the frequency of F ₀ sc is equal that of the original F _C AL- Therefore, when presented with a calibration frequency, the frequency regulator 12 is able to self-calibrate by adjusting the ΣΔ dither code.

An important benefit of the use of the SC pair-based FCVR 15 in conjunction with a ΣΔ DAC input control signal is that any quantisation noise in the DAC 10 will be suppressed by the noise-shaping characteristic of the ΣΔ converter.

Various modifications to the principles described above would suggest themselves to the skilled person. For example, the components used in the similar component pair 1 , as illustrated in Figure 1 , need not be capacitors 2a, 2b and may instead be resistors 6a, 6b or inductors 7a, 7b as shown in Figures 2 and 3 respectively. Whilst it is beneficial for the capacitors or the resistors to be arranged in parallel with series switches, alternative arrangements may be implemented e.g. the components may be arranged in series with parallel switches. Similarly, whilst it is beneficial for the similar inductor pair to be arranged in series with parallel switches, alternative arrangements may be implemented.

Further, more than two components can be used to provide an effective component value.