Title:
DATA TRANSFER DEVICE AND DATA TRANSFER METHOD
Document Type and Number:
WIPO Patent Application WO/2021/111583
Kind Code:
A1
Abstract:
This data transfer device comprises: a plurality of masters, each including a buffer and calculating a remaining-time counter on the basis of the amount of data in the buffer; a memory system that performs data transfer with the plurality of masters and that has a memory access prohibition period during which access from the plurality of masters is intermittently prohibited; a bus arbiter that performs arbitration between the plurality of masters on the basis of the remaining-time counter; and a remaining-time counter adjustment unit that adds, to at least one of the plurality of masters, a remaining-time counter offset for adjusting the remaining-time counter until the start of the memory access prohibition period.
Inventors:
MURATA YUTAKA (JP)
TSUCHIDA RYUSUKE (JP)
TSUCHIDA RYUSUKE (JP)
Application Number:
PCT/JP2019/047625
Publication Date:
June 10, 2021
Filing Date:
December 05, 2019
Export Citation:
Assignee:
OLYMPUS CORP (JP)
International Classes:
G06F13/16
Foreign References:
| JP2019134240A | 2019-08-08 | |||
| JP2004252523A | 2004-09-09 | |||
| JP2007108996A | 2007-04-26 | |||
| JP2003337741A | 2003-11-28 |
Attorney, Agent or Firm:
MATSUNUMA Yasushi et al. (JP)
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