TECHNICAL FIELD

[0001] The present invention relates generally to the field of data processing systems, and more particularly to an improved data logging and user visualization system.

BACKGROUND ART

[0002] Programmable integrated circuits (ICs), such as field programmable gate arrays (FPGAs), are known in prior art. For example, U.S. Patent No. 8,775,986, entitled "Software Debugging of Synthesized Hardware," is directed to a system for debugging an object- orientated high-level language (HLL) such as Java or C++ that includes an IC having a set of programmable resources and a microprocessor circuit. The system includes a computing platform coupled to the programmable IC. The computing platform is programmed to implement a software debug-configuration tool or module in response to user input selecting one or more variables to observe/control in a function of the HLL program. The patent also discloses an integrated circuit that includes a set of programmable resources specially programmed to implement a logic circuit having one or more registers to be observed in a memory.

[0003] U.S. Patent Publication No. 2014/0196050, entitled "Processing System Including a Plurality of Cores and Method of Operating the Same," is directed to a system and method for allocating resource among cores in a multi-core system, in particular a system-on-chip having a plurality of cores. The system determines cores that are able to process tasks to be performed, and uses history of usage information to select a core to process the tasks.

[0004] U.S. Patent Publication No. 2014/0229723, entitled "Random Access to Signal Values of an FPGA at Runtime," is directed to a method of assessing a signal value of an FPGA at runtime. A data processing system with a control computer and a realtime system is provided. The realtime system comprises a computation node with a CPU and an FPGA, which in the exemplary embodiment is a Xilinx FPGA.

BRIEF SUMMARY OF THE INVENTION

[0005] With parenthetical reference to the corresponding parts, portions or surfaces of the disclosed embodiment, merely for purposes of illustration and not by way of limitation, provided is a data processing system (15) comprising a programmable hardware element (17), a processor (16) communicating with the programmable hardware element, a graphic user interface (22a), the graphic user interface comprising a user display (73, 74), the processor comprising one or more data creation elements (23), the programmable hardware element comprising one or more data creation elements (35), a data aggregator (26) configured and arranged to receive data signals (100) from the processor data creation elements at one or more processor rates, to receive data signals (101) from the programmable hardware element data creation elements at one or more hardware rates, and to aggregate the data signals, to thereby provide aggregated data output signals at a common rate (104a), a data selector (27) configured and arranged to receive a control signal (106) from the graphic user interface and, as a function of the control signal, to select a subset of signals that are sourced from the aggregated data output signals, to thereby provide a selected subset of data output signals ( 105), and a data buffer (30) configured and arranged to receive signals sourced from the selected subset of data output signals and to communicate the data signals to the display via the processor,

whereby a user can visualize the data signals in real time.

[0006] The programmable hardware element may further comprise a triggering module (29) configured and arranged to receive a control signal (109a) from the graphic user interface for determining which signal (108) sourced from the aggregated data output signals to trigger upon and to output, as a function of the control signal, one or more viewable data output signals (1 1 1a) that are sourced from the aggregated data output signals. The programmable hardware element may further comprise a decimation module (28a) configured and arranged to receive a rate control signal (107a) from the graphic user interface and, as a function of the rate control signal, to decimate signals (105) that are sourced from the aggregated data output signals, to thereby provide data output signals at a selected rate ( 108). The signals sourced from the aggregated data output signals received by the decimation module may comprise the one or more viewable output data signals from the triggering module. The signals sourced from the aggregated data output signals received by the data buffer may comprise the data output signals at a selected rate from the decimation module. The signals sourced from the aggregated data output signals received by the triggering module may comprise the data output signals at a selected rate from the decimation module. The signals sourced from the aggregated data output signals received by the data buffer may comprise the one or more viewable output data signals from the triggering module.

[0007] The programmable hardware element may comprise a field programmable gate array (FPGA). The processor may comprise a plurality of ARM processing cores (65, 66).

[0008] The data aggregator may be configured and arranged to provide up to about 300 aggregated data output signals. The data selector may comprise a signal multiplexer. The data selector may be configured to provide a selected subset of up to about 16 data output signals. The processor rates of the data signals from the one or more data creation elements of the processor may be less than about 100 kHz and the one or more hardware rates from the data creation elements of the programmable hardware element may be greater than about 100 kHz. The common rate of the aggregated data output signals may be the same or greater than any of the one or more hardware rates from the data creation elements of the programmable hardware element. The common rate may be about 100 MHz or greater. The data aggregator may be configured and arranged to oversample the data signals from the processor to thereby aggregate the data signals to the common rate. The data aggregator may be configured and arranged to oversample the data signals from the programmable hardware element to thereby aggregate the data signals to the common rate.

[0009] The one or more data creation elements of the programmable hardware element comprise one or more external data signal inputs (36) and/or one or more internal data generation programs (37) that produce one or more data signals. The one or more data creation elements of the processor may comprise one or more external data signal inputs (24) and/or one or more internal data generation programs (25) that produce one or more data signals. The signals from the external data signal inputs may be selected from a group consisting of digital signals sourced from an analog to digital converter (63). The analog to digital converter may be configured to receive input voltages from a sensor on an external controllable hardware device. The analog to digital converter may be configured to receive input voltages from sensors selected from a group consisting of a motor current feedback sensor, a temperature sensor, a position sensor and a bus voltage sensor. The internal data generation program may comprise a current loop algorithm and the signals from the program may be selected from a group consisting of motor current error, motor current command, motor state, fault conditions, over current condition and temperature. The trigger module may be configured and arranged to receive a second control signal from the graphic user interface for determining a triggering methodology, and to output, as a function of the first and second control signals, one or more viewable data output signals that are sourced from the aggregated data output signals.

[0010] In another aspect, a data processing system is provided comprising a programmable hardware element ( 17), a processor (16) communicating with the programmable hardware element, a graphic user interface (22b), a memory medium (34), the processor comprising one or more data creation elements (23), the programmable hardware element comprising one or more data creation elements (35), a data aggregator (26) configured and arranged to receive data signals (100) from the processor data creation elements at one or more processor rates, to receive data signals (101) from the programmable hardware element data creation elements at one or more hardware rates, and to aggregate the data signals, to thereby provide aggregated data output signals at a common rate ( 104b), and a data buffer (45) configured and arranged to receive signals sourced from the aggregated data output signals and to communicate the data signals to the memory medium, whereby a user can store the data signals.

[0011] The memory medium may comprise an external storage device. The external storage device may comprise an SD card. The programmable hardware element may further comprise a SD card modulation module (32) configured and arranged to convert multiple parallel data signals (1 12) to a serial data stream for storage on the SD card. The processor may further comprise an SD card demodulation module (19) configured and arranged to convert the serial data stream into multiple parallel data signals. The programmable hardware element may further comprise a SD card write interface (46) configured and arranged to write data to the SD card or to freeze an SD card clock as a function of the amount of data in the data buffer. The processor may comprise a second memoiy medium (20) and the programmable hardware element may further comprise a SD card read interface (47) configured and arranged to read data stored on the SD card and a second data buffer (33) communicating with the second memory medium.

[0012] The system may further comprise a data selector (27) configured and arranged to receive a control signal (106) from the graphic user interface and, as a function of the control signal, to select a subset of signals (105) that are sourced from the aggregated data output signals, to thereby provide a selected subset of data output signals. The programmable hardware element may further comprise a triggering module (31) configured and arranged to receive a control signal (109b) from the graphic user interface for determining which signal sourced from the aggregated data output signals to trigger upon and to output, as a function of the control signal, one or more viewable data output signals that are sourced from the aggregated data output signals. The programmable hardware element may further comprise a decimation module (28b) configured and arranged to receive a rate control signal ( 107b) from the graphic user interface and, as a function of the rate control signal, to decimate signals that are sourced from the aggregated data output signals, to thereby provide data output signals at a selected rate (108). The signals sourced from the aggregated data output signals received by the triggering module may comprise the data output signals at a selected rate from the decimation module. The signals sourced from the aggregated data output signals received by the data buffer may comprise the one or more viewable output data signals from the triggering module. [0013] The programmable hardware element may comprise a field programmable gate array (FPGA). The processor may comprise a plurality of ARM processing cores.

[0014] The data aggregator may be configured and arranged to provide up to about 300 aggregated data output signals and the data selector may be configured to provide a selected subset of up to about 16 data output signals. The processor rates of the data signals from the one or more data creation elements of the processor may be less than about 100 kHz and the one or more hardware rates from the data creation elements of the programmable hardware element are greater than about 100 kHz. The common rate of the aggregated data output signals may be the same or greater than any of the one or more hardware rates from the data creation elements of the programmable hardware element. The common rate may be about 100 MHz or greater. The data aggregator may be configured and arranged to oversample the data signals from the processor to thereby aggregate the data signals to the common rate. The data aggregator may be configured and arranged to oversample the data signals from the programmable hardware element to thereby aggregate the data signals to the common rate. The one or more data creation elements of the programmable hardware element may comprise one or more external data signal inputs and/or one or more internal data generation programs that produce one or more data signals. The one or more data creation elements of the processor may comprise one or more external data signal inputs and/or one or more internal data generation programs that produce one or more data signals. The signals from the external data signal inputs may be selected from a group consisting of digital signals sourced from an analog to digital converter. The analog to digital converter may be configured to receive input signals from a sensor on an external controllable hardware device. The analog to digital converter may be configured to receive input voltages from sensors selected from a group consisting of a motor current feedback sensor, a temperature sensor, a position sensor and a bus voltage sensor. The internal data generation program may comprise a current loop algorithm and the signals from the program may be selected from a group consisting of motor current error, motor current command, motor state, fault conditions, over current condition and temperature. The trigger module may be configured and arranged to receive a second control signal from the graphic user interface for determining a triggering methodology, and to output, as a function of the first and second control signals, one or more viewable data output signals that are sourced from the aggregated data output signals.

[0015] In another aspect, a method of processing data is provided comprising the steps of providing a programmable hardware element, a processor communicating with said programmable hardware element, and a graphic user interface having a user display, providing data signals to a data aggregator of said programmable hardware element through said processor at one or more processor rates, providing data signals to said data aggregator through said programmable hardware element at one or more processor rates, aggregating said data signals, to thereby provide aggregated data output signals at a common rate, providing a control signal to a data selector of said programmable hardware element, as a function of said control signal, selecting a subset of signals that are sourced from said aggregated data output signals, to thereby provide a selected subset of data output signals, providing signals sourced from said selected subset of data output signals to a data buffer, and communicating said data signals to said display via said processor, whereby a user can visualize said data signals in real time.

[0016] In another aspect, a method of processing data is provided comprising the steps of providing a programmable hardware element, a processor communicating with said programmable hardware element, a graphic user interface and a memory medium, providing data signals to a data aggregator of said programmable hardware element through said processor at one or more processor rates, providing data signals to said data aggregator through said programmable hardware element at one or more processor rates, aggregating said data signals, to thereby provide aggregated data output signals at a common rate, providing signals sourced from said aggregated data output signals to a data buffer, and communicating said data signals to said memory medium, whereby a user can store said data signals.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG. 1 is a general schematic view of a first embodiment of the improved data visualization and logging system.

[0018] FIG. 2 is detailed schematic view of the data aggregator shown in FIG. 1.

[0019] FIG. 3 is a flow chart of the data aggregator shown in FIG. 1 processing.

[0020] FIG. 4 is detailed schematic view of the decimation module shown in FIG. 1 .

[0021] FIG. 5 is a flow chart of the decimation module shown in FIG. 1 processing.

[0022] FIG. 6 is a flow chart of the triggering module shown in FIG. 1 processing

[0023] FIG. 7 is a detailed schematic view of the SD card modulation module shown in FIG. 1.

[0024] FIG. 8 is a flow chart of the SD card modulation module shown in FIG. 7 processing.

[0025] FIG. 9 is a flow chart of the SD card demodulation module shown in FIG. 1 processing. [0026] FIG. 10 is a top level block diagram of components of the system shown in FIG. 1.

[0027] FIG. 1 1 is a screen shot of a sample real-time GUI display shown in FIG. 1.

[0028] FIG. 12 is a sample user input screen shot of the real-time GUI display shown in FIG. 1 1.

[0029] FIG. 13 is a screen shot of a sample post-process data storage GUI display shown in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030J At the outset, it should be clearly understood that like reference numerals are intended to identify the same structural elements, portions or surfaces consistently throughout the several drawing figures, as such elements, portions or surfaces may be further described or explained by the entire written specification, of which this detailed description is an integral part. Unless otherwise indicated, the drawings are intended to be read (e.g., cross- hatching, arrangement of parts, proportion, degree, etc.) together with the specification, and are to be considered a portion of the entire written description of this invention. As used in the following description, the terms "horizontal", "vertical", "left", "right", "up" and "down", as well as adjectival and adverbial derivatives thereof (e.g. , "horizontally", "rightwardly", "upwardly", etc.), simply refer to the orientation of the illustrated structure as the particular drawing figure faces the reader. Similarly, the terms "inwardly" and "outwardly" generally refer to the orientation of a surface relative to its axis of elongation, or axis of rotation, as appropriate.

[0031] Memory Medium—Any of various types of memory devices or storage devices. The term "memory medium" is intended to include an installation medium, (e.g., a CD-ROM, Flash drive, USB stick, DVD, blue ray, etc.), a computer system memory or random access memory (e.g., DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.)., or a nonvolatile memory such as solid state media (e.g., SD card, USB drive, solid state drive), magnetic media, (e.g., a hard drive, optical storage etc.). The memory medium may comprise other types of memory as well, or combinations thereof. In addition, the memory medium may be located in a first computer in which the programs are executed, and/or may be located in a second different computer which connects to the first computer over a network, such as the Internet. The term "memory medium" may include two or more memory mediums which may reside in different locations, e.g., in different computers that are connected over a network. "Computer-readable medium" comprises a medium configured to store or transport computer readable code, or in which computer readable code may be embedded. Some examples of computer-readable medium are CD-ROM disks, ROM cards, floppy disks, flash ROMS, RAM, nonvolatile ROM, magnetic tapes, computer hard drives, conventional hard disks, and servers on a network.

[0032] Data Link—any physical transmission medium, such as a bus, network, and/or other physical transmission medium that conveys signals such as electrical, electromagnetic, or digital signals. A data link may be wired or wireless.

[0033] Programmable Hardware Element—includes various hardware devices comprising multiple programmable function blocks connected via a programmable interconnect. Examples include FPGAs (Field Programmable Gate Arrays), PLDs (Programmable Logic Devices), FPOAs (Field Programmable Object Arrays), and CPLDs (Complex PLDs). The programmable function blocks may range from fine grained (combinatorial logic or look up tables) to coarse grained (arithmetic logic units or processor cores). A programmable hardware element may also be referred to as "reconfigurable logic".

[0034] Computer or Processor— includes internet appliances, hand-held devices, workstations, network appliances, wearable computers, multi-processor systems, programmable consumer electronics, personal computer systems (PC), network PCs, mainframe computers, personal digital assistant (PDA), television system, grid computing system, or other device or combinations of devices and the like. Some examples of processors are microprocessors, microcontrollers, CPUs, PICs, PLCs, PCs or microcomputers. In addition, it is meant to encompass processing that is performed in a distributed computing environment, where tasks or modules are performed by more than one processing device or by remote processing devices that are run through a communications network, such as a local area network, a wide area network or the internet. In general, the term "computer" can be broadly defined to encompass any device (or combination of devices) having at least one processor that executes instructions from a memory medium. Thus, the term computer and processor are to be interpreted expansively.

[0035] Program— the term "program" is intended to have the full breadth of its ordinary meaning. The term "program" includes a software program which may be stored in a memory and is executable by a processor or a hardware configuration program useable for configuring a programmable hardware element (e.g. firmware, etc.).

[0036] Software Program— the term "software program" is intended to have the full breadth of its ordinary meaning, and includes any type of program instructions, code, script and/or data, or combinations thereof, that may be stored in a memory medium and executed by a processor. Exemplary software programs include programs written in text-based programming languages, such as C, C++, PASCAL, FORTRAN, COBOL, JAVA, assembly language, etc., graphical programs (programs written in graphical programming languages), assembly language programs, programs that have been compiled to machine language, scripts, and other types of executable software. A software program may comprise two or more software programs that intemperate in some manner. Note that various embodiments described herein may be implemented by a computer or software program. A software program may be stored as program instructions on a memory medium.

[0037] Firmware Program~a program (e.g., netlist, bit file, etc.) that can be used to program or configure a programmable hardware element (e.g. firmware, VHDL Verilog, etc.).

[0038] Graphical User Interface-this term is intended to have the full breadth of its ordinary meaning. The term "Graphical User Interface" is often abbreviated to "GUI". A GUI may comprise only one or more input GUI elements, only one or more output GUI elements, or both input and output GUI elements. A GUI may comprise a single window having one or more GUI Elements, or may comprise a plurality of individual GUI Elements (or individual windows each having one or more GUI Elements), wherein the individual GUI Elements or windows may optionally be tiled together.

[0039] Graphical User Interface Element—an element of a graphical user interface, such as for providing input or displaying output. Exemplary graphical user interface elements comprise input controls and output indicators.

[0040] Input Control—a graphical user interface element for providing user input to a program via an input device. An input control displays the value input by the user and is capable of being manipulated at the discretion of the user. Exemplary input controls include without limitation buttons, menus, dials, knobs, sliders, input text boxes, etc.

[0041] Input Device— any tool or device allowing a user to interact with an input control (e.g., mouse, keyboard, touchscreen)

[0042] Output Indicator— a graphical user interface element for displaying output from a program. Exemplary output indicators include status bars, charts, graphs, gauges, output text boxes, numeric displays, etc. An output indicator is sometimes referred to as an "output control".

[0043] Output Device—means any tool or device allowing a user to receive an output indicator (e.g. display screen, computer monitor, tablet screen, television, etc.)

[0044] Measurement Device— includes instruments, data acquisition devices, smart sensors, and any of various types of devices that are operable to acquire and/or store data. A measurement device may also optionally be further operable to analyze or process the acquired or stored data. Examples of a measurement device include an instrument, such as a traditional stand-alone "box" instrument, a computer-based instrument (instrument on a card) or external instrument, a data acquisition card, a device external to a computer that operates similarly to a data acquisition card, a smart sensor, one or more DAQ or measurement cards or modules in a chassis, an image acquisition device, such as an image acquisition (or machine vision) card (also called a video capture board) or smart camera, a motion control device (e.g. resolver, LVDT, etc.), and other similar types of devices. Exemplary "standalone" instruments include oscilloscopes, multimeters, signal analyzers, arbitrary waveform generators, spectroscopes, and similar measurement, test, or automation instruments.

[0045] Real Time— having a low latency compared to the rate of change of the signals being processed and operating in a deterministic manner.

[0046] To the extent that the definitions provided above are consistent with ordinary, plain and accustomed meanings (as generally evidenced, in alia, by dictionaries and/or technical lexicons), the above definitions shall be considered supplemental in nature. To the extent that the definitions provided above are inconsistent with ordinary, plain and accustomed meanings (as generally evidenced, inter alia, by dictionaries and/or technical lexicons), the above definitions shall control. If the definitions provided above are broader than the ordinary, plain and accustomed meanings in some aspect, than the above definitions will control at least in relation to their broadening aspects. ^'

[0047] Referring now to FIG. 1 , an improved data processing system is provided, an embodiment of which is generally indicated at 15. As shown, system 15 broadly includes processor 16 communicating via data links 42 with FPGA 17. As shown in FIG. 10, processor 16 and FPGA 17 are contained in a single housing 18 having 8 analog inputs, 4 analog outputs, 24 digital inputs/outputs 53, RS485 port 54, RS232 port 55, USB Uart port 56, JTAG port 57, USB OTG port 58, Ethernet port 59, two SD card slots 60 and 61 , and HDMI link 62 for connection to a display or monitor. Also contained in the unit are analog to digital converter 63 and digital to analog converter 64 that provide for 12 and 4 channels, respectively. The unit receives analog and digital signals, processes such signals at a high speed, and then provides signal visualization, signal logging and outputs for external hardware 38 operations.

[0048] As shown in FIG. 10, processor 16 generally includes first ARM processor core [0] 65 on which the operating system runs, second ARM processor core [1] 66 that runs a real-time data generation program, and 1 GB DDR RAM memory medium 21. A secondary on-chip memory unit is included for intra-core communication between core processor 65 and core processor 66. [0049] As shown in FIG. 10, core processor 65 runs graphic user interface (GUI) 22 connected to external monitor 73 via HDMI link 62 or via Ethernet link 59 to remote desktop computer 68. If connected via Ethernet link 59, inputs from mouse 70 and keyboard 69, or a touchscreen or any other user input device, are provided to GUI 22 through desktop 68 or any other computer or computer system. If operating via HDMI 62, inputs to GUI 22 from the user are through USB OTG port 58, which acts as a hub.

[0050] With reference to FIG. 1 , the general elements of processor 16 include SD card demodulation module 19, storage medium 20, processor memory 21 for both logging and visualization, post-run GUI display 22b and real-time GUI display 22a, and data creation element 23. As described above, in this embodiment storage medium 20 comprises an SD card [0] in SD Card slot 60, which acts as an embedded hard drive. In this embodiment, GUI display 22, both post-run and real-time, are operated through ARM processing core [0] 65 .

[0051] Data creation element 23 comprises data signals that are provided from both external inputs 24 and internal data generation programs 25. In this embodiment, internal data generation programs 25 are run on ARM processor core [1] 66. External inputs coming through processor 16 to data aggregator 26 may include UART 56 communications to processor 16 and any Ethernet 59 data through processor 16. In this embodiment, when not using Ethernet for a remote desktop, Ethernet port 59 can communicate with external devices, such as test or measurement equipment, to receive and send data to FPGA 17, where it can be logged and visualized. Data creation program 25 may, for example, be a motor control program run on processor 16 that operates on signals from the external environment and serves to command a specific motor current to a motor by operating upon feedback signals and other internal states. This program will generate several states and signals that can be logged and/or visualized.

[0052] As shown, the communications or data link 42 between processor 16 and FPGA 17 is provided, in this embodiment, thorough an AXI interface. This includes the communication of data signals from data creation element 23 to data aggregator 26, as well as the communication of control inputs 106, 107 and 109 through GUI 22 to the various modules on FPGA 17. However, it is contemplated that other interfaces or communication systems may be used.

[0053] As shown in FIG. 1 , FPGA 17 generally includes a number of modules and data buffers. With respect to processing of data for visualization by a user, FPGA 17 generally includes data aggregator 26, data selector or multiplexer 27, decimation module 28a, triggering module 29 and data buffer 30. With respect to processing of data for data logging, FPGA 17 generally includes data aggregator 26, decimation module 28b, triggering module 31 , SD card modulation module 32, SD card write interface 46, SD card read interface 47, and data buffer 33,

[0054] Similar to data creation element 23 of processor 16, data creation element 35 of FPGA 17 allows for digital data signals to be input into data aggregator 26 from external input source 36 or an internal program 37 running on FPGA 17. For example, with respect to data creation through program 37, FPGA 17 may run a resolver demodulation program which inputs two input signals, sine and cosine, and serves to perform mathematical operations to determine an output signal representing rotary position. This signal can be logged and/or visualized and presented up to processor 16 to aid in the processing of the program as well. With respect to external inputs, such inputs may, for example, include analog inputs from various sensors, digital inputs from communication ports such as RS232 port 55 or RS485 port 54 and discrete digital inputs through digital connectors 53.

[0055] As shown, FPGA 17 may also communicate with external controllable hardware 38 through digital to analog outputs 64 or the discrete digital outputs 53. For example, controllable hardware 38 may be a motor and/or a hydraulic actuator wherein the digital to analog outputs serve to move a servo valve which in effect moves a hydraulic actuator. Digital outputs can be used for solenoid control and for gate control for the electric motor. Thus, FPGA 17 may output commands to controllable hardware 38 and may in turn receive signals from sensors in or on controllable hardware 38 through external data inputs 36.

[0056] As shown in FIGS. 2 and 3, data aggregator 26 generally takes the serial data streams from FPGA 17 and processor 16 and places the data into register map 39 where it is combined. As shown in FIG. 2, processor 16 includes clock 40, which runs in this embodiment at about 1 GHz or more. Clock 40 controls the execution rate of processor 16. Although processor 16 runs at IGHz, signals from processor 16 will typically update at rates of about lOO Hz or less, albeit synced to I GHz clock 40. FPGA 17 includes clock 41 , which receives input from processor clock 40 and derives FPGA clock 41 from such signal via a phase locked loop. Data interface link 42 between FPGA 17 and processor 16 is synced with FPGA clock 41. The key to the process is that both data streams are synchronized with FPGA clock 41. Thus, clock 41 is originated at processor clock 40 and distributed to FPGA 17, data aggregator 26 and the associated FPGA modules. In this embodiment, data 101 from FPGA 17 and data 100 from processor 16 is oversampled, which results in synchronization to a common data rate regardless of the source. In this embodiment, the processor data 100 update rate may be 10kHz and the FPGA data 101 update rate may be 1 MHz. Data aggregator 26 oversamples both signals 100 and 101 to provide a synchronized signal at a common rate of 100MHz. Thus, as shown in FIG. 3, processor data 100 and FPGA data 101 is sampled 102 at the same rate. Such data is then logged 103 into register map 39. Register 39 thereby includes aggregated data that can be viewed 104a in real time and aggregated data that can be stored 104b in a memory medium, such as SD card 34, as described herein.

[0057] In this embodiment, data selector 27 is a multiplexer that allows for the user, through GUI 22, to select a subset of data signals to process. In this embodiment, data selector 27 is able to reduce up to 300 data signals to a subset of 16 signals. Thus, data selector 27 receives from processor 16 and GUI 22 a command 106 with respect to which signals to select and operates to select those signals for further processing. In this embodiment, data selector 27 can output up to 16 channels of data 105 from aggregated data 104 in data register 39.

[0058] As shown in FIGS. 4 and 5, decimation module 28 modifies the viewing rate or the capture rate of the aggregated data 104 and selected signals 105 from the FPGA and the processor to any time base that is desired by the user. The desired time base is input 107 through GUI 22 by the user and conveyed through processor 16 to decimation module 28. Decimation is in FPGA 17, which frees up processor 16 and allows the user to view the overall data at a high rate. This function is performed all in real time. Thus, as shown, data 104 in register map 39 is reduced to a subset by multiplexor 27 based on input 106 from the user to provide a subset of data 105. This subset 105 is decimated by decimation module 28 to a desired rate based on the user input and control signal 107 from GUI 22 to provide a decimated output signal 108 at the desired rate.

[0059] With respect to decimation of data that will be viewed by the user and decimation of data that will be stored or logged, in this embodiment there is a slight difference in how decimation modules 28a and 28b operate. With respect to decimation modules 28a for data that will be viewed, decimation modules 28a splits the data into two groups of eight. Each group of eight will have a common decimation rate applied by processor 16, thus enabling two distinct sets of data, each set of data containing eight signals and wherein all eight signals are decimated at the same rate. Thus, each of the signals in subset 105, which in this embodiment can be up to 16, can be decimated at one of two different rates as desired by the user. These signals can then be viewed through GUI 22a in display 73 or 74 by the user.

[0060] With respect to decimation of data that is going to be stored, decimation modules 28b each have a unique decimation factor received from processor 16 such that each module can be configured independent of other signals. All of data 104 from data aggregator 26, which in this embodiment is 300 signals, can be decimated at different rates as desired by the user and then stored as desired. It should be noted that in this embodiment, data 104 from data aggregator 26 that will be stored or logged does not need to be run through data selector 27 and that all of the aggregate data 104 may be stored or logged for future reference.

[0061] Triggering modules 29 and 31 control how the user can view and log the data by specifying which signal to trigger upon. As shown in FIG. 6, based on input 109 from the user through GUI 22, triggering modules 29 and 31 determine whether decimated data 108 from decimation module 28 meets the triggering source parameters 109 from the user. If yes, the data signal is then provided to data buffer 30 or SD card module 32 as the case may be. In this regard, it should be noted that multiple user input parameters 109 may be employed by triggering module 29 or 31. The first control parameter is the data signal that the user wants to trigger on. The user may select additional triggering methodologies such as, without limitation, rising edge, falling edge, zero crossing, level threshold and other more advanced triggering methodologies. Also, with respect to triggering module 29, given two groups of displays, each containing eight signals, each set of eight signals is triggered by a single signal within subset 105 from data selector 27, such that there are a total of two triggering signals, one of each for each set of eight channels. Data 1 1 1a from triggering module 29 gets stored and sent to processor 16 from data buffer 30 for visualization in GUI 22a and data 1 1 1b from triggering module 31 gets stored to an external source such as an SD card via SD card modulation module 32 and SD card write interface 46.

[0062] As shown in FIGS. 7 and 8, the decimated data 1 1 1a from trigger module 31 is tagged 1 12 with identification information, such as header, time stamp and channel. The tagged data is then placed 1 13 within circular ping/pong buffer 43. The buffers continue to fill and, when they are about half full, a flag is sent and received by mux 44. Mux 44 inputs the multiple signals and forwards the data into a single line 1 15 to modulated data buffer 45. Such process continues in a fashion that clears the circular buffers when they become half full and syncs all the circular buffer data into data buffer 45. Thus, data is manipulated and modulated via SD card modulation module 32 and processed into modulated data buffer 45.

[0063] The modulated data buffer data is a serial data stream which is fed into SD card write interface 46. SD card write interface 46 serves to transfer the data from modulated data buffer 45 to the physical SD card 34. SD card 34 is operated in burst or high-speed mode. When data is available in modulated data buffer 45, SD card 34 is run in burst mode and when there is no data in buffer 45, the SD card 34 clock is frozen by SD card write interface 46 to allow SD card 34 to maintain its burst status without cancelling the burst operation. Once data appears again in buffer 45, SD card write interface 46 unfreezes the clock and SD card write interface 46 continues to write at the same address that it left off on in burst mode. [0064] With reference to FIGS. 1 and 9, once data is written to physical SD card 34 and the user wants to access the data, SD card read interface 47 serves to read such data from data SD card 34. SD card read interface 47 serves to pull data from SD card 34 and to transfer it to data buffer 33. Once data is in a serial format in data buffer 33, it can be fed up to processor 16 and to SD card demodulation module 19. SD card demodulation module 19 serves to take the serial data stored in buffer 33 and to convert it back into a parallel format where it existed in the SD card modulation module before being selected and multiplexed. Thus, in essence, data input into SD card modulation module 32 exists in a parallel fashion, with the modules following triggering module 31 serving to convert the data from parallel to serial and to save it on SD card 34 in a serial fashion. It can then be read back through SD card demodulation module 19, where it is demultiplexed and reappears in parallel fashion and is stored on storage medium 20 connected to processor 16. In particular, with reference to FIG. 9, SD card demodulation module 19 will read the data from data buffer 33, interpret the header of the data packets, determine which channel the data is from, and save it off to the corresponding file. This process is repeated until data buffer 33 is cleared out. Data buffer 33 is immediately refilled by SD card 34 and SD card read interface 47, and the process continues until SD card 34 is empty, data buffer 33 is empty and all data is written to a plurality of output files that are stored on storage medium 20 of processor 16. In this embodiment, storage medium 20 is operating system SD card [0] in SD card slot 60.

[0065] Once data is stored on processor SD card [0], if the user chooses to visualize the post run data, GUI 22b serves to access the stored data from SD card [0] and load it into processor memory 21 , from which it can be viewed in GUI display 22b, enabling the user to zoom in, zoom out and to view the selected data sets stored on storage medium 20.

[0066] FIG. 1 1 is a screen shot of a sample real-time GUI input display 22a. As shown, GUI 22a includes panel 80 on the left side through which the user can select data input sources to be visualized in the display, either internally or externally generated as described above, a data output visualization canvas or screen 84, and a input menu bar 85 above display screen 84. Input panel 80 and bar 85 are the means for receiving the user inputs as described above.

[0067] In this embodiment, an analog input voltage 1 and an analog output voltage 1 are being displayed correspondingly on a channel 1 and a channel 2 in display 84, indicated at 81 and 82 respectively. With reference to FIG. 12, once the user has selected a data source from panel 80 to be displayed, the user can select, for example, a triggering "Channel" 83 from drop-down menu 86 from input bar 85 that serves to trigger all eight signals in the drop down menu. As shown, drop down menu 86 includes not just channels 1-8, which can be selected, but also includes the "Type" of the trigger, such as rising edge, falling edge, level, and zero crossing. The triggering function can also be disabled by a selection in drop down menu 86. If the triggering is not enabled, buffer 30 fills and, when filled, are simply displayed on screen 84 without any triggering functionality or flow control. If the triggering functionality is enabled, the buffer does not release the data and the data is not viewed until the triggering type has been fulfilled in the selected channel. As a result, the display will be frozen until the triggering criteria have been met. Thus, drop-down menu 86 allows for the user to input the triggering parameters 109 for triggering module 29.

[0068] As shown in FIGS. 1 1 and 12, input bar 85 also includes drop-down menu 87, which provides the user input 107a for decimation module 28a. The user may select from drop-down menu 87 the decimation rate as described above.

[0069] FIG. 13 is a screen shot of the display of stored data on post-run GUI display 22b. As shown, the data set in its entirety 90 is shown on the bottom. This is all the data from SD card 34, demodulated by module 19 and residing in storage medium 20. A region of interest can be selected by moving vertical selectors 91a and 91b to the desired portion of data set 90. Selectors 91a and 91 b serve as a zoom-in feature in which the region of interest selected is viewed in a zoomed-in manner on upper screen 92, in this embodiment as two traces 92 and 93. In this embodiment, these two traces correspond to the analog input voltage 1 and analog output voltage 1 selected by the user from input panel 80 shown in FIGS. 1 1 and 12. In this way, the entire content of SD card 34 can be visualized by panning and zooming in on selected regions of interest of the SD card data set.

[0070] While the presently preferred form of the improved data visualization and logging system has been shown and described, and several modifications thereof discussed, persons skilled in this art will readily appreciate that various additional changes and modifications may be made without departing from the scope of the invention, as defined and differentiated by the following claims.