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Title:
DDFS FOR A MIXER OF A DOWNCONVERTER
Document Type and Number:
WIPO Patent Application WO/2021/063478
Kind Code:
A1
Abstract:
The invention relates to a DDFS (100) for generating a LO signal for a down converter (300). The DDFS (100) includes an l-path and a Q-path, and obtains a register output value, and generates a phase slope signal by adding a FCW to the register output value. Further, the phase slope signal is converted to a LO signal and a calibration code value (IIP2CAL_I, IIP2CAL_Q) is added to the LO signal. Finally, a phase shifted LO signal including the calibration code value (IIP2CAL_I, IIP2CAL_Q) is generated by phase shifting the LO signal including the calibration code value (IIP2CAL_I, IIP2CAL_Q). Thereby, all desired LO frequencies can be generated from a single clock frequency and the LO signal waveform can be freely chosen. Moreover, no additional components such as decoupling capacitors and resistors are needed on the analog side in the mixer of the down converter. Furthermore, the invention also relates to a mixer, a down converter and a corresponding method.

Inventors:
RIEKKI, Jonne (Kista, SE)
Application Number:
EP2019/076448
Publication Date:
April 08, 2021
Filing Date:
September 30, 2019
Export Citation:
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Assignee:
HUAWEI TECHNOLOGIES CO., LTD. (Shenzhen, Guangdong 9, CN)
RIEKKI, Jonne (Kista, SE)
International Classes:
G06F1/02; G06F1/03; H03D3/00
Attorney, Agent or Firm:
KREUZ, Georg (Riesstr. 25, Munich, DE)
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Claims:
CLAIMS

1 . A digital frequency synthesis circuit (100) for generating a local oscillator, LO, signal for a downconverter (300), wherein the digital frequency synthesis circuit (100) includes an l-path and a Q-path, and comprises a phase accumulator block (110) configured to obtain a register output value, generate a phase slope signal by adding a frequency control word, FCW, to the register output value; a converter block (120) configured to convert the phase slope signal to a LO signal; an adder block (130) configured to add a calibration code value (IIP2CAL_I, IIP2CAL_Q) to the LO signal; and a differential block (140) configured to generate a phase shifted LO signal including the calibration code value (IIP2CALJ, IIP2CAL_Q) by phase shifting the LO signal including the calibration code value (IIP2CALJ, IIP2CAL_Q).

2. The digital frequency synthesis circuit (100) according to claim 1 , wherein the converter block (120) further is configured to reduce the amplitude of the LO signal from digital full-scale.

3. The digital frequency synthesis circuit (100) according to claim 1 or 2, wherein the converter block (120) further is configured to convert the phase slope signal to the LO signal using a square wave signal or a sine wave signal.

4. The digital frequency synthesis circuit (100) according to any one of the preceding claims, wherein the adder block (130) further is configured to add a calibration code value to the LO signal so that a maximum value of the LO signal including the calibration code value is less than digital full-scale.

5. The digital frequency synthesis circuit (100) according to any one of the preceding claims, wherein the adder block (130) further is configured to add a calibration code value to the LO signal so that a minimum value of the LO signal including the calibration code value is greater than zero.

6. The digital frequency synthesis circuit (100) according to any one of the preceding claims, wherein the calibration code value is a constant value.

7. The digital frequency synthesis circuit (100) according to claim 6, wherein the constant value is predefined and tuned for a mixer (200) of the downconverter (300).

8. The digital frequency synthesis circuit (100) according to claim 7, wherein the calibration code value is tuned for removing second order nonlinearities of the mixer (200).

9. The digital frequency synthesis circuit (100) according to claim 7 or 8, wherein the differential block (108) further is configured to provide the phase shifted LO signal including the calibration code value (IIP2CAL_I, IIP2CAL_Q) to the mixer (200).

10. A mixer (200) for a downconverter (300), wherein the mixer (200) includes an l-path and a Q-path, and comprises a first input (210) configured to receive a radio frequency signal (RFJ, RF_q) for downconversion, provide the radio frequency signal (RFJ, RF_q) to a plurality of switches (M1[0] - M4[0]); a second input (220) configured to receive a phase shifted LO signal including a calibration code value (LOIP, LOIN, LOOP, LOQN) from a digital frequency synthesis circuit (100) according to any one of claims 1 to 9, provide the phase shifted LO signal including the calibration code value (LOIP, LOIN, LOOP, LOQN) to the plurality of switches (M1 [0] - M4[0]); and an output (230) configured to output a baseband signal comprising the radio frequency signal (RFJ, RF_q) multiplied with the phase shifted LO signal including the calibration code value (LOIP, LOIN, LOOP, LOQN).

11. The mixer (200) according to claim 10, further lacking decoupling capacitors and bias resistors.

12. A downconverter (300) for downconverting a radio frequency signal to a baseband signal, the downconverter (300) comprising a digital frequency synthesis circuit (100) according to any one of claims 1 to 9, and a mixer (200) according to claim 10 or 11 .

13. A method (400) for generating a LO signal for a digital frequency synthesis circuit (100), the method (400) comprising obtaining (402) a register output value; generating (404) a phase slope signal by adding a FCW to the register output value; converting (406) the phase slope signal to a LO signal; adding (408) a calibration code value (IIP2CAL_I, IIP2CAL_Q) to the LO signal; and generating (410) a phase shifted LO signal including the calibration code value (NP2CALJ, IIP2CAL_Q) by phase shifting the LO signal including the calibration code value (IIP2CALJ, IIP2CAL_Q).

Description:
DDFS FOR A MIXER OF A DOWNCONVERTER

Technical Field

The invention relates to a DDFS for a mixer of a downconverter. Furthermore, the invention also relates to a mixer, a downconverter and a corresponding method.

Background

In wireless frequency division duplex (FDD) systems the received and transmitted radio frequency (RF) signals are located at different radio frequencies. The received RF signal is downconverted around DC frequency, i.e. zero frequency, with a local oscillator (LO) signal into a baseband signal at the receiver. At the downconverter output the downconverted transmitted signal is at a duplex distance, i.e. the distance between the received signal and transmitted signal, while the downconverter im2 product i.e. the second order nonlinearity, is centered around zero frequency. The second order nonlinearity is mostly due to mismatch between switches in the mixer of analogue and digital downconverters. The second order nonlinearity limits the signal-to-noise and distortion ratio (SNDR) of the received signal.

In conventional downconverters the second-order input intercept point (IIP2) calibration is performed by tuning the DC bias voltage of the LO signals independently for each of the switches of the mixer. By tuning the DC level of the LO signals, the mismatch between the switches of the mixer can be compensated. In order to tune the DC level of the LO signals, DC decoupling between mixer gate terminals and LO signals is required.

In a conventional analog mixer of a downconverter the gate terminals of the switches are decoupled from the LO signals with the use of capacitors and the DC bias voltages are connected to the gate terminals of the switches via large resistors. The DC bias voltages can be used for compensating the mismatch of the switches of the mixer. For example, if the threshold voltage is 20mV higher on a switch a first DC bias voltage can be tuned 20mV higher than a second DC bias voltage to compensate the threshold voltage mismatch. The threshold voltage is the voltage between the gate and the source terminal of the switch. Typically, the DC voltage of the source terminal (and drain terminal) is set by the analog baseband filter at the output of the mixer which is typically half the supply voltage, i.e. VDD/2, for all mixer outputs.

Summary

An objective of embodiments of the invention is to provide a solution which mitigates or solves the drawbacks and problems of conventional solutions. The above and further objectives are solved by the subject matter of the independent claims. Further advantageous embodiments of the invention can be found in the dependent claims.

According to a first aspect of the invention, the above mentioned and other objectives are achieved with a digital frequency synthesis circuit for generating a local oscillator, LO, signal for a downconverter, wherein the digital frequency synthesis circuit includes an l-path and a Q-path, and comprises a phase accumulator block configured to obtain a register output value, generate a phase slope signal by adding a frequency control word, FCW, to the register output value; a converter block configured to convert the phase slope signal to a LO signal; an adder block configured to add a calibration code value to the LO signal; and a differential block configured to generate a phase shifted LO signal including the calibration code value by phase shifting the LO signal including the calibration code value.

An advantage of the digital frequency synthesis circuit according to the first aspect is that all desired LO frequencies can be generated from a single clock frequency (CLK). Also, the LO signal waveform can be freely chosen. Moreover, the calibration can be done on the digital side. Hence, no additional components such as decoupling capacitors and resistors are needed on the analog side in the mixer of the downconverter. This implies more compact layout (smaller chip size) in the mixer and cost saving when producing the mixer. Further, better matching between cells of the mixer is achieved which results in improved SNDR and lower current consumption due to lower parasitic effects in the mixer.

In an implementation form of a digital frequency synthesis circuit according to the first aspect, the converter block further is configured to reduce the amplitude of the LO signal from digital full-scale.

An advantage with this implementation form is that the LO signal waveform is maintained after adding the calibration code. If the LO signal waveform clips the harmonic content of the LO is changed thus degrading the harmonic rejection of the mixer. In an implementation form of a digital frequency synthesis circuit according to the first aspect, the converter block further is configured to convert the phase slope signal to the LO signal using a square wave signal or a sine wave signal.

An advantage with this implementation form is that by using a square wave signal higher conversion gain is possible which means that the signal at the mixer output is higher. By using a sine wave signal the LO signal does not mix from its harmonics since the sinewave does not have harmonics.

In an implementation form of a digital frequency synthesis circuit according to the first aspect, the adder block further is configured to add a calibration code value to the LO signal so that a maximum value of the LO signal including the calibration code value is less than digital full-scale.

An advantage with this implementation form is that the LO signal waveform is maintained after adding the calibration code.

In an implementation form of a digital frequency synthesis circuit according to the first aspect, the adder block further is configured to add a calibration code value to the LO signal so that a minimum value of the LO signal including the calibration code value is greater than zero.

An advantage with this implementation form is that the LO signal waveform is maintained after adding the calibration code.

In an implementation form of a digital frequency synthesis circuit according to the first aspect, the calibration code value is a constant value.

An advantage with this implementation form is that the calibration can be done at factory and correct calibration values for the mixer application can be selected from predefined tables. This means that the mixer is already calibrated at delivery since no calibration is needed at start-up of the mixer/downconverter.

In an implementation form of a digital frequency synthesis circuit according to the first aspect, the constant value is predefined and tuned for a mixer of the downconverter. An advantage with this implementation form is that no calibration is needed at start-up of the mixer/down converter.

In an implementation form of a digital frequency synthesis circuit according to the first aspect, the calibration code value is tuned for removing second order nonlinearities of the mixer.

An advantage with this implementation form is that the second order nonlinearities of the mixer are removed or mitigated.

In an implementation form of a digital frequency synthesis circuit according to the first aspect, the differential block further is configured to provide the phase shifted LO signal including the calibration code value to the mixer.

According to a second aspect of the invention, the above mentioned and other objectives are achieved with a mixer for a downconverter, wherein the mixer includes an l-path and a Q-path, and comprises a first input configured to receive a radio frequency signal for downconversion, provide the radio frequency signal to a plurality of switches; a second input configured to receive a phase shifted LO signal including a calibration code value from a digital frequency synthesis circuit according to any one implementation form of a digital frequency synthesis circuit according to the first aspect, provide the phase shifted LO signal including the calibration code value to the plurality of switches; and an output configured to output a baseband signal comprising the radio frequency signal multiplied with the phase shifted LO signal including the calibration code value.

An advantage of the mixer according to the second aspect is that the calibration can be done on the digital side.

In an implementation form of a mixer according to the second aspect, the mixer further lacking decoupling capacitors and bias resistors. This implies more compact layout (smaller chip size) in the mixer and cost saving when producing the mixer. Further, better matching between cells of the mixer is achieved which results in improved SNDR and lower current consumption due to lower parasitic effects in the mixer. According to a third aspect of the invention, the above mentioned and other objectives are achieved with a downconverter for downconverting a radio frequency signal to a baseband signal, the downconverter comprising a digital frequency synthesis circuit according to any implementation form of a digital frequency synthesis circuit according to the first aspect, and a mixer according to any implementation form of a mixer according to the second aspect.

According to a fourth aspect of the invention, the above mentioned and other objectives are achieved with a method for generating a LO signal for a digital frequency synthesis circuit, the method comprising obtaining a register output value; generating a phase slope signal by adding a FCW to the register output value; converting the phase slope signal to a LO signal; adding a calibration code value to the LO signal; and generating a phase shifted LO signal including the calibration code value by phase shifting the LO signal including the calibration code value.

The method according to the fourth aspect can be extended into implementation forms corresponding to the implementation forms of the digital frequency synthesis circuit according to the first aspect. Hence, an implementation form of the method comprises the feature(s) of the corresponding implementation form of the digital frequency synthesis circuit.

The advantages of the methods according to the fourth aspect are the same as those for the corresponding implementation forms of the digital frequency synthesis circuit according to the first aspect.

Further applications and advantages of the embodiments of the invention will be apparent from the following detailed description.

Brief Description of the Drawings

The appended drawings are intended to clarify and explain different embodiments of the invention, in which:

- Fig. 1 shows a DDFS according to an embodiment of the invention;

- Fig. 2 shows a flow cart of a method according to an embodiment of the invention;

- Fig. 3 shows a DDFS and a mixer according to an embodiment of the invention;

- Fig. 4a-4c shows signalling diagrams illustrating embodiments of the invention; - Fig. 5a and 5b illustrates back off from full scale;

- Fig. 6 shows a downconverter according to an embodiment of the invention;

- Fig. 7 illustrates calibration test signals and second order intermodulation at the receiver output;

- Fig. 8 and 9 show performance results; and

- Fig. 10 illustrates a wireless communication system.

Detailed Description

As aforementioned the IIP2 calibration of conventional digital downconverters is performed by changing the DC bias voltages of the calibration voltages for the l-path and Q-path, respectively. However, according to the invention the IIP2 calibration is performed in the digital side contrary to conventional solutions. By changing the DC bias voltage of the digital LO signal, any mismatch of the switches of the mixer can be compensated hence moving the IIP2 calibration functionality from the analog side to the digital side. Furthermore, according to aspects of the invention instead of generating full-scale LO signal in the Direct Digital Frequency Synthesis (DDFS), the LO signal amplitude is lowered, i.e. backed-off from digital full-scale, so as to leaving room for DC level adjustments. The offset value, i.e. the IIP2 calibration value, can then be added in the DDFS to the digital LO signal to compensate the switching mismatch in the mixer of the downconverter.

Fig. 1 shows a block diagram of a DDFS 100 according to an embodiment of the invention. The DDFS 100 includes both an l-path and a Q-path, and further comprises a phase accumulator block 110 configured to obtain a register output value and generate a phase slope signal by adding a frequency control word (FCW) to the register output value. The DDFS further comprises a converter block 120 configured to convert the phase slope signal to a LO signal and an adder block 130 configured to add a calibration code value (CCV) IIP2CALJ, IIP2CAL_Q to the LO signal. The DDFS 100 further comprises a differential block 140 configured to generate a phase shifted LO signal including the calibration code value IIP2CALJ, IIP2CAL_Q by phase shifting the LO signal including the calibration code value IIP2CALJ, IIP2CAL_Q.

Fig. 2 shows a flow chart of a corresponding method 400 for generating a LO signal for a digital frequency synthesis circuit 100, such as the one shown in Fig. 1. The method 400 comprises obtaining 402 a register output value and generating 404 a phase slope signal by adding a FCW to the register output value. The method 400 further comprises converting 406 the phase slope signal to a LO signal and adding 408 a calibration code value IIP2CALJ, IIP2CAL_Q to the LO signal. The method 400 further comprises generating 410 a phase shifted LO signal including the calibration code value IIP2CAL_I, IIP2CAL_Q by phase shifting the LO signal including the calibration code value IIP2CAL_I, IIP2CAL_Q.

Fig. 3 shows a digital downconverter300 comprising a DDFS 100 according to an embodiment of the invention. The general function of the downconverter 300 and its mixer 200 is to convert a high frequency RF input signal, e.g. around 2 GHz to zero frequency, to obtain a baseband signal representation of the RF signal. The mixer 200 therefore multiplies the 2 GHz input signal with the 2 GHz LO signal which results in a zero-frequency output signal.

The DDFS 100 comprises as aforementioned a phase accumulator block 110, a phase-to- amplitude converter block 120, an adder block 130, and a single-ended-to-differential block 140 which are described more in detail in the following disclosure. The corresponding signal waveforms at the DDFS 100 for different processing steps are illustrated in Figs. 4a-4c.

Furthermore, the DDFS 100 in Fig. 3 is connected to a mixer 200 of a downconverter 300. Hence, the differential block 140 is configured to provide the phase shifted LO signal including the calibration code value IIP2CALJ, IIP2CAL_Q to the mixer 200. In embodiments, the mixer 200 includes an l-path and a Q-path. The mixer 200 also comprises a first input(s) 210 configured to receive a radio frequency signal RFJ, RF_q for downconversion, and to provide the RF signal RFJ, RF_q, respectively, to a plurality of switches M1[0] - M4[0]. The mixer 200 further comprises a second input(s) 220 configured to receive a phase shifted LO signal including a calibration code value, i.e. LOIP, LOIN, LOOP, LOQN from the DDFS 100 as previously mentioned. The second input 220 is further configured to provide the phase shifted LO signal including the calibration code value LOIP, LOIN, LOOP, LOQN to the plurality of switches M1 [0] - M4[0]. The mixer 200 further comprises output(s) 230 configured to output a baseband signal comprising the radio frequency signal RFJ, RF_q multiplied with the phase shifted LO signal including the calibration code value LOIP, LOIN, LOOP, LOQN.

In the digital downconverter architecture in Fig. 3 the mixer switches are split into many cells 250n. First mixer cell includes switches M1 [0] - M4[0], second mixer cell includes switches M1 [1] - M4[1], etc. On total the mixer 200 has n number of cells. The number n should be chosen high enough to meet SNDR requirements and may also depend on weighing method selected, e.g. binary weighing or equal weighing. The cells can be binary or some other way weighted. Each cell is driven with its own digital LO signal, i.e. LOIP[n:0], LOIN[n:0], etc. In the digital mixer there is only switch transistors that can be arranged closely together to achieve best possible matching. Hence no capacitors or resistances as in conventional mixers are needed in a digital mixer 200. To provide deep understanding of embodiments of the invention, the different blocks of the DDFS 100 will be described more in detail in the following disclosure.

Phase accumulator block

The DDFS 100 comprises a phase accumulator block 110 which is driven by FCWs and constant clock (CLK) signals. The phase accumulator block 110 is configured to add a FCW to an output value of a register for each clock sample of the CLK. After reset said value is zero and then increases at the slope given by the FCW. The FCW determines the phase slope and thus the DDFS frequency which is equal to the LO frequency, i.e. “PA_out” (phase accumulator output) in Fig. 4a. PA_out is the value held at the register output plus the FCW for each clock sample.

The phase accumulator block 110 therefore comprises a register block 116, an adder block 112 and a feedback line 114 from the register block 116 output to the adder block 112 as shown in Fig. 3. The register block 116 changes a register input value to a register output value at each rise of the CLK signal, i.e. once per clock period. This value is held at the output until the CLK signal rises again. For example, if the FCW value is 2, starting from reset:

CLK cycle FCW Register output value

1 2 FCW + register output (on reset 0) = 2

2 2 FCW + register output (previous value 2) = 4

The PA_out is thereafter outputted to the phase-to-amplitude converter block 120.

The DDFS 100 comprises a phase-to-amplitude converter block 120 which is coupled to the phase accumulator block 110. The phase-to-amplitude converter block 120 converts the phase slope signal received from the phase accumulator block 110 to a LO signal, i.e. the “PAC_out” (phase to amplitude converter output) in Fig. 4b.

In embodiments the converter block 120 is configured to convert the phase slope signal to the LO signal using a square wave function or a sine wave function. This means that the LO signal or PAC_out in Fig. 4b is the square wave signal or sinewave signal waveform output for each CLK hence not a continuous signal but a sampled signal. The PAC_out is outputted to the adder block 130. In embodiments the converter block 120 is configured to reduce the amplitude of the LO signal from digital full-scale. Hence, the signal from the phase-to-amplitude block 120 is backed off from the full-scale so as to make room for calibration offset value.

Adder block

The DDFS 100 comprises an adder block 130 which is coupled to phase-to-amplitude converter block 120. The adder block 130 is configured to receive the LO signal (PAC_out) from the phase-to-amplitude converter block 120 and add a calibration code value, i.e. IIP2CALJ and IIP2CAL_Q, respectively, depending on whether the path is l-path or Q-path, to the LO signal output from the phase-to-amplitude converter block 120. The calibration code value is received by the adder block 130, e.g. from a memory of the DDFS 100.

In embodiments the calibration value is a constant value in the respect that it does not change over time. More specifically, the constant value is predefined and tuned for a mixer 200 of the downconverter 300. This implies that the calibration is performed in factory at production of the DDFS 100. Predefined tables can be provided which indicates different calibration values for different mixer applications. Hence, a suitable calibration value can be pick at production. The calibration value can be stored in a memory (not shown) of the downconverter 300 and fetched from the memory when needed.

In embodiments, the calibration code value is tuned for removing second order nonlinearities of the mixer 200.

In further embodiments, the calibration code value is different for different receivers but constant for one downconverter/receiver. The nonidealities during the manufacturing process causes mismatch in different properties, such as threshold voltage, of the mixer switches. Further, the non-symmetrical layout design by the designer can cause mismatch. However, these effects are not changed over time but stays constant for one physical instance of the mixer. Therefore, the calibration values can be constant and fixed for a single mixer 200. Moreover, the calibrated code effectively creates a mismatch to the LO port to counter the mismatch in the mixer switch itself. Therefore, the output is perfectly in balance and no second order nonlinearity is created.

In further embodiments, the adder block 130 is configured to add a calibration code value to the LO signal so that a maximum value of the LO signal including the calibration code value is less than digital full-scale. In further embodiments, the adder block 130 is also configured to add a calibration code value to the LO signal so that a minimum value of the LO signal including the calibration code value is greater than zero.

The LO signal including the calibration code must be less than the full-scale in order to maintain the LO waveform. Also, if the LO signal is higher than the maximum value and lower than the minimum value, hence clips at both ends, even the calibration functionality is lost.

Sinqle-ended-to-differential block

The DDFS 100 comprises a single-ended-to-differential block 140 coupled to the adder block 130. The single-ended-to-differential block 140 is configured to receive the LO signal including the calibration code value from the adder block 130 and add another 180-degree phase shift to the sinewave waveform output signal added with the calibration signal. The 180-degree phase shift signal is required to create differential downconverter output signals. The differential outputs are required to suppress the second order nonlinearity. With the LO signal including the optimal calibration code and non-ideal mixer the differential outputs (IP, IM) are in balance and therefore have no differential second order nonlinearity component. Without the differential output there is no way of suppressing the second order nonlinearity.

The output of the differential block 140 are the digital LO signals LOIP[n:0], LOIN[n:0], LOQP[n:0], LOQN[n:0], used for IIP2 calibration of the switches in the digital mixer 200 of the downconverter 300. Hence, the output of the single-ended-to-differential block 140 is 180- degree phase shift of the PAC_out + constant calibration code value signal (shown in Fig. 4c) which is equal to the digital LO signal used for IIP2 calibration of the switches in the digital mixer of the downconverter.

It noted that for simplicity only the processing of the l-path according to the invention is illustrated in Figs. 4a-4c and 5a-5b. However, the processing of the Q-path is the same as for the l-path except for a 90-degree phase shift on the PAC output. Typically, the calibration of the l-path and the Q-path is performed separately. Also, said calibration is usually not performed in parallel but in series. In zero inter frequency (IF) receivers the baseband signal can be downconverted around DC with the I (in-phase) and the Q (quadrature) signals. By using IQ signals the analog baseband (ABB) filter can be simple lowpass filter. The I- and Q- paths are added together in the digital domain (see Fig. 6) to construct the complex signal, i.e. l+jQ. Further, it is noted that each n signal of the LOIP [n: 0] signals in Fig. 3 is a digital zero “0” or a digital one “1”. When the sinewave signal is at maximum all n signals have value “1”, and all n signals have values “0” when the sinewave is at minimum. At other time instances some of the n signals have the value “0” and others have the value “1 ” to effectively create the sinewave curve for mixing of RF signals with LO signals at the mixer 200.

Fig. 5a shows a digital 10-bit full-scale waveform calibration signal LOIP[n:0] without DC offset. The DC level in Fig. 5a is shown with dashed line which is exactly at the center value. It can be seen that there is no room for DC adjustment without clipping the signal. Fig. 5b shows the backed-off from full-scale waveform calibration signal with DC offset added as previously described. The DC level is again shown with dashed line which now is above the center value illustrated with the arrow. In the DDFS 100 there is a single-ended to differential buffer which drives the positive (M1 [n:0j) switches with a stronger LO signal. This effect can be used for compensating the mismatch of switches in the mixer 200.

Fig. 6 shows a downconverter according to an embodiment of the invention. A calibration signal is inserted into a low noise amplifier (LNA) of a radio frequency integrated circuit (RFIC). The LNA is typically the first block of the RFIC. The LNA amplifies the signal and adds as little noise as possible. The next block is the downconverter 300 including the LO signal which converts the amplified RF signal to baseband around zero frequency. The ABB filters the unwanted blocker signals including the transmitter (TX) signal and amplifies the signal to a correct level for the analog to digital (A/D) converter (ADC) which converts the filtered signal to the digital domain (DIGITAL) and applies further filtering and combines the I- and Q-paths to a complex IQ signal (l+jQ).

Moreover, it is recognized that IIP2 calibration needs test tones to mixer input that can generated with external generators or with own TX through loopback switch in the Front-end Module (FEM). After the test tones are added, the second order intermodulation product is minimized by optimizing the IIP2CAL calibration values. The calibration is done separately for the l-path and Q-path. The test tone frequencies are at duplex distance of LO frequency and 2xdf apart (1 MHz for example) which is illustrated in the left signal diagram in Fig. 7. Power is the maximum transmit power at the LNA input. The second order intermodulation is at 2 * df which is illustrated in the right signal diagram in Fig. 7.

Fig. 8 and 9 shows simulation results of the proposed IIP2 calibration scheme. Fig. 8 shows the simulation results for IIP2 with different DC offset values added. The x-axis shows different IIP2 calibration values (IIP2CAL), and the y-axis shows the IIP2 value in dBm in Fig. 8. This means that the higher value the better. In Fig. 8 the calibration value, i.e. IIP2CAL constant value, is swept from -100m to 110m. It can be seen from Fig. 8 that by changing the value of the calibration signal IIP2CAL by 10m the IIP2 is improved by 10 dBm.

Fig. 9 shows simulation results for second and third order intermodulation and the gain. In Fig. 9 there is second and third order intermodulation products as well as gain as a function of the LO offset, i.e. the calibration value (IIP2CAL constant). The x-axis shows the LO offset values (IIP2CAL), i.e. calibration values, and the y-axis shows the intermodulation hence the lower value the better. As seen from Fig. 9 the second order intermodulation product is minimized and the third order intermodulation is kept quite constant. Furthermore, it is noted from Fig. 9 that the gain is not affected by IIP2 calibration.

The downconverter 300 and hence also the DDFS 100 and the mixer 200 according to embodiments of the invention can in non-limiting examples be implemented/comprised in a client device 510 and/or a network access node 520 of a wireless communication system 500, such as 3GPP new radio (NR). Fig. 10 illustrates a wireless communication system 500 according to an embodiment of the invention. The wireless communication system 500 comprises a client device 510 and a network access node 520 configured to operate in the wireless communication system 500. For simplicity, the wireless communication system 500 shown in Fig. 10 only comprises one client device 510 and one network access node 520. However, the wireless communication system 500 may comprise any number of client devices 510 and any number of network access nodes 520 without deviating from the scope of the invention. The client device 510 and a network access node 520 can perform uplink and/or downlink communication.

The client device 510, may be denoted as a user device, a User Equipment (UE), a mobile station, an internet of things (loT) device, a sensor device, a wireless terminal and/or a mobile terminal, is enabled to communicate wirelessly in a wireless communication system, sometimes also referred to as a cellular radio system. The UEs may further be referred to as mobile telephones, cellular telephones, computer tablets or laptops with wireless capability. The UEs in this context may be, for example, portable, pocket-storable, hand-held, computer- comprised, or vehicle-mounted mobile devices, enabled to communicate voice and/or data, via the radio access network, with another entity, such as another receiver ora server. The UE can be a Station (STA), which is any device that contains an IEEE 802.11 -conformant Media Access Control (MAC) and Physical Layer (PHY) interface to the Wireless Medium (WM). The UE may also be configured for communication in 3GPP related LTE and LTE-Advanced, in WiMAX and its evolution, and in fifth generation wireless technologies, such as New Radio.

The network access node 520 may also be denoted as a radio network access node, an access network access node, an access point, or a base station, e.g. a Radio Base Station (RBS), which in some networks may be referred to as transmitter, “gNB”, “gNodeB”, “eNB”, “eNodeB”, “NodeB” or “B node”, depending on the technology and terminology used. The radio network access nodes may be of different classes such as e.g. macro eNodeB, home eNodeB or pico base station, based on transmission power and thereby also cell size. The radio network access node can be a Station (STA), which is any device that contains an IEEE 802.11- conformant Media Access Control (MAC) and Physical Layer (PHY) interface to the Wireless Medium (WM). The radio network access node may also be a base station corresponding to the fifth generation (5G) wireless systems. Finally, it should be understood that the invention is not limited to the embodiments described above, but also relates to and incorporates all embodiments within the scope of the appended independent claims.