BREWER TONY M (US)
US20120072628A1 | 2012-03-22 | |||
US20140115209A1 | 2014-04-24 | |||
US20190303307A1 | 2019-10-03 | |||
US20180293192A1 | 2018-10-11 | |||
KR20100087328A | 2010-08-04 |
CLAIMS What is claimed is: 1. An apparatus comprising: a first chiplet couplable to multiple other chiplets using a serial peripheral interface (SPI) configured for an SPI protocol, the first chiplet configured as an SPI primary device, wherein the first chiplet is configured to: send a first message across the SPI interface, the first message comprising a command field configured to access a first selected chiplet of the multiple other chiplets, the first selected chiplet configured as an SPI secondary device: and receive a response message from the first selected chiplet in response to the first message, wherein the response message comprises a secondary device status field indicating a readiness of the first selected chiplet to provide a data payload to the first chiplet. 2. The apparatus of claim 1, wherein the secondary device status field includes one or more bits set to indicate a deferred return status: and wherein the first chiplet is further configured to, in response to receiving a response message with one or more bits set to indicate a deferred return status, send a deferred read request to the first selected chiplet. 3. The apparatus of claim 2, further comprising the first selected chiplet wherein in response to the deferred read request, the first selected chiplet is configured to send an updated response message to the first chiplet, and the updated response message comprises the secondary device status field including one or more bits to indicate a subsequent readiness of the first selected chiplet to provide the data payload to the first chiplet. 4. The apparatus of claim 1, wherein the command field of the first message includes one or more bits set to indicate whether the first chiplet previously received a deferral from the first selected chiplet. 5. The apparatus of claim 1, wherein the first message further comprises a register address field of the first message, the register address field including one or more bits set to indicate an address of a memory register on the first selected chiplet. 6. The apparatus of claim 5, wherein the first message comprises a data field, and data in the data field is configured to be stored in a location corresponding to the register address field of the first message. 7. The apparatus of claim 6, wherein the first message comprises a chiplet identification field indicating the first selected chiplet of the multiple other chiplets: wherein in the first message, the data field immediately follows the chiplet identification field, and the chiplet identification field immediately follows the command field. 8. The apparatus of claim 1, wherein the response message comprises the payload, and the payload comprises data from a memory register on the first selected chiplet. 9. The apparatus of claim 1, wherein the command field includes one or more bits set to enable the first selected chiplet to access specified memory registers on the first selected chiplet. 10. A system comprising: a first chiplet coupled to multiple other chiplets, the first chiplet configured to generate a clock signal; and a first selected chiplet of the multiple other chiplets, the first selected chiplet configured to interface with the first chiplet using a serial peripheral interface (SPI) protocol; wherein the first chiplet is configured to perform operations comprising: enable a controller on the first selected chiplet; send the clock signal to the first selected chiplet; send a first message to the first selected chiplet using the SPI interface, wherein the first message comprises a command field and a register address field, the command field including one or more bits to enable the controller to access memory registers of the first selected chiplet, and the register address field including one or more bits to address a particular memory register on the first selected chiplet: and wherein, in response to receiving the first message, the first selected chiplet is configured to: send a response message to the first chiplet using the SPI interface, wherein the response message comprises a secondary device status field including one or more bits to indicate a readiness of the first selected chiplet to provide a payload to the first chiplet. 11 . The system of claim 10, wherein the first message further comprises a data field. 12. The system of claim 10, wherein the response message comprises the payload when the secondary device status field indicates the first selected chiplet is ready to provide the payload. 13. The system of claim 10, wherein the response message comprises one or more bits set to instruct the first chiplet to queue a later read request for the first selected chiplet. 14. The system of claim 10, wherein the first message comprises a chiplet identification field including one or more bits to address the first selected chiplet; and wherein in the first message, the chiplet identification field immediately follows the command field, and the register address field immediately follows the chiplet identification field. 15. The system of claim 10, wherein the response message leads with the secondary device status field before one or more other data bits. 16. A method comprising: at a first chiplet configured to be communicatively coupled to a second chiplet using a serial peripheral interface (SPI) interface bus, sending a first message to the second chiplet, wherein the first message comprises a command field including one or more bits configured to enable access to the second chiplet; and receiving a response message from the second chiplet in response to the first message from the first chiplet, the response message comprising a secondary device status field, wherein the secondary device status field includes one or more bits selected to indicate a readiness of the second chiplet to provide a data payload to the first chiplet. 17. The method of claim 16, further comprising preparing the response message at the second chiplet, wherein the response message indicates a deferral in the secondary device status field, and the method further including: using the first chiplet, sending a subsequent second message to the second chiplet to determine whether the data payload is available. 18. The method of claim 17, further including, in response to the subsequent second message, sending an updated response message from the second chiplet to the first chiplet, the updated response message comprising one or more bits in the secondary device status field to indicate a subsequent readiness of the second chiplet to provide the data payload to the first chiplet. 19. The method of claim 16, wherein the command field indicates whether the first message is an original read request or a deferred read request for information in a specified register of the second chiplet. 20. The method of claim 16, wherein the first chiplet is communicatively coupled to a third chiplet using the SPI interface bus, and the method further comprising: at the first chiplet, sending a second message to the third chiplet, wherein the second message comprises a command field including one or more bits configured to enable access to the third chiplet; and at the third chiplet, receiving the second message from the first chiplet and, in response, preparing a second response message that comprises a secondary device status field, wherein the secondary device status field includes one or more bits selected to indicate a readiness of the third chiplet to provide a data payload to the first chiplet. |
Table 1: Example Message Fields in SPI Deferred-Response Communications [0079] In an example, a 2-bit Command message (e.g., C[1:0] in Table 1) can be provided from the primary device to a secondary device. The Command message can comprise a portion or field of the secondary device input signal 320 and can indicate a command or instruction from the primary device 310. In an example, the Command message can include information about whether the receiving device or secondary device is directed to perform a read operation or a write operation. In an example, the Command message can indicate whether a controller request (e.g., a read request from a primary device) is an initial request or a deferred request. [0080] In an example, a 7-bit Chiplet Identification message and parity bit (e.g., ID[6:0] and IDP in Table 1) can be provided from the primary device to a secondary device. The Chiplet Identification message can be used, for example, to address a particular chiplet in a system, such as in the chiplet system 110. The Chiplet Identification message can be optional and, in an example, is used in cases where individual SPI chip selects are unavailable or unused. [0081] In an example, a 32-bit Address and parity bit (e.g., A[31:0] and AP in Table 1) can follow the Chiplet Identification message. The Address message can be used, for example, to locate a particular register, such as in the data register 306 or elsewhere in the chiplet system 110. In an example, a 64-bit Data message and parity bit (e.g., D[63:0] and DP in Table 1) can follow the Address message. The Data message can comprise a data payload such as for storage in, or retrieval from, the secondary device. [0082] In an example, a Secondary Device status message and parity bit (e.g., S[2:0] and SP in Table 1) can be provided from the secondary device to the primary device. The Secondary Device status message can, in an example, be a one, two, three, or more bit message or field. In the examples illustrated herein, the Secondary Device status message comprises a 3-bit message and a parity bit, however Secondary Device status messages can be configured to have more or fewer bits depending on an amount of information to be exchanged with the message. Table 2 describes generally various commands or information that can be encoded in a Secondary device status message. Table 2: Secondary device status Message Commands [0083] The various message fields, usages, and message components discussed herein are examples only and should not be considered limiting. For example, other additional message fields can be used, or fewer message fields can be used in SPI deferred-response communications. In an example, the various fields can be arranged in different orders or sequences to similarly provide deferred-response communications. The various sizes of the message components are provided as examples only. [0084] Using the conventions provided in Table 1 and Table 2, FIG.4 illustrates generally a first timing diagram 400 that includes using a secondary device status field in messages used in a read operation, and FIG.5 illustrates generally a second timing diagram 500 that includes using a secondary device status field in messages used in a write operation. [0085] The example of FIG. 4 shows a general timing diagram for various signals communicated using an SPI bus, such as between the primary device 310 and the SPI memory device 302. FIG.4 includes examples of the select signal 316, the clock signal 318, the secondary device input signal 320, and the secondary device output signal 314. As mentioned above, the primary device 310 can initiate communication by setting the select signal 316 low, as generally indicated by reference numeral 402. [0086] In the example of FIG.4, a first rising edge 404 of the clock signal 318 corresponds to a first bit of the 2-bit Command message. In FIG. 4, the 2-bit Command message is 0-1 and indicates to the secondary device that the message includes a first or initial read instruction. Following the Command message, the primary device 310 can send the Chiplet Identification message, such as followed by the Address message, such as to indicate a register location. The bits of the various message bit components can correspond to respective pulses in the clock signal 318. In the example of FIG. 4, a blanking period can follow the Address message. [0087] In response to the Command, Chiplet Identification, and Address messages, the secondary device can prepare and communicate a response to the primary device 310, such as using the secondary device output signal 314. In the example of FIG.4, the secondary device output signal 314 comprises a signal that leads with a secondary device status message 408. Depending on the information in the secondary device status message 408, the secondary device output signal 314 can include or comprise a payload, such as comprising an n-bit Data message. The communication can terminate when the primary device 310 sets the select signal 316 high, such as indicated in FIG. 4 by reference numeral 410. [0088] The example of FIG. 5 shows a second timing diagram 500 for various signals communicated using an SPI bus, such as between the primary device 310 and the SPI memory device 302. FIG.5 includes examples of the select signal 316, the clock signal 318, the secondary device input signal 320, and the secondary device output signal 314. As mentioned above, the primary device 310 can initiate communication by setting the select signal 316 signal low, as generally indicated by reference numeral 502. [0089] In the example of FIG.5, a first rising edge 504 of the clock signal 318 corresponds to a first bit of the 2-bit Command message. In FIG. 5, the 2-bit Command message is 1-0 and indicates to the secondary device that the message includes a write instruction. Following the Command message, the primary device 310 can send the Chiplet Identification message, such as followed by the Address message, such as to indicate a register location. Following the Address message, the primary device 310 can send the Data message or payload, such as for storage in a register indicated by the information in the Address message portion of the communication. In the example of FIG. 5, a blanking period can follow the Data message. [0090] Following the blanking period and in response to the write instruction, the secondary device can return a message to the primary device 310 using the secondary device output signal 314. In the example of FIG. 5, the returned message can include a secondary device status message 508. Using the information in the secondary device status message 508, the primary device 310 can be configured to take a particular responsive action. For example, the secondary device status message 508 can indicate to the primary device 310 that it should queue a deferred read request, such as to the same or different secondary device. [0091] FIG. 6 illustrates generally a third timing diagram 600 with a deferred return secondary device status. FIG. 6 includes examples of the select signal 316, the clock signal 318, the secondary device input signal 320, and the secondary device output signal 314. In an example, the primary device 310 can initiate communication according to the third timing diagram 600 by setting the select signal 316 low, as generally indicated by reference numeral 602. [0092] On a first rising ed ge 604 of the clock signal 318 following the transition at 602, the primary device 310 can provide a Command message. In the example of FIG. 6, the Command message is 0-1 and indicates to the secondary device that the message includes a read request or instruction. Following the Command message, the primary device 310 can send the Chiplet Identification message, such as followed by the Address message, such as to indicate a register location. [0093] In response to the Command, Chiplet Identification, and Address messages, the secondary device can prepare and communicate a response to the primary device 310, such as using the secondary device output signal 314. In the example of FIG.6, the secondary device output signal 314 comprises a signal that leads with a deferred secondary device status message 606 (e.g., Secondary device status message 0-0-1). From the information in Table 2, the Secondary device status message can be understood to be a request for a Deferred Read Response. [0094] In an example, the deferred secondary device status message 606, or Deferred Read Response status, can be provided by the secondary device when the secondary device is unable to reply or is otherwise not ready to send a proper response to the primary device 310. In other words, the secondary device can issue the deferred secondary device status message 606 to request more time to complete the instruction as-received from the primary device 310 following the onset of the communication. Following the deferred secondary device status message 606 in the third timing diagram 600, the communication can terminate. In an example, upon receiving the deferred secondary device status message 606, the primary device 310 can queue a deferred read request for later communication to the secondary device. [0095] FIG. 7 illustrates generally a fourth timing diagram 700 with a deferred read response from a secondary device. FIG. 7 includes examples of the select signal 316, the clock signal 318, the secondary device input signal 320, and the secondary device output signal 314. In an example, the primary device 310 can initiate communication according to the fourth timing diagram 700 by setting the select signal 316 low, as generally indicated by reference numeral 702. [0096] On a first rising edge 704 of the clock signal 318 following the CS transition at 702, the primary device 310 can provide a Command message. In the example of FIG.7, the Command message is 1-1 and indicates to the secondary device that the message includes a deferred read request or instruction. In other words, the deferred read request or instruction can indicate to the secondary device that the present instruction follows a previous instruction, received from the same secondary device, to defer its response. Following the Command message, the primary device 310 can send the Chiplet Identification message. [0097] In the example of FIG.7, the deferred read request omits an Address message. Since the secondary device previously issued a deferral, the secondary device can be configured to expect to receive the deferred read request. Accordingly, the secondary device can queue its response in a cache register, for example, to help expedite its reply and thereby obviate any need for the primary device 310 to repeat the Address message with each deferred read request. [0098] In response to the Command and Chiplet Identification messages, the secondary device can prepare and communicate a response to the primary device 310, such as using the secondary device output signal 314. In the example of FIG. 7, the secondary device output signal 314 includes a signal that leads with a secondary device status message 706 that is followed by a payload data message 708. The communication can terminate following transmission of the data message 708, when the primary device 310 sets the select signal 316 high, such as indicated in FIG.7 by reference numeral 710. [0099] FIG. 8 illustrates generally a fifth timing diagram 800 with a further deferred read response from a secondary device. FIG. 8 includes examples of the select signal 316, the clock signal 318, the secondary device input signal 320, and the secondary device output signal 314. In an example, the primary device 310 can initiate communication according to the fifth timing diagram 800 by setting the select signal 316 low, as generally indicated by reference numeral 802. [0100] On a first rising edge 804 of the clock signal 318 following the CS transition at 802, the primary device 310 can provide a Command message. In the example of FIG.8, the Command message is 1-1 and indicates to the secondary device that the message includes a deferred read request or instruction. In other words, the deferred read request or instruction can indicate to the secondary device that the present instruction follows a previous instruction, received from the same secondary device, to defer its response. Following the Command message, the primary device 310 can send the Chiplet Identification message. [0101] In the example of FIG.8, the deferred read request omits an Address message. Since the secondary device previously issued a deferral, the secondary device can be configured to expect to receive the deferred read request. Accordingly, the secondary device can queue its response in a cache register, for example, to help expedite its reply and thereby obviate any need for the primary device 310 to repeat the Address message with each deferred read request. [0102] In response to the Command and Chiplet Identification messages, the secondary device can prepare and communicate a response to the primary device 310, such as using the secondary device output signal 314. In the example of FIG. 8, the secondary device output signal 314 includes a signal that leads with a secondary device status message 808 that indicates a deferral. That is, the secondary device output signal 314 can include a signal that leads with a deferred secondary device status message (e.g., Secondary device status message 0-0-1), such as can indicate a request for a Deferred Read Response. In an example, the Deferred Read Response status can be provided by the secondary device when the secondary device is initially, or remains, unable to reply properly to the primary device 310. In other words, the secondary device can issue the secondary device status message 808 with a further deferral to request additional time to complete the instruction as previously received from the primary device 310. [0103] In an example, following the secondary device status message 808 in the fifth timing diagram 800, the communication can terminate. In an example, upon receiving the secondary device status message 808 indicating a further deferral, the primary device 310 can queue a deferred read request for later communication to the secondary device, or, in some examples, can give up after a specified duration or specified number of read attempts. [0104] FIG. 9 illustrates a flow diagram of an example of a first method 900 for communication using an SPI interface with deferred response messaging, in accordance with one embodiment. In the example of FIG.9, the first method 900 begins at block 902 with using an SPI interface to communicate messages between a first chiplet, or primary device, and a second chiplet, or secondary device. Block 902 can include using the SPI interface to send a first message from the first chiplet to the second chiplet, such as in a system with two or more chiplets. [0105] The first message can include various fields, such as a command field with one or more bits configured to enable access to the second chiplet, and a chiplet identification field with one or more bits configured to indicate or specify the second chiplet from among one or more other chiplets in the system. In an example, the first message comprises a request for a particular data payload from the second chiplet. In an example, the first message comprises an initialization instruction for the second chiplet. [0106] At block 904, the first method 900 can include receiving the first message at the second chiplet. At block 906, the first method 900 can include using the second chiplet to prepare a response message to the first message. In an example, the response message can include one or more fields or bits, such as a secondary device status field. The status field can include one or more bits that indicate a status of the second chiplet, including a readiness of the second chiplet to provide a particular data payload to the first chiplet. At block 908, the second chiplet can use the SPI interface to send the response message to the first chiplet. In an example, the response message can include information about an initialization status of the second chiplet. [0107] At block 910, the first method 900 can include receiving the response message at the first chiplet, such as via the SPI interface. At block 912, the first method 900 can include using the same SPI interface to send a subsequent second message from the first chiplet to the second chiplet. The subsequent second message can include, for example, a particular data request. In an example, the first message and the second message comprise requests for the same data payload from the same second chiplet. For example, the first and second messages can comprise requests for verification or timing information about initialization of the second chiplet. [0108] At block 914, the second chiplet can prepare an updated response message. In an example, the updated response message can include a data payload corresponding to the data request in the second message. For example, the payload can include information indicating that the second chiplet is initialized and ready to begin using another protocol or bus to carry out other operations. At block 916, the first method 900 can include using the SPI interface to send the updated response message with the data payload from the second chiplet to the first chiplet. [0109] FIG. 10 illustrates a block diagram of an example machine 1000 with which, in which, or by which any one or more of the techniques (e.g., methodologies) discussed herein can be implemented. Examples, as described herein, can include, or can operate by, logic or a number of components, or mechanisms in the machine 1000. Circuitry (e.g., processing circuitry) is a collection of circuits implemented in tangible entities of the machine 1000 that include hardware (e.g., simple circuits, gates, logic, etc.). Circuitry membership can be flexible over time. Circuitries include members that can, alone or in combination, perform specified operations when operating. In an example, hardware of the circuitry can be immutably designed to carry out a specific operation (e.g., hardwired). In an example, the hardware of the circuitry can include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including a machine readable medium physically modified (e.g., magnetically, electrically, moveable placement of invariant massed particles, etc.) to encode instructions of the specific operation. In connecting the physical components, the underlying electrical properties of a hardware constituent are changed, for example, from an insulator to a conductor or vice versa. The instructions enable embedded hardware (e.g., the execution units or a loading mechanism) to create members of the circuitry in hardware via the variable connections to carry out portions of the specific operation when in operation. Accordingly, in an example, the machine readable medium elements are part of the circuitry or are communicatively coupled to the other components of the circuitry when the device is operating. In an example, any of the physical components can be used in more than one member of more than one circuitry. For example, under operation, execution units can be used in a first circuit of a first circuitry at one point in time and reused by a second circuit in the first circuitry, or by a third circuit in a second circuitry at a different time. Additional examples of these components with respect to the machine 1000 follow. [0110] In alternative embodiments, the machine 1000 can operate as a standalone device or can be connected (e.g., networked) to other machines. In a networked deployment, the machine 1000 can operate in the capacity of a server machine, a client machine, or both in server-client network environments. In an example, the machine 1000 can act as a peer machine in peer-to- peer (P2P) (or other distributed) network environment. The machine 1000 can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a network router, switch or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations. [0111] The machine 1000 (e.g., computer system) can include a hardware processor 1002 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 1008, a static memory 1010 (e.g., memory or storage for firmware, microcode, a basic-input-output (BIOS), unified extensible firmware interface (UEFI), etc.), and mass storage 1012 (e.g., hard drives, tape drives, flash storage, or other block devices) some or all of which can communicate with each other via an interlink 1018 (e.g., a bus, such as an SPI bus). The machine 1000 can further include a display device 1020, an alphanumeric input device 1022 (e.g., a keyboard), and a user interface (UI) navigation device 1024 (e.g., a mouse). In an example, the display device 1020, input device 1022, and navigation device 1024 can be a touch screen display. The machine 1000 can additionally include a mass storage 1012 (e.g., drive unit), a signal generation device 1028 (e.g., a speaker), a network interface device 1014, and one or more sensor(s) 1026, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine 1000 can include an output controller 1030, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.). [0112] Registers of the processor 1002, the main memory 1008, the static memory 1010, or the mass storage 1012 can be, or include, a machine-readable medium 1006 on which is stored one or more sets of data structures or instructions 1004 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 1004 can also reside, completely or at least partially, within any of registers of the processor 1002, the main memory 1008, the static memory 1010, or the mass storage 1012 during execution thereof by the machine 1000. In an example, one or any combination of the hardware processor 1002, the main memory 1008, the static memory 1010, or the mass storage 1012 can constitute the machine-readable medium 1006 or media. While the machine-readable medium 1006 is illustrated as a single medium, the term “machine readable medium” can include a single medium or multiple media (e.g., a centralized or distributed database, or associated caches and servers) configured to store the one or more instructions 1004. In an example, the various memory units or processor 1002 can be communicatively coupled using a bus such as an SPI bus. [0113] The term “machine readable medium” can include any medium that is capable of storing, encoding, or carrying instructions for execution by the machine 1000 and that cause the machine 1000 to perform any one or more of the techniques of the present disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting machine readable medium examples can include solid-state memories, optical media, magnetic media, and signals (e.g., radio frequency signals, other photon based signals, sound signals, etc.). In an example, a non-transitory machine readable medium comprises a machine readable medium with a plurality of particles having invariant (e.g., rest) mass, and thus are compositions of matter. Accordingly, non-transitory machine- readable media are machine readable media that do not include transitory propagating signals. Specific examples of non-transitory machine readable media can include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto- optical disks; and CD-ROM and DVD-ROM disks. [0114] In an example, information stored or otherwise provided on the machine-readable medium 1006 can be representative of the instructions 1004, such as instructions 1004 themselves or a format from which the instructions 1004 can be derived. This format from which the instructions 1004 can be derived can include source code, encoded instructions (e.g., in compressed or encrypted form), packaged instructions (e.g., split into multiple packages), or the like. The information representative of the instructions 1004 in the machine-readable medium 1006 can be processed by processing circuitry into the instructions to implement any of the operations discussed herein. For example, deriving the instructions 1004 from the information (e.g., processing by the processing circuitry) can include: compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamically or statically linking), encoding, decoding, encrypting, unencrypting, packaging, unpackaging, or otherwise manipulating the information into the instructions 1004. [0115] In an example, the derivation of the instructions 1004 can include assembly, compilation, or interpretation of the information (e.g., by the processing circuitry) to create the instructions 1004 from some intermediate or preprocessed format provided by the machine- readable medium 1006. The information, when provided in multiple parts, can be combined, unpacked, and modified to create the instructions 1004. For example, the information can be in multiple compressed source code packages (or object code, or binary executable code, etc.) on one or several remote servers. The source code packages can be encrypted when in transit over a network and decrypted, uncompressed, assembled (e.g., linked) if necessary, and compiled or interpreted (e.g., into a library, stand-alone executable etc.) at a local machine, and executed by the local machine. [0116] The instructions 1004 can be further transmitted or received over a communication network 1016 using a transmission medium via the network interface device 1014 utilizing any one of a number of transfer protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks can include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), mobile telephone networks (e.g., cellular networks), plain old telephone (POTS) networks, and wireless data networks (e.g., Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards known as Wi-Fi®, IEEE 802.16 family of standards known as WiMax®), IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, among others. In an example, the network interface device 1014 can include one or more physical jacks (e.g., Ethernet, coaxial, or phone jacks) or one or more antennas to connect to the communication network 1016. In an example, the network interface device 1014 can include a plurality of antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. The term “transmission medium” shall be taken to include any intangible medium that is capable of storing, encoding or carrying instructions for execution by the machine 1000, and includes digital or analog communications signals or other intangible medium to facilitate communication of such software. A transmission medium is a machine readable medium. [0117] The following are examples or devices and methods in accordance with the teachings herein. [0118] Example 1 can include a chiplet system comprising a first chiplet coupled to multiple other chiplets using a serial peripheral interface (SPI) interface using an SPI protocol, the first chiplet configured as an SPI primary device. In Example 1, the first chiplet can be configured to send a first message across the SPI interface, the first message comprising a command field configured to access a first selected chiplet of the multiple other chiplets. In Example 1, the first selected chiplet can be configured as an SPI secondary device or peripheral device. Example 1 can further include the first chiplet configured to receive a response message from the first selected chiplet in response to the first message, and the response message can include a secondary device status field of the response message. The secondary device status field can indicate a readiness of the first selected chiplet to provide a data payload to the first chiplet. [0119] Example 2 can include or use features of Example 1, and can further include the secondary device status field having one or more bits set to indicate a deferred return status, and the first chiplet can be further configured to, in response to receiving a response message with one or more bits set to indicate a deferred return status, send a deferred read request to the first selected chiplet. [0120] Example 3 can include or use the features of Example 2, and can further include the first selected chiplet. In response to the deferred read request, the first selected chiplet can be configured to send an updated response message to the primary device, and the updated response message can comprise the secondary device status field having one or more bits to indicate a subsequent readiness of the secondary device to provide the data payload to the primary device. [0121] Example 4 can include or use features of any of the preceding examples, and can further include, in the command field of the first message, one or more bits set to indicate whether the primary device previously received a deferral from the secondary device. [0122] Example 5 can include or use features of any of the preceding examples, and can further include, in the first message, a register address field of the first message, the register address field including one or more bits set to indicate an address of a memory register on the first selected chiplet. [0123] Example 6 can include or use the features of Example 5, wherein the first message comprises a data field, and data in the data field is configured to be stored in a location corresponding to the register address field of the first message. [0124] Example 7 can include or use the features of Example 6, wherein the first message comprises a chiplet identification field of the first message indicating the first selected chiplet of the multiple other chiplets, and wherein in the first message, the data field immediately follows the chiplet identification field, and the chiplet identification field immediately follows the command field. [0125] Example 8 can include or use features of any of the preceding examples, wherein the response message comprises the payload, and the payload comprises data from a memory register on the first selected chiplet. [0126] Example 9 can include or use features of any of the preceding examples, wherein the command field of the first message includes one or more bits set to enable the first selected chiplet to access specified memory registers on the first selected chiplet. [0127] Example 10 can include a system comprising a first chiplet coupled to multiple to multiple other chiplets, wherein the first chiplet is configured to generate a clock signal, and Example 10 can further include a first selected chiplet of the multiple other chiplets, wherein the first selected chiplet is configured to interface with the first chiplet using a serial peripheral interface (SPI) interface protocol. In Example 10, the first chiplet can be configured to perform operations comprising: enable a controller on the first selected chiplet, send the clock signal to the first selected chiplet, send a first message to the first selected chiplet using the SPI interface, wherein the first message comprises a command field of the first message, the command field including one or more bits to enable the controller to access memory registers of the first selected chiplet, and a register address field of the first message, the register address field including one or more bits to address a particular memory register on the first selected chiplet chiplet. In Example 10, in response to receiving the first message, the first selected chiplet can be configured to send a response message to the first chiplet using the SPI interface, wherein the response message comprises a secondary device status field including one or more bits to indicate a readiness of the first selected chiplet to provide a payload to the first chiplet. [0128] Example 11 can include or use the features of Example 10, wherein the first message further comprises a data field of the first message. [0129] Example 12 can include or use the features of Example 10 or Example 11, wherein the response message comprises the payload when the secondary device status field indicates the first selected chiplet is ready to provide the payload. [0130] Example 13 can include or use the features of any of Examples 10-12, wherein the response message comprises one or more bits set to instruct the first chiplet to queue a later read request for the first selected chiplet. [0131] Example 14 can include or use the features of any of Examples 10-13, wherein the first message comprises a chiplet identification field of the first message, the chiplet identification field including one or more bits to address the first selected chiplet, and wherein in the first message, the chiplet identification field immediately follows the command field, and the register address field immediately follows the chiplet identification field. [0132] Example 15 can include or use the features of any of Examples 10-14, wherein the response message leads with the secondary device status field before one or more other data bits. [0133] Example 16 can include a method comprising, at a first chiplet that is configured to be communicatively coupled to a second chiplet using a serial peripheral interface (SPI) interface bus, sending a first message to the second chiplet, wherein the first message comprises a command field of the first message including one or more bits configured to enable access to the second chiplet. In Example 16, the method can comprise, receiving a response message from the second chiplet in response to the first message from the first chiplet, the response message comprising a secondary device status field, wherein the secondary device status field includes one or more bits selected to indicate a readiness of the second chiplet to provide a data payload to the first chiplet. [0134] Example 17 can include or use the features of Example 16, and can further include preparing the response message at the second chiplet. Preparing the response message at the second chiplet can include preparing a response message that indicates a deferral in the secondary device status field, and the method can further include receiving the response message at the first chiplet, and sending a subsequent second message to the second chiplet to determine whether the data payload is available. [0135] Example 18 can include or use the features of Example 17, and can further include, in response to the subsequent second message, sending an updated response message from the second chiplet to the first chiplet, the updated response message comprising one or more bits in the secondary device status field to indicate a subsequent readiness of the second chiplet to provide the data payload to the first chiplet. [0136] Example 19 can include or use the features of any of Examples 16-18, wherein the command field of the first message indicates whether the first message is an original read request or a deferred read request for information in a specified register of the second chiplet. [0137] Example 20 can include or use the features of any of Examples 16-19, wherein the first chiplet is communicatively coupled to a third chiplet using the SPI interface bus, and the method further comprises, at the first chiplet, sending a second message to the third chiplet, wherein the second message comprises a command field of the second message including one or more bits configured to enable access to the third chiplet, and at the third chiplet, receiving the second message from the first chiplet and, in response, preparing a second response message that comprises a secondary device status field, wherein the secondary device status field includes one or more bits selected to indicate a readiness of the third chiplet to provide a data payload to the first chiplet. [0138] Each of the above Examples can be combined or used together in various ways to carry out deferred communications over a synchronous interface, such as over an SPI interface. [0139] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples”. Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein. [0140] In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” can include “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein”. Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects. [0141] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features can be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter can lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.