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Patent Searching and Data


Title:
DELAY TIME DETECTION CIRCUIT, TIMESTAMP INFORMATION GENERATION DEVICE, AND DELAY TIME DETECTION METHOD
Document Type and Number:
WIPO Patent Application WO/2020/100374
Kind Code:
A1
Abstract:
This delay time detection circuit comprises a clock generation unit (11), counting unit (12), subscale signal generation unit (13), and delay time calculation unit (14). The clock generation unit (11) generates a subscale clock signal on the basis of a system clock signal. The counting unit (12) generates a count signal while sequentially and repeatedly incrementing by a preset counting number on the basis of the subscale clock signal. The subscale signal generation unit (13) receives the count signal and generates a number of subscale signals equal to the counting number that have, in a one-to-one ratio with the counting number, square waves of a duration corresponding to a second period and timings that are shifted according to the second period. The delay time calculation unit (14) receives an input clock signal and calculates the delay time, within a first period, of the input clock signal in relation to the system clock signal on the basis of one subscale signal having a timing matching that of the input clock signal.

Inventors:
TAKAHASHI MASAYUKI (JP)
Application Number:
PCT/JP2019/033300
Publication Date:
May 22, 2020
Filing Date:
August 26, 2019
Export Citation:
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Assignee:
NEC PLATFORMS LTD (JP)
International Classes:
G04G5/00; G04F10/06; H03K5/26
Foreign References:
JPH05333169A1993-12-17
JP2018054352A2018-04-05
JP2002196087A2002-07-10
JPS6017389A1985-01-29
JPS5390973A1978-08-10
US9379714B12016-06-28
JP2018054352A2018-04-05
JP2008131659A2008-06-05
JP2018212047A2018-11-12
Other References:
See also references of EP 3865956A4
Attorney, Agent or Firm:
IEIRI Takeshi (JP)
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