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Title:
A DIFFERENTIAL DELTA-SIGMA MODULATOR FOR A HEARING AID
Document Type and Number:
WIPO Patent Application WO/2021/063874
Kind Code:
A1
Abstract:
A differential delta-sigma-modulator has an integrator (49) including a pair of single-ended amplifiers (46, 47). The differential delta-sigma-modulator comprises a sample clock (50) driving a first switchable capacitor configuration (31) and a second switchable capacitor configuration (32) at a predetermined switching cycle. The second switchable capacitor configuration (32) is adapted for sampling respective outputs from the pair of single-ended amplifiers (46, 47) on a pair of output sampling capacitors (C3, C5) in the first part of the switching cycle (P1), and charging a common mode capacitor (C4) with the average voltage of the voltage sampled by the pair of output sampling capacitors (C3, C5) in the second part of the switching cycle (P2). The voltage across the common mode capacitor (C4) represents the common mode voltage for the integrator (49).

Inventors:
KNUDSEN, Niels Ole (Lynge, DK)
Application Number:
EP2020/077080
Publication Date:
April 08, 2021
Filing Date:
September 28, 2020
Export Citation:
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Assignee:
WIDEX A/S (Lynge, DK)
International Classes:
H03M3/02; H03F3/45
Download PDF:
Claims:
C L A I M S

1. A differential delta-sigma-modulator having an integrator (49) including a pair of single- ended amplifiers (46, 47) and comprising: a sample clock (50) driving a first switchable capacitor configuration (31) and a second switchable capacitor configuration (32) at a predetermined switching cycle; wherein second switchable capacitor configuration (32) is adapted for: o sampling respective outputs from the pair of single-ended amplifiers (46, 47) on a pair of output sampling capacitors (C3, C5) in the first part of the switching cycle (PI); and o charging a common mode capacitor (C4) with the average voltage of the voltage sampled by the pair of output sampling capacitors (C3, C5) in the second part of the switching cycle (P2); wherein the voltage across the common mode capacitor (C4) represents the common mode voltage for the integrator (49).

2. The differential delta-sigma-modulator according to claim 1, wherein the second switchable capacitor configuration (32), during a second part of the switching cycle (P2), is adapted for providing a feed-back path to respective inputs of the pair of single-ended amplifiers (46, 47) via a pair of common mode feedback capacitors (C6, C7).

3. The differential delta-sigma-modulator according to claim 1, wherein the first switchable capacitor configuration (31) is adapted for: sampling input from a pair of differential input terminals (30) by means of an input sampling capacitor (Cs) during a first part (Pi) of the switching cycle; and delivering the sampled input from the input sampling capacitor (Cs) to respective inputs of the pair of single-ended amplifiers (46, 47) during a second part (P2) of the switching cycle.

4. The differential delta-sigma-modulator according to claim 3 wherein the second switchable capacitor configuration (32), in a second part (P2) of the switching cycle, is adapted for providing a feed through path for the sampled input on the input sampling capacitor (Cs) to respective inputs of the pair of single-ended amplifiers (46, 47). 5. The differential delta-sigma-modulator according to claim 1, wherein a quantizer (48) is adapted for comparing the output from the pair of single-ended amplifiers (46, 47) and outputting a logical level in accordance to the comparison.

6. The differential delta-sigma-modulator according to claim 5, wherein the first switchable capacitor configuration (31) in first part of the switching cycle is adapted for sampling an output signal from the quantizer (48) by means of the pair of common mode feedback capacitors (C6, C7) in the first part (Pi) of the switching cycle; and connecting the pair of common mode feedback capacitors (C6, C7) to respective inputs of the pair of single-ended amplifiers (46, 47) in the second part (P2) of the switching cycle.

7. The differential delta-sigma-modulator according to claim 1 wherein sample clock (50) driving of the first and second switchable capacitor configurations (31, 32) is adapted for providing a sampling cycle consisting of two non-overlapping periods (Pi, P2).

8. A hearing assistive device having a microphone (61) providing a differential output (62) and a differential delta-sigma-modulator (40) according to claim 1 for delivering an output signal for signal processing.

9. A method of operating a differential delta-sigma-modulator having an integrator including a pair of single-ended amplifiers and comprising: driving a first and a second switchable capacitor configuration at a predetermined switching cycle; sampling respective outputs from the pair of single-ended amplifiers on a pair of output sampling capacitors in the first part of the switching cycle; and charging the average voltage of the voltage sampled by the pair of output sampling capacitors on a common mode capacitor in a second part of the switching cycle, wherein the voltage across the common mode capacitor represents the common mode voltage for the integrator.

10. The method according to claim 9 and further comprising providing a feed-back path via a pair of common mode feedback capacitors to respective inputs of the pair of single-ended amplifiers in a second part of the switching cycle.

11. The method according to claim 9 and further comprising sampling in a first part of the switching cycle input from a pair of differential input terminals on an input sampling capacitor; and delivering the sampled input from the input sampling capacitor to respective inputs of the pair of single-ended amplifiers in a second part of the switching cycle.

12. The method according to claim 11 and further comprising providing a feed through path for the sampled input on the input sampling capacitor to respective inputs of the pair of single-ended amplifiers in a second part of the switching cycle.

13. The method according to claim 9 and further comprising comparing the output from the pair of single-ended amplifiers and outputting a logical level in accordance to the comparison.

14. The method according to claim 13 and further comprising sampling an output signal from a quantizer by means of the pair of common mode feedback capacitors in first part of the switching cycle; and connecting the pair of common mode feedback capacitors to respective inputs of the pair of single-ended amplifiers in a second part of the switching cycle.

15. The method according to claim 9 wherein the sampling cycle driving of the first and second switchable capacitor configurations is consisting of two non-overlapping periods.

16. A differential delta-sigma-modulator having two differential input terminals (30) and further comprising: an integrator (49) including a pair of single-ended amplifiers (46, 47); a first switchable capacitor configuration (31) provided between the two differential input terminals (30) and the input of the pair of single-ended amplifiers (46, 47); a second switchable capacitor configuration (32) provided between inputs and outputs of respective pair of single-ended amplifiers (46, 47); and a sample clock (50) for driving the first switchable capacitor configuration (31) and the second switchable capacitor configuration (32) at a predetermined switching cycle.

17. The differential delta-sigma-modulator according to claim 16, wherein the second switchable capacitor configuration (32) in a first part of the switching cycle (Pi) samples the output from the pair of single-ended amplifiers (46, 47) by means of a pair of output sampling capacitors (C3, C5).

18. The differential delta-sigma-modulator according to claim 16, wherein the second switchable capacitor configuration (32) in a second part (P2) of the switching cycle is adapted for charging a common mode capacitor (C4) charged by the average of the voltage sampled by the pair of output sampling capacitors (C3, C5), wherein the voltage across the common mode capacitor (C4) represents the common mode voltage for the integrator (49).

19. The differential delta-sigma-modulator according to claim 18, wherein the second switchable capacitor configuration (32) in a second part (P2) of the switching cycle furthermore provides a feed-back path via a pair of common mode feedback capacitors (C6, C7) to a respective input of the pair of single-ended amplifiers (46, 47).

20. The differential delta-sigma-modulator according to claim 16, wherein the first switchable capacitor configuration (31) in a first part of the switching cycle (Pi) samples input from the pair of differential input terminals (30) by means of an input sampling capacitor (Cs).

21. The differential delta-sigma-modulator according to claim 20, wherein the first switchable capacitor configuration (31) in a second part (P2) of the switching cycle provides a feed through path for the sampled input value on the input sampling capacitor (Cs) to respective inputs of the pair of single-ended amplifiers (46, 47).

22. The differential delta-sigma-modulator according to claim 16 and further comprising a quantizer (48) comparing the output from the pair of single-ended amplifiers (46, 47) and outputting a logical level in accordance to the comparison.

23. The differential delta-sigma-modulator according to claim 22, wherein the pair of common mode feedback capacitors (C6, C7) in first part of the switching cycle (Pi) samples an output signal from the quantizer (48), and wherein the first switchable capacitor configuration (31) in a second part (P2) of the switching cycle connects the pair of common mode feedback capacitors (C6, C7) to respective inputs of the pair of single-ended amplifiers (46, 47).

24. The differential delta-sigma-modulator according to claim 16, wherein the sample clock (50) provides a sampling cycle consisting of two non-overlapping periods (Pi, P2).

25. A hearing assistive device having a microphone (61) providing a differential output (62) and a differential delta-sigma-modulator (40) according to claim 16 for delivering an output signal for signal processing.

Description:
A DIFFERENTIAL DELTA-SIGMA MODULATOR FOR A HEARING AID

The present invention relates to hearing aids. The invention, more particularly, relates to a hearing aid including a differential delta-sigma modulator for providing a digitized signal.

It is desirable to use differential topologies for sensitive analog circuits in complex mixed mode integrated circuits. The differential topologies are highly immune to noise coupling from adjacent circuitries. This immunity becomes increasingly important with higher demand for integration of more functionalities on the integrated circuits or chips.

However, in power sensitive applications like hearing aids, it can be advantageous to use single ended topologies, as single ended amplifiers for same noise performance generally consume less power compared to differential amplifiers.

The purpose of the invention is to provide a differential delta-sigma modulator having a low power consumption. There is a demand for increasing integration of our audio converters with other circuitries. Easy integration and noise immunity are increasingly important.

This purpose is according to the invention achieved by a differential delta-sigma-modulator comprising a pair of single-ended amplifiers. The invention is defined in claims 1, 8, 9, 16, 25. Preferred embodiments are defined in the dependents claims.

The invention will be described in further detail with reference to preferred aspects and the accompanying drawing, in which: fig. 1 illustrates the basic principles of a delta-sigma-modulator; fig. 2 shows a basic single-stage single-ended amplifier; fig. 3 illustrates schematically one embodiment of a differential delta-sigma-modulator according to the invention; fig. 4 illustrates one embodiment of a differential delta-sigma modulator according to the invention, and figs. 5a and 5b illustrates the differential delta-sigma modulator shown in fig. 4 in respective one of the two non-overlapping periods of the sampling cycle; fig. 6 shows an embodiment of the invention where the differential delta-sigma-modulator is included in a hearing assistive device.

DETAILED DESCRIPTION

Delta-sigma modulation is a method for encoding analog signals into digital signals. In one embodiment of the invention, a delta-sigma modulator is used for converting an analogue input signal into higher-frequency digital signals. According to one embodiment of the invention, a delta-sigma modulator is used for converting an output from a differential microphone into a 1-bit bitstream for further signal processing, e.g. in a hearing aid.

The delta-sigma modulator according to one embodiment of the invention comprises an integrator, a quantizer and a feed-back loop. The number of integrators, and consequently, the numbers of feedback loops, defines the order of the delta-sigma modulator. In general, first-order modulators are unconditionally stable, while higher-order modulators stability shall be ensured via the actual design.

In an ideal differential circuit, the output signal is represented by a differential voltage (difference), whereas the output common mode (sum) is ideally zero (as the two outputs are equal but have opposite signs). Similarly, the input signal is interpreted as a voltage difference. An ideal differential circuit only responds to voltage differences and ignores common mode voltages.

The advantage of the differential circuit is that external noise affects both outputs equally, so such noise is entered as common mode and not as differential. This means that the differential circuit rejects external noise sources. External disturbances may for example originate from substrate noise, power supply or reference noise. Common mode amplification will ideally be zero, but for circuits in practice, the common mode amplification may differ from zero.

It is important, that common mode amplification is moderate, so that the common mode signals do not saturate the outputs (following circuits). Common mode amplification should therefore preferably be less than 1, otherwise the common mode amplification may end up being too large when cascading further differential blocks, e.g. in a higher order delta sigma modulator.

In case a circuit is well balanced, the Common Mode Rejection Ratio (CMRR) is high, why it is not so important that the common mode amplification is to zero. A good balance enables the circuit to resist common mode signals on the input without introducing a differential residual on the output.

In one embodiment, the common mode amplification is small, in order to ensure that common mode voltage is not amplified from one modulator stage to the following modulator stage or integrator stage and thereby risking saturation of subsequent differential circuitries. In one embodiment, the common mode amplification is one; and in other embodiments the common mode amplification is slightly lower than one, e.g. in the range 0,9 - 1.

Fig. 1 illustrates the basic principles of a delta-sigma-modulator, e.g. for use in a hearing aid or a hearing assistive device. On an input 10, delta-sigma-modulator receives an analog input signal representing e.g. an audio signal picked up by means of an input transducer like a microphone. The analog input signal is via an adder 11 directed to an integrator 12 integrating the signal received from the adder 11, and further to a quantizer 13 outputting a digitized signal based on the signal received from the adder 11 and integrated in the integrator 12, a reference signal and a clock signal controlling the sample frequency or bit- rate of the output signal. The signal delivered to an output 14 from the quantizer 13 is via a feed-back loop fed back to the adder 11 and subtracted from the analog input signal. The feed-back loop includes a 1-bit digital -to-analog converter 15 ensuring that the feedback signal is presented to the adder 11 as an analog signal. Fig. 2 shows a basic single-stage single-ended amplifier 20 having a first p-channel MOSFET transistor 21 and a second n-channel MOSFET transistor 22. The single-stage single-ended amplifier 20 is powered by a positive supply voltage, V dd , and a negative supply voltage or ground V ss . The input signal supplied to the single-stage single-ended amplifier 20 is received on the input terminal V m , and the output provided by the single- stage single-ended amplifier 20 is delivered on the output terminal V out .

The single-stage single-ended amplifier 20 shown in fig. 2 is very power efficient. Furthermore, the single-stage single-ended amplifier 20 exhibits several advantages when a pair of single-stage single-ended amplifiers 20 are used in an integrator stage of a delta- sigma-modulator according to the invention. Both transistors 21 and 22 contribute to transconductance. Therefore, the input referred voltage noise for the combined transistors 21, 22 end up being lower than the noise from each of the individual transistors 21, 22. This is an improvement compared to commonly used differential amplifiers topologies where transistor noise sums up. Furthermore, non-linearities in each individual transistor tends to cancel the opposite transistors non-linearity. The combined characteristic of both transistors is more linear than a single transistor.

Furthermore, the single-stage single-ended amplifier 20 shown in fig. 2 has excellent input and output properties. The single-stage single-ended amplifier 20 operates as a push-pull amplifier that alternately supplying current to, or absorbing current from, a connected load. A push-pull amplifier is generally very efficient and may achieve high output power. The transconductance increases when the amplifiers input amplitude is large, which reduces settling time. A combined single stage input- and output stage is power efficient compared to topologies with multiple gain stages. In addition, a single stage amplifier is inherently stable in a closed loop. This allows use of the amplifier without frequency compensation and therefor with fast settling. In a differential configuration power supply noise (e.g. on V dd ) appears as common mode and gets rejected.

According to the invention, the common mode is fed-back from the output to the input for taming the common mode gain. This does not change the important differential properties of the circuit. This will be explained in detail below. Fig. 3 illustrates schematically one embodiment of a differential delta-sigma-modulator according to the invention. The differential delta-sigma-modulator has two differential input terminals 30 and an integrator 49 including a pair of single-ended amplifiers 46, 47. The integrator 49 has a first switchable capacitor configuration 31 provided between the two differential input terminals 30 and the input of the pair of single-ended amplifiers 46, 47; and a second switchable capacitor configuration 32 provided between inputs and outputs of respective pair of single-ended amplifiers 46, 47. A sample clock 50 is used for driving the two switchable capacitor configuration 31, 32 at a predetermined switching cycle. In one embodiment, the sample clock 50 provides a sampling cycle consisting of two non-overlapping parts or periods PI, P2.

In one embodiment, the second switchable capacitor configuration 32 comprises a pair of output sampling capacitors C3, C5, and the switches S½, S17, as shown in fig. 4, for sampling respective outputs from the pair of single-ended amplifiers 46, 47 on in the first part of the switching cycle Pi. The second switchable capacitor configuration 32 further comprises a common mode capacitor C4 and switches S26, S27 adapted for charging the common mode capacitor C4 with the low-pass filtered average voltage of the voltage sampled by the pair of output sampling capacitors C3, C5 in the second part of the switching cycle P2. The voltage across the common mode capacitor C4 represents the low-pass filtered common mode voltage for the integrator 49.

In one embodiment, the second switchable capacitor configuration 32 provides, in a second part P2 of the switching cycle, a feed-back path via a pair of capacitors C , C7 and switches S23, S21, S25 to a respective input of the two single-ended amplifiers 46, 47, as shown in fig. 4.

In one embodiment, the first switchable capacitor configuration 31 comprises a input sampling capacitor Cs, and the switches S12, S14, as shown in fig. 4, for sampling input from the differential input terminals Vi n +, Vin- (referred to as 30 in fig. 3) during the first part Pi of the switching cycle, and switches S22, S24 for delivering the sampled input from the input sampling capacitor Cx to respective inputs of the pair of single-ended amplifiers 46, 47 during a second part P2 of the switching cycle. In one embodiment, a third switchable capacitor configuration comprises switches Sn, S15, as shown in fig. 4, adapted for sampling an output signal from the quantizer 48 by means of the pair of common mode feedback capacitors C , C7 during the first part Pi of the switching cycle. The switches S21, S25 are adapted for connecting the output from the quantizer 48 sampled by the pair of common mode feedback capacitors C , Cvto respective inputs of the pair of single-ended amplifiers 46, 47 during the second part P2 of the switching cycle.

In one embodiment, the differential delta-sigma-modulator further comprises a quantizer 48 (operating as a comparator) comparing the output from the pair of single-ended amplifiers 46, 47 and outputting a logical level in accordance to the comparison. The two of capacitors C , C7 (fig. 4 and 5a) samples, in first part of the switching cycle Pi, an output signal from the quantizer 48. The first switchable capacitor configuration 31 connects, in a second part P2 of the switching cycle, the pair of capacitors C , C7 to respective inputs of the pair of single-ended amplifiers 46, 47.

Referring to fig. 4, a differential delta-sigma modulator 40 according to one embodiment of the invention is shown. The differential delta-sigma modulator 40 has a differential input, Vin+ and Vin-, followed by a differential integrator 49 marked in dotted lines and being based on the two single-ended amplifiers 46 and 47.

The first single-ended amplifier 46 is formed by a first inverting amplifier 41 and a capacitor Ci, and the second single-ended amplifier 47 is formed by a second inverting amplifier 42 and a capacitor C2. The output from the two single-ended amplifiers 46, 47 is fed to the input of a comparator 43, whose single-ended output is received at the D-input of a flip-flop 44. Together, the comparator 43 and the flip-flop 44 form a quantizer 48. The Q-output from the flip-flop 44 provided an output 45 of the delta-sigma modulator. The Q- output and the inverted Q-output from the flip-flop 44 is fed back to the input of respective single-ended amplifiers 46, 47 via respective feedback paths.

In the embodiment shown in fig. 4, the differential delta-sigma modulator 40 according to the invention includes a plurality of switches S11-S17 and S21-S27. The switches S11-S17 and S21-S27 operate at sampling frequency. A sampling cycle consists of two non-overlapping periods denoted Pi and P2. The switches S11-S17 are activated (closed) in the Pi-period, and thereafter deactivated (open) in the P 2 -period. The switches S 21 -S 27 are deactivated (open) in the Pi-period, and thereafter activated (closed) in the P 2 -period.

The two switches SI 1 and SI 5 belongs to the feed-back loop of the differential delta-sigma modulator 40. The two single-ended amplifiers 46 and 47, the switches S12-S14, S16-S17, and S 21 -S 27 , and the capacitors C 3 -C 8 form the integrator 49 of the differential delta-sigma modulator 40.

Because of that the switches S11-S17 are closed and the switches S21-S27 are open in the Pi- period, two capacitors C3 and C5 samples respectively the output voltages of the two single- ended amplifiers 41 and 42 in the Pi-period as seen in fig. 5a. In period P2, the two capacitors C3 and C5 are connected by switches S26 and S27, which results in providing an average voltage of the two capacitors C3 and C5 charging a capacitor C4 during the P2- period. The average voltage represents the common mode voltage. The function of a switching capacitor charging another capacitor is equivalent to a low pass filter. The lowpass filtered common mode voltage is fed back to the inputs of the amplifiers 41 and 42 via two sampling capacitors C 6 and C7 as seen in fig. 5b.

The signal present on the differential input, Vi n + and Vm-, is during the Pi-period sampled by a capacitor Cs as seen in fig. 5a and delivered as input to the two single-ended amplifiers 46 and 47 during the P 2 -period as seen in fig. 5b.

The proposed solution is extremely power efficient. The power of operating the plurality of switches S 11 -S 17 and S 21 -S 27 is practically negligible. Another significant advantage of the common mode feedback circuit is that the switch capacitor noise of the second switchable capacitor configuration 32 only adds common mode noise but not differential noise. This is of importance for the performance of the differential delta-sigma modulator 40 using the two single-ended amplifiers 46 and 47. Common mode voltage gain approximates 1.

Fig. 4 illustrates a first order delta-sigma modulator 40 according to one embodiment of the invention and acting as an analog-to-digital converter. The differential integrator 49 has two inputs, one coming from the differential input, Vi n + and Vm- of the delta-sigma modulator 40, the other is the feedback from the Flip-Flop 44 or the quantizer 48. In order to control the common mode DC of the two single-ended amplifiers 46, 47 it is required to feed-back common mode via at least one of the two integrator inputs 30. The capacitor Cx samples the differential input voltage received at the two integrator inputs 30(Vm+ and Vm-)· The differential input voltage has no reference to ground. The common mode feedback is entered via the sampling caps C 6 and Ci.

The inventive concept is generally applicable to any delta-sigma analog-to-digital converter. It is desired for most high high-performance converters to implement them differentially, why the power saving solution according to the invention where the integrator is implemented as simple, single-ended amplifiers is very attractive.

Compared to a single-ended configuration, the differential delta-sigma converter or modulator using simple, single-ended amplifiers in the integrator stage will increase dynamic range for same power usage and make the converter more tolerable to noise from other circuits on the same chip. The converter will also emit less noise to other circuits.

In one embodiment of the invention shown in fig. 6, the differential delta-sigma-modulator 40 according to the invention having an integrator 49 including a pair of single-ended amplifiers 46, 47, is included in a hearing assistive device 60, such as a hearing aid. The delta-sigma-modulator 40 receives a differential signal directly from a microphone 61 with a differential output 62. The delta-sigma-modulator 40 delivers an output signal to a digital signal processor (DSP) 63 for processing the digital signal so an audio signal output via a receiver or speaker 64 by the hearing assistive device 60 will be conditioned and amplified at frequencies in those parts of the audible frequency range where the user suffers a hearing deficit.