Title:
DYNAMIC DIVIDER HAVING INTERLOCKING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2014/209717
Kind Code:
A3
Abstract:
A high-speed and low power divider (100) includes a ring of four dynamic latches (101-104), an interlocking circuit (110), and four output inverters (106-109). Each latch has a first dynamic node M and a second dynamic node N. The interlocking circuit is coupled to the M nodes. Based on one or more of the M node signals received, the interlocking circuit selectively controls the logic values on one or more of the M modes such that over time, as the divider is clocked (Clk, ClkB), only one of the signals on the N nodes is low at a given time. The output inverters generate inverted versions of the N node signals that are output from the divider as low phase noise 25% duty cycle output signals I, IB, Q and QB. In one specific example, each latch has eight transistors and no more than eight transistors (fig. 14: 115-122). The divider recovers quickly and automatically from erroneous state disturbances.
Inventors:
GOLDBLATT JEREMY MARK (US)
GODBOLE DEVAVRATA VASANT (US)
PAN HSUANYU (US)
GODBOLE DEVAVRATA VASANT (US)
PAN HSUANYU (US)
Application Number:
PCT/US2014/042952
Publication Date:
March 05, 2015
Filing Date:
June 18, 2014
Export Citation:
Assignee:
QUALCOMM INC (US)
International Classes:
H03K23/42; H03K5/15
Domestic Patent References:
| WO2005117266A1 | 2005-12-08 |
Foreign References:
| US7573305B1 | 2009-08-11 | |||
| US20090256596A1 | 2009-10-15 | |||
| US20100111244A1 | 2010-05-06 |
Attorney, Agent or Firm:
BINDSEIL, James, J. et al. (LLP1717 K Street, N.w, Washington DC, US)
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