Field of the Invention

The present invention to relates to applying bias voltages to the access transistors in the cells depending on the determined data retention time data of the cells in dynamic random access memory (hereinafter will be referred to as DRAM) structures in an adaptive manner or not applying them at all.

Background of the Invention

Today, DRAM manufacturers set pre-determined refresh times for DRAMs during production at the factory level resulting with retention times according to the DRAM characteristics. Refresh time can be expressed as a predetermined time during which the capacitor used to retain data in the cells is recharged periodically before being fully discharged, and retention time can be expressed as the amount of time that a cell can retain data without being refreshed.

Some of the cells in a DRAM are weaker than other cells. A cell being weak means that the said cell loses the data it retains in a shorter period of time than the other cells, in other words, the retention time is shorter. Some cells can retain the data therein for a longer period of time. These changes in the retention time are caused by production-related differences. Even if the proportion of the weak cells is low, the frequency of refresh for all DRAM cells is determined by the manufacturers according to the retention time value of these weak cells. In this case, unnecessary refreshing is performed for many cells (even for the non-weak cells) since the refresh operation is carried out for the weakest cell. In addition to the power consumption required for the refresh operation, the requests for these cells have to be held as read and write operations cannot be performed during the refresh operation. Therefore, a decrease in the total number of refresh operations or in the frequency of refresh is needed in order to reduce power consumption as wells as enhancing performance.

Summary and Objects of the Invention The object of the present invention is to provide a DRAM which requires a frequency of refresh that is 70-80% (varies according to the applied bias voltage) less than the basic-design DRAMs in the state of the art, and thus wherein power consumption and the likelihood of read/write operations clashing with refresh operation are reduced.

Another object of the present invention is to provide a DRAM having 60-70% lower static energy dissipation thanks to the reduced leakage currents of the transistors in its cells. Another object of the present invention is to provide a DRAM having cells that are more resistant to effects such as electromagnetic interaction thanks to increasing the threshold values of the weak cells.

Detailed Description of the Invention

A DRAM structure having an adaptive body bias voltage developed to fulfill the objects of the present invention is illustrated in the accompanying figures, in which: Figure 1 is a schematic view of the DRAM structure.

Figure 2 is a schematic view of a cell. The components shown in the figures are each given reference numbers as follows:

1. DRAM structure with adaptive body bias voltage

2. Basic DRAM

21. Cell

211. Access Transistor

212. Bias line

3. Control unit

4. Multiplexer

5. Bias driver

G. Ground

B. Bias voltage

The DRAM with adaptive body bias voltage (1) of the present invention essentially comprises

• at least one basic DRAM (2) including at least one row consisting of a plurality of cells (21),

• an access transistor (211) which forms each cell (21) together with a capacitor,

• a bias line (212) to which the body terminals of each of the access transistors (211) in the cells (21) forming a row are connected,

• at least one multiplexer (4) for controlling whether a predetermined value of bias voltage (B) will be supplied to the bias line (212),

• at least one control unit (3) which is connected to the selection input of the multiplexer (4),

• at least one bias driver (5) through which the bias voltage (B), which, according to the data coming from the control unit (3) to the multiplexer (4), will be received from at least one of the data inputs of the multiplexer and will be transmitted to the bias line (212), passes. In the DRAM structure with adaptive body bias voltage (1) of the present invention, there is provided a basic DRAM (2) for retaining the data, program code and similar information required for performing the functions of the processor in the electronic device in which it is used. There are cells (21) in the basic DRAM (2). Each cell (21) is comprised of a capacitor and an access transistor (211). The cells (21), which are comprised of a capacitor and an access transistor (211), are lined up to form rows and the rows build up one under the other to form the structure of the basic DRAM (2).

The threshold voltage of an access transistor (211) in a cell (21) can be adjusted by changing the difference between the source voltage and the body voltage of that access transistor (211). As the threshold voltage of a transistor (211) increases, that transistor (211) starts to leak less, and hence, the cell (21) wherein the said transistor (211) is located can retain the data stored therein for a longer period of time, that is to say, the retention time increases. By applying different threshold voltage to the transistor (211), the retention time of the transistor (211) can be increased thereby reducing leakage.

In the DRAM structure (1) of the present invention, the control unit (3) decides whether the bias voltage (B) will be applied to a row and thus to each access transistor (211) in the cells (21) forming the row, and this decision is applied by means of the multiplexer (4). In the preferred embodiment of the present invention, when making the said decision, the retention time data determined for a row is used. The retention time for a row is determined according to the weakest cell (21) in that row. The row is labelled by the interval to which the retention time of the row corresponds among the predetermined preferred number of retention time intervals. As an exemplary embodiment for this process that is called classification, when a time of 128 milliseconds is desired to be divided into two intervals, two intervals are determined as 0-64 ms and 64-128 ms. This means that the cells (21) can be refreshed every 64 ms or every 128 ms taking into account the retention times that vary due to production-related differences. For example, since a cell (21) having a retention time of 64 ms to 128 ms (e.g. 75 ms) should be refreshed before expiration of the said time, it is labelled in the 0-64 ms interval among the determined retention time intervals. A cell (21) having a retention time greater than 128 ms is labelled in the 64-128 ms interval. However, even if a row contains cells (21) labeled in the higher retention time interval, it receives the same label with its cell (21) labeled in the shortest retention time interval. The control unit (3) is adapted to provide the required voltage from the selection input according to the label data of the rows. When the retention time label of a row is evaluated as weak by the control unit (3), the control unit (3) generates the required selection input to transmit the bias voltage (B) from the output of the multiplexer (4) to the bias line (212). When the retention time label of a row is not evaluated as weak by the control unit (3), the control unit (3) generates a selection input such that the bias voltage (B) will not be transmitted from the output of the multiplexer (4) to the bias line (212). For a row evaluated as weak, the bias voltage (B) is received from at least one of the data inputs of the multiplexer (4) and transmitted to the bias line (212) via the bias driver (5) according to the voltage coming from the selection input of the control unit (3). The bias voltage (B) coming from the bias line (212) is applied to the body terminal of the access transistor (211) of each cell (21) in the said row. When bias voltage (B) is applied to the access transistor (211), the threshold voltage of that transistor (211) increases. With the increase of the threshold voltage, the leakage of the transistor (211) decreases, therefore the retention time of the cell (21), in which the said transistor (211) is located, increases. If the retention time of the said cell (21) ascends to a higher level interval, in the next classification process, the said cell (21) is henceforth labeled according to the interval it has reached. Thus, if all weak cells (21) in a row are labeled in a higher level interval, the refresh time can be chosen to be longer for that row and the refresh frequency is reduced.

In one embodiment of the invention, the access transistors (211) in each row are preferably connected to a single bias line (212). The access transistors (211) in each row are connected to a same and single bias line (212). The bias voltage (B) is applied to the access transistors (211) in each row through a single and same bias line (212).

The bias voltage (B) coming from the bias line (212) is applied to the body terminal of the access transistor (211) of each cell (21) in the said row. When bias voltage (B) is applied to the access transistor (211), the threshold voltage of that transistor (211) increases.

In the preferred embodiment of the invention, labeling and classification of the cells (21) and rows are performed in the step of booting the basic DRAM. After the bias voltage (B) is applied to the rows, the reclassification process is performed again in the booting step.

In a preferred embodiment of the invention, the control unit (3) is adapted to use the access pattern of the cells (21) to decide whether to apply bias voltage (B) to a row.