Technical field

The present invention relates to field-programmable gate array, FPGA, devices. In particular the invention relates to artificial intelligence, Al, accelerator FPGA devices and other hardware for performing autonomous driving calculations.

Background

Field-programmable gate arrays, FPGAs, have long been used to build system prototypes of application-specific integrated circuits, ASICs, and system-on-a-chip, SoC, devices. FPGAs are versatile components comprising large amounts of configurable logic and are a natural choice for building and testing the new integrated circuits, ICs. As IC designs have grown in both size and complexity, FPGAs have also grown to provide ever-increasing and corresponding numbers of logical gates. FPGA prototypes enables development and testing of systems more flexibly and may grant software developers earlier access to more functionally advanced hardware platforms. FPGAs may be used in artificial intelligence, Al, accelerators that typically need to perform very large volumes of calculations. For autonomous driving applications, especially when relying on stored electrical energy for propulsion as in an electric vehicle, EV, this may become an issue as FPGAs generally consume more power than ASICs. Typical figures for Al accelerator FPGA power consumption may be in the range 1-5 kW. As such, an autonomous EVs range could be substantially reduced, e.g. by 5-10%. The higher power consumption may be attributed to more logical gates and more wiring between logical gates being required in an FPGA. The higher power consumption may additionally lead to larger thermal losses. Increases in temperature may additionally cause thermal runway effects as current leakage increases through the conventional Si transistors, commonly used in FPGAs. There is thus need for improvements within the technical field. Summary of the invention

An object of the inventor has been to solve or at least mitigate some of the above issues in the state of the art.

According to a first aspect a field-programmable gate array, FPGA, device is provided. The FPGA device may be an artificial intelligence, Al, accelerator FPGA device. The FPGA device may be configured for, or suitable for, performing autonomous driving calculations. The FPGA device comprises a configurable logic block, CLB. The CLB comprises one logic inverter. The logic inverter comprises at least one high-electron-mobility transistor, FIEMT. Each FIEMT comprises an Al _y Ga _y -iN layer structure, wherein 0 < y < 1 , and a GaN layer structure.

The term “field-programmable gate array device” (and its corresponding acronym) should be understood as referring to a device based on or to a significant extent comprising an FPGA. It should not be interpreted as limiting the disclosure to just an FPGA as such.

The term “logic inverter” should be understood as a device that may convert a high input signal to a, relatively to the input signal, lower output signal and vice versa.

The term “high-electron-mobility transistor” (and its corresponding acronym) should be understood as a semiconductor device comprising at least two layer structures of different energy band gaps forming a common heterojunction interface enabling substantially two-dimensional electron transport. This interface may be understood to enable the forming of a so- called two-dimensional electron gas, 2DEG. A FIEMT may alternatively be referred to as a heterojunction field-effect transistor, FIFET.

Autonomous driving applications may require massive amounts of related calculations to be performed and data to be processed. This may be especially relevant for machine learning or Al based autonomous driving. The inventor has realized that nitride FIEMTs may be beneficial for use in autonomous driving FPGA devices. This is due to their overall improved efficiency. Nitride FIEMTs, e.g. FIEMTs comprising a GaN and AIGaN layer structure interface generally provide higher voltage/current operation, higher switching frequencies, and less energy loss, compared to legacy metal-oxide- semiconductor field-effect transistors, MOSFETs. The energy efficiency aspect of nitride HEMTs would in particular provide advantages for autonomous driving FPGA devices onboard EVs such that a larger extent of the energy stored in e.g. a battery may be used for propelling the vehicle instead of performing autonomous driving calculations. Furthermore, the reduced energy losses may lead to less waste heat being produced. As such less effort may be put into addressing the waste heat build-up by e.g. cooling means. Furthermore, waste less heat may be preferable for safety aspects in regard to EV batteries.

The logic inverter may be a cascode inverter. The logic inverter may comprise at least two HEMTs. Each HEMT may comprise an Al _y Ga _y -iN layer structure, and a GaN layer structure.

The term “cascode” may refer to a two-stage circuit or amplifier with a common-source/emitter stage and a common-gate/base stage. The two stages usually comprise one transistor each.

The use of a cascode inverter setup may provide greater isolation of the inverter input and output signals by reducing reverse transmission of current as there is no direct coupling from the output node to the input node. Furthermore, the negative consequences of the Miller effect, such as e.g. an increase of the input capacitance, may be mitigated, thus increasing the inverter bandwidth.

The logic inverter may comprise at least one pull-up transistor.

The introduction of a pull-up transistor, e.g. being a part of a pull-up network, may improve inverter operation by providing a reliable way to produce high output signal levels.

The CLB may be a K-input CLB.

The term “K-input” should be understood to refer to a CLB comprising any integer K number of inputs.

The CLB may be configured for learning function mapping.

The FPGA device may further comprise a parallel shift register.

The FPGA device may further comprise a memory block. As such instructions and data may be stored by the FPGA device. The FPGA device may further comprise a programmable input/output, I/O, block.

By the programmable IO block the FPGA device may be accessed by other devices, e.g. a central processing unit, CPU, in order to program the FPGA device.

The CLB, the parallel shift register, the memory block, and the programmable I/O block may all be formed on a same Si substrate.

By forming all components on the same substrate, the FPGA device may be miniaturized, and less material may be wasted. As Si IC fabrication methods are readily available to the skilled person, production complexity may be reduced. Si is also relatively abundant to the alternatives such as bulk nitride materials. Furthermore, less individual discrete components may need to be integrated post their individual formation.

The FPGA device may further comprise an interconnect configured to electrically connect at least two of the CLB, the parallel shift register, the memory block, and the programmable I/O block.

The term “interconnect” may be understood as an electrical/conductive interconnect able to transmit a current and hold a voltage potential.

The Al _y Ga _y -iN layer structures of each HEMT may be integrally formed. The GaN layer structures of each HEMT may be integrally formed.

As such, the same layer structures may be used for forming a plurality of HEMTs.

Each HEMT may further comprise a Si substrate. Each HEMT may further comprise a crystal transition layer structure arranged on the Si substrate.

By basing the HEMTs on a Si substrate, production and integration with other circuits and devices on a same substrate may be made less complex and more material efficient in line with the already provided advantages of using Si as a substrate. The crystal transition layer may be advantageous in adjusting the material structure or crystal lattice to requirements for creating high quality nitride materials and material interfaces. The Al _y Ga _y -iN layer structure may be arranged on the crystal transition layer structure. The GaN layer structure may be arranged on the Al _y Ga _y -iN layer structure.

The GaN layer structure may be arranged on the crystal transition layer structure. The Al _y Ga _y -iN layer structure may be arranged on the GaN layer structure.

The crystal transition layer may comprise a plurality of vertical nanowire structures perpendicularly arranged on the Si substrate. The crystal transition layer may further comprise an Al _x Ga _x -i N layer structure, wherein 0 < x < 1 . The Al _x Ga _x -i N layer structure may be arranged to vertically and laterally enclose the vertical nanowire structures.

Such a crystal transition layer may be used to provide a good material and lattice conditions for epitaxial forming/growth of high-quality nitride layer structures. The crystal transition layer may also be made thinner and thus less material intensive than conventional buffer layer-based approaches to achieve higher quality nitride layer structures.

According to a second aspect an Al processing system is provided.

The system comprises an FPGA device according to the first aspect. The system further comprises a sensor, providing an analog sensor output signal. The system further comprises an analog-to-digital converter, ADC, for processing said sensor output signal. The system further comprises a digital- to-analog converter, DAC, for regulating said sensor. A memory block of the FPGA device holds stored instructions for operating the Al processing system.

In addition to the advantages provided by the first aspect, such a system may be advantageously employed to perform autonomous driving calculations. The system may feature the ADC and/or the DAC comprise nitride FIEMTs and hence, further integration of devices may be achieved.

The system may essentially be integrated as a SoC.

A further scope of applicability of the present invention will become apparent from the detailed description given below. Flowever, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the scope of the invention will become apparent to those skilled in the art from this detailed description.

Hence, it is to be understood that this invention is not limited to the particular component parts of the device described or acts of the methods described as such device and method may vary. It is also to be understood that the terminology used herein is for purpose of describing particular embodiments only and is not intended to be limiting.

It must be noted that, as used in the specification and the appended claims, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements unless the context clearly dictates otherwise. Thus, for example, reference to "a unit" or "the unit" may include several devices, and the like. Furthermore, the words "comprising", “including”, “containing” and similar wordings does not exclude other elements or steps.

Brief description of the drawings

The above and other aspects of the present invention will, in the following, be described in more detail with reference to appended figures. The figures should not be considered limiting; instead they should be considered for explaining and understanding purposes.

As illustrated in the figures, the sizes of layers and regions may be exaggerated for illustrative purposes and, thus, are provided to illustrate the general structures. Like reference numerals refer to like elements throughout.

Fig 1 shows a schematic block diagram of an FPGA device.

Fig. 2 shows a schematic block diagram of an FPGA device comprising a plurality of CLBs.

Fig. 3 shows a schematic block diagram of an exemplary CLB.

Fig. 4 shows an exemplary flip-flop logic circuit.

Fig. 5a shows a logic inverter comprising one HEMT.

Fig. 5b shows a logic inverter comprising one HEMT and one pull-up transistor.

Fig. 6a shows a cascode inverter comprising two HEMTs. Fig. 6b shows a cascode inverter comprising two HEMTs and two pull- up transistors.

Fig. 7 shows a cross-sectional view of semiconductor layer structures and a HEMT.

Fig. 8 shows schematic block diagram of an Al processing system. Detailed description

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which currently preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided for thoroughness and completeness, and to fully convey the scope of the invention to the skilled person.

Fig. 1 shows an FPGA device 100. The FPGA device 100 may be an Al accelerator FPGA device. The FPGA device 100 may be configured for performing autonomous driving calculations. The FPGA device 100 may be suitable for performing autonomous driving calculations. The autonomous driving calculations may comprise performing machine learning, or Al assisted calculations relating to the operation of an autonomous vehicle. The vehicle may be an autonomous road vehicle. The vehicle may be partially or fully autonomous in its operation. The vehicle may be an EV with an electrochemical battery and electrical propulsion means e.g. an electric motor. The FPGA device 100 may be installed in the vehicle. The FPGA device 100 may additionally find utility in a data center installation.

The FPGA device 100 comprises a CLB 110. The FPGA device 100 may comprise a plurality of CLBs 110 as shown in Fig. 2. The CLB 110 may be a K-input CLB, wherein K represents an integer corresponding to the number of inputs of the CLB 110. The integer K may e.g. be 3, 4, or 8. The CLB 110 may be configured for learning function mapping. The CLB 110 may be exemplified by Fig. 3. The CLB 110 comprises at least one logic inverter 120. Fig. 3 shows the CLB comprising a look-up-table, LUT, input stage with four inputs, IN. This may be understood as K=4. The LUT output is shown to connect to an input, referred to as input D, of a flip-flop, FF. The FF may be a so-called D-type FF. The LUT output line is also shown to connect to a multiplexer MUX. The FF may receive a further input in the form of a clock signal, CLK. The FF may provide an output, referred to as output Q. The output Q is shown to connect to the MUX. The MUX may produce the CLB output signal, OUT.

Fig. 4 shows a logic circuit diagram of a D-type FF. As mentioned in connection with Fig. 3, the FF may comprise a D input and a CLK input. The FF may comprise a Q output and a Q' output. The Q' output may be considered the inverse or complementing logical output to the Q output. E.g. if Q corresponds to a binary 1 , Q' would correspond to a binary 0 and vice versa. The FF is shown to comprise a logic inverter 120 at the D input line. This logic inverter 120 may be considered the logic inverter of the CLB 110. The FF is further shown to comprise four logical NOT-AND, NAND, gates.

The NAND gates may comprise a logical AND gate and a logical inverter 120.

The logic inverter 120 comprises at least one HEMT 130. Fig. 5a shows the logic inverter 120 comprising one HEMT 130. The HEMT130 is shown to be arranged as a pull-down network of the logic inverter 120. The logic inverter 120 comprises a resistor as its pull-up network, between the output line, VOUT, and the VDD node. The resistor may be realized as an always-on transistor with a specific on state resistance, thus corresponding to that of a discrete resistor. The logic inverter of Fig. 5a is a so-called 1 transistor, 1T, inverter. A high signal/binary 1 on the input line, VIN, connected to the HEMTs 130 gate node, may result in a low signal/binary 0 at VOUT and vice versa. The 1T inverter may see a direct current path between the VDD node and the ground node, GND, via the HEMTs 130 drain and source nodes, when the HEMTs 130 channel is open.

Fig. 5b shows the logic inverter 120 comprising a pull-up transistor 230 instead of, as in Fig. 5a, having a resistor act as a pull-up network. The pull- up transistor 230 may be connected with its gate/base node to the input line, VIN. The pull-up transistor 230 may be connected with its source/emitter and drain/collector nodes connected to either one of the VDD and VOUT nodes. Such a logic inverter 120 may feature reduced leakage current from the VDD node to the GND node as the direct current path there between is only open for a short time during switching. Rise and fall times on the VOUT node may also be shorter due to this. The voltage at the VOUT node may also be larger than without a pull-up transistor 230.

The pull-up transistor 230 may be a p-type MOSFET transistor, PMOS. The pull-up transistor 230 may be a Si-based transistor. The pull-up transistor 230 may be a Ge-based transistor. The pull-up transistor 230 may be a GaN/nitride-based transistor. The pull-up transistor 230 may be carbon nanotube-based transistor. The pull-up transistor 230 may be a high-hole- mobility transistor, HHMT. The pull-up transistor 230 may be a tunnel field- effect transistor, TFET. The pull-up transistor 230 may be a bipolar junction transistor, BJT.

Fig. 6a shows he logic inverter 120 being a cascode inverter. The logic inverter 120 may comprise at least two FIEMTs 130. The two FIEMTs 130 are shown to be arranged as a pull-down network of the logic inverter 120. A resistor is shown to form the pull-up network in a similar way to Fig. 5a. The top FIEMT 130 is shown to be connected at its gate node to the VDD node.

As such, the top FIEMT 130 may be considered as an always-on transistor. The top FIEMT 130 may additionally be considered a common gate stage of the cascode configured logic inverter 120. The bottom FIEMT 130 is shown to be connected at its gate node to the input line, VIN. The bottom FIEMT 130 may be considered as a common source stage of the cascode configured logic inverter 120.

Fig. 6b shows the cascode configured logic inverter 120 comprising two pull-up transistors 230 as part of its pull-up network instead of the single resistor of Fig. 6a. The top pull-up transistor 230 is shown to be connected with its gate node to the input line, VIN. The top pull-up transistor 230 may be considered a common source/emitter stage of the cascode configured logic inverter 120. The bottom pull-up transistor 230 is shown to be connected with its gate node to the GND node. The bottom pull-up transistor 230 may be considered an always-on transistor. The bottom pull-up transistor 230 may additionally be considered a common gate stage of the cascode configured logic inverter 120.

The HEMT 130 comprises an Al _y Ga _y -iN layer structure 380, wherein 0 < y < 1 . The HEMT 130 also comprises a GaN layer structure 382. These layer structure features are not shown in Fig.1 but are instead shown in Fig.

7, to which the reader’s attention is now directed. Fig. 7 shows a cross- sectional view of a HEMT 130 comprising the aforementioned layer structures 380, 382. Fig. 7 shows the HEMT 130 being based on a Si substrate 384.

The Si substrate 384 may be a substantially monocrystalline Si structure. The Si substrate 384 may be a Si substrate with a <111 > Miller index. The Si substrate 384 may be a Si wafer formed with the Czochralski process. The Si substrate 384 may be a chip or die from a larger Si wafer.

Fig. 7 further shows a crystal transition structure 386 being formed on the Si substrate 384. The crystal transition structure 286 is shown to comprise a plurality of vertical nanowire structures 388. The vertical nanowire structures 388 are further shown to be perpendicularly arranged on the Si substrate 384. The vertical nanowire structures 388 may comprise GaN or AIN or AIGaN.

Fig. 7 also shows the crystal transition structure 286 comprising an Al _x Ga _x -iN layer structure 389, wherein 0 < x < 1 . The Al _x Ga _x -iN layer structure 389 is shown to be arranged to vertically and laterally enclose the vertical nanowire structures 388. The Al _x Ga _x -i N layer structure 389 may comprise a plurality of sublayers. The plurality of sublayers may feature a gradually decreasing value for the variable x.

Such a structure as well as HEMTs based thereon is further described in the European Patent Application EP19215267, which is hereby incorporated by reference. Figures 1-6 and their corresponding passages in the text provide context and alternatives to the layer structures and HEMTs 130 of the present disclosure. Figures 7-12 and their corresponding passages in the text should be understood as context about methods for producing the same layer structures and HEMTs 130. The summary of the referenced application provides context on technical advantages and definitions of the language therein. The wording “crystal transition structure” does not appear in the referenced application but may be understood as referring to the combined structure comprising every layer and structure intermediate to the “Si substrate” (reference 102) and the “third semiconductor layer” (reference 130).

Fig. 7 shows the Al _y Ga _y -iN layer structure 380 being arranged on the crystal transition structure 386 and the GaN layer structure 382 being arranged on the Al _y Ga _y -iN layer structure 380. Alternatively, the GaN layer structure 382 may be arranged on the crystal transition structure 386 and the Al _y Ga _y -iN layer structure 380 may be arranged on the GaN layer structure 382.

Fig. 7 further shows source S, drain D, and gate G contacts of the FIEMT 130. The drain contact D should not be confused with the input D of the flip-flop in either Fig. 3 or Fig. 4. The contacts source, drain, and gate contacts may be formed by metal material. The source and drain contacts may comprise Ti, Al, Cu, Ni, and/or Au. The source and drain contacts may comprise compounds or alloys such as e.g. AICu. The gate contact may, in addition to the materials mentioned for the source and drain contacts, also or alternatively comprise Pd and/or Au. As for the source and drain contacts compounds and alloys are also options for the gate contact.

In the case that the logic inverter 120 is a cascode inverter each of the logic inverters 120 comprises at least two FIEMTs 130 comprising an AlyGay- iN layer structure 380, and a GaN layer structure 382. The Al _y Ga _y -iN layer structures 380 of each FIEMT 130 of the logic inverter 120, cascode or otherwise configured, may be integrally formed. The GaN layer structures 382 of each FIEMT 130 of the logic inverter 120, cascode or otherwise configured, may be integrally formed. The layer structures 380, 382 of FIEMTs 130 may be separated by passivation/spacer structures to prevent the individual FIEMTs 130 unintentionally affecting each other during operation.

Fig. 1 shows that the FPGA device 100 may comprise a parallel shift register 140. The parallel shift register 140 may be a part of the CLB 110. The parallel shift register 140 may be considered to correspond to a LUT of the CLB 110 e.g. as the one shown in Fig. 3. Fig. 1 further shows that the FPGA device 100 may comprise a memory block 150. The memory block 150 may be a part of the CLB 110.

The memory block 150 may comprise a random-access memory, RAM. The RAM may be static, SRAM, or dynamic, DRAM. Other alternative memory solutions may include e.g. magnetoresistive RAM, MRAM.

Fig. 1 and Fig. 3 further shows that the FPGA device 100 may comprise programmable I/O block(s) 160. Fig. 1 further shows that the FPGA device 100 may comprise an interconnect 170. The interconnect 170 may be configured to electrically connect at least two of the CLB 110, the parallel shift register 140, the memory block 150, and the programmable I/O block 160.

Fig. 3 shows the interconnect 170 electrically connecting an array of CLBs 110 and programmable I/O blocks 160.

The CLB 110, the parallel shift register 140, the memory block 150, and the programmable I/O block 160 may all be formed on a same Si substrate 384.

Fig. 8 shows an Al processing system 400. The Al processing system 400 is shown to comprise the FPGA device 100. The FPGA device 100 may comprise a memory block 150. The memory block 150 may hold, or be configured to hold, stored instructions for operation the Al processing system 400.

The Al processing system 400 is further shown to comprise a sensor 410. The sensor may provide, or be configured to provide, an analog sensor output signal. The sensor 410 may be e.g. a camera or stereo camera setup comprising image sensors, a radar/laser/acoustic range finder/object detection sensor, a microphone, an accelerometer, a gyroscope, a temperature sensor, a barometer, a motion sensor, a radio frequency sensor, etc.

The Al processing system 400 is further shown to comprise an ADC 420. The ADC 420 may be provided or configured for receiving the sensor output signal, from the sensor 410, and processing the sensor output signal.

In particular the ADC 420 may process the analog sensor output signal as to provide a corresponding digital signal to the FPGA device 100. The ADC 420 may be a microchip type ADC. An exemplary ADC 420 is further described in the European Patent Application EP19205265, which is hereby incorporated by reference. The block and circuit diagrams of Figures 1-2 and their corresponding passages in the text provide context to how the ADC 420 may be implemented. Figures 3- 5 and their corresponding passages in the text provide context on the layer structures and FIEMTs 130 of the present disclosure. In particular, the referenced application provides further context on integration of two FIEMTs 130 in close proximity. This may provide improvements to e.g. the cascode configured logical inverters 120 of the FPGA device 100 as overall device footprint may be minimized. The summary of the referenced application provides further context on technical advantages and definitions of the language therein.

The Al processing system 400 is further shown to comprise a DAC 430. The DAC 430 may be provided or configured for regulating the sensor 410. The DAC 430 may receive digital instructions from the FPGA device and provide a corresponding analog signal to the sensor 410. The DAC 430 may be a microchip type DAC.

Additionally, variations to the disclosed embodiments can be understood and effected by the skilled person in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.