BACKGROUND

Memory systems including an array of memory devices may be used in a variety of applications ranging from data storage to in-memory computation. In these systems, a single device or a collection of devices and circuits may define a single cell which may be connected together to form an array. Based on the properties of these memory cells, the memory may be used to store a data in a volatile or non-volatile form. Memory arrays like SRAM uses memory cells implemented with regular CMOS transistors and belong to the category of volatile memory. Non-volatile memory devices like resistive-RAMs, PCM, flash, etc may be used as a memory cell to implement a non-volatile memory array. Each memory cell may be configured to store a single or multiple bits of information and may be read from or written to multiple times using the peripheral circuitries designed and located around the memory array. The array of memory cells may also be used for applications other than storage like in-memory computation where array of memory cells may be used to perform mathematical operations such as dot-product or vector-by-matrix multiplication using the data stored in memory cells. In such applications, the memory module may include some extra circuits like Analog-to- Digital Converter (ADC), Digital-to-Analog Converter (DAC), sense amplifier, current-to- voltage converter, etc. The memory array with NVM memory cells may include circuitries to generate and route high-voltage signals needed to program the NVM cells.

Arrays of memory devices as well as the peripheral circuits included in the memory system are often temperature sensitive meaning that the behavior of the system during reading data from the memory or writing data to the memory changes by the temperature. For memory arrays used for in-memory computation, changes in temperature may result in a change in the results of computation. This sensitivity of the memory system to temperature may affect and degrade the speed, precision of operation, power consumption and performance of the system. This happens mainly because the channel currents of the CMOS transistors in subthreshold, linear (triode) and saturation may change significantly from temperature to temperature. While linear or saturation operation points has less sensitivity to temperature, subthreshold operation regime is very sensitive to temperature. Using output circuitries like sense amplifiers, ADCs, etc. to compensate the temperature effects may result in a bulky, inefficient memory system with high power consumption. On the other side, compensating temperature effects at the memory cell level may avoid all the aforementioned problems. Current comparators are circuits that determines whether one current is larger than another current. Current comparators have many applications in a variety of analog circuits. By moving toward more advanced technology nodes in CMOS process, designing accurate, fast and efficient current comparators gets harder and harder for several reasons. First, current amplitudes are getting smaller and smaller. For example, in the circuit operating in subthreshold, the amplitude of currents can be in a nA region. Secondly, with the reduction of current amplitudes, the signal to noise ratio will be also reduced making the design of accurate current comparators a challenging problem. Thirdly, due to the increasing device-to-device variations in submicron processes, an acceptable level of accuracy may only be reached by using bulky circuits. Finally, high-speed current comparators require high-gain amplifiers, which are very power hungry.

Current comparators may work by first subtracting the two currents to be compared from one another using Kirchhoff s current law and then converting the subtraction result into voltage using current-to-voltage converter circuits. In this configuration, the sign and/or amplitude of the output voltage of the current-to-voltage converter may show whether the first current is larger than the second one or vice versa. However, using conventional current-to- voltage converters with resistive feedback is very sensitive to noise and device-to-device mismatch. Moreover, for large current differences, the current-to-voltage converter circuit may go into saturation reducing the speed of the circuit dramatically. To avoid saturation, the driving capability of the converter may be increased which may result in higher power consumption.

Matrix of memory devices arranged in rows and columns may form a memory system used in variety of applications ranging from data storage to in-memory computation. Each memory device or cell may be a single element like a resistor, resistive memory, flash transistor, etc. or may include a combination of elements like 1T-1R memory cells. Each memory cell may be used to store a single bit of information or it may be used to store analog (multibit) values. The memory array may be called non-volatile if a non-volatile memory device like resistive-RAMs, PCM, flash, etc. is used in the memory cells to store data. The memory array may include multiple peripheral circuitries to properly bias memory devices inside the memory array during programming, read and/or operation. Different memory device types may be biased differently compared to each other and in different modes of operation (e.g. program, read, operation). Provided biases may bias the memory devices in different operating modes. For example, flash of floating-gate memory devices may be used subthreshold, triode (linear) or saturation regime. The memory array may be configured to also a include programming circuits and methodology through which memory devices may be programmed with analog or digital values. The array of memory cells may also be used for applications other than storage like in-memory computation where array of memory cells may be used to perform mathematical operations such as dot-product or vector-by-matrix multiplication using the data stored in memory cells. In such applications, the memory module may include some extra circuits like Analog-to-Digital Converter (ADC), Digital-to-Analog Converter (DAC), sense amplifier, current-to-voltage converter, etc. The memory array with non-volatile memory (NVM) cells may include circuitries to generate and route high-voltage signals needed to program the NVM cells.

In memory arrays used for data storage and retrieval or in-memory processing, there may be a need to measure multiple currents in parallel or to convert multiple analog currents generated by the memory devices within the memory array to digital. When the number of currents to be measured becomes large, it may not be possible or efficient to use multiple large, high-power ADCs to convert currents into voltage. Moreover, circuits designed for measuring small analog currents in sub-micron technologies may be bulky and sensitive to mismatches, device-to-device variations, process variations, etc. which may affect the precision of conversion. In such cases, the dependency of a bitline’s voltage to the current being measured may be used to convert the analog current to digital using simpler circuits consuming less power and chip area while operating at higher speed.

Compared to regular and volatile memories like SRAM, non-volatile memory arrays have the advantage that they can retain their states for several years without the need for refreshing of states. However, in order to be able to use these memory arrays in any sort of applications, individual memory cells within the array need to be programmed with predetermined data. If the non-volatile memory (NVM) is used in digital applications, for example to store binary data, the NVM cells will be programmed to a binary state where each state will represent one of the binary values. The same memory array can also be used in another type of application known as in-memory computation used for the implementation of deep neural networks and machine learning algorithms in which each memory cell will store analog values corresponding to neural network parameters. In this case, the same exact device storing network parameters will later be used to perform analog in-memory computations such as vector-by -matrix multiplication, or dot-product. In any of these cases, analog or digital programming of NVM devices is usually done through the application of a sequence of narrow pulses (e.g. lOns-lOms) with amplitudes higher than those used for normal operation of the array (e.g. 3-12V for flash memory array and l-5v for resistive switching memory arrays). Depending on the structure and functionality of the device, these high-voltage pulses may be applied to a single or multiple terminals of the NVM cells with carefully adjusted timings. If NVM memory cells are arranged in rows and columns creating an array, these pulses may be applied to common rows and columns of the array which will be seen by all the cells connected to that rows or columns. Application of these high-voltage pulses may result in high currents passing through these NVM cells. Inability to limit this current properly may degrade the endurance of the device and lower the accuracy of analog programming of these memory cells. SUMMARY

In one embodiment, a memory system having a temperature effect compensation mechanism is provided. The memory system may include a plurality of memory cells, the memory cells being organized in an array having two or more rows of memory cells arranged horizontally and two or more columns of memory cells arranged vertically. The plurality of memory cells may have an operating temperature range. The memory system may also include a temperature-dependent biasing circuit, the temperature-dependent biasing circuit that is configured to reduce a biasing voltage to the plurality of memory cells when the temperature of the array is at or near an upper end of the operating temperature range and increase the biasing voltage to the plurality of memory cells when the temperature of the array is at or near a lower end of the operating temperature range.

In another embodiment, a system for comparing currents is provided. The system may include a subtractor that is configured to receive a plurality of current input signals and generate a single output current signal that is equal to a difference between the plurality of current input signals. The system may also include a current-to-voltage converter that is configured to receive the output current signal and convert it into an output voltage.

In another embodiment, a system with analog to digital converters is provided. The system may include a plurality of non-volatile memory cells that may be organized into an array having two or more rows of memory cells arranged horizontally and two or more columns of memory cells arranged vertically. The system may include a bitline electrically coupled to a column of memory cells vertically arranged in the array. The bitline may be configured to sum up the current produced by the memory cells in the column. The system may also include a digital-to-analog converter having an output that is electrically coupled to the bitline. The digital-to-analog converter may be configured to generate a current and add it through the output to the bitline. The system may further include a voltage comparator having an input that is electrically coupled to the bitline. The voltage comparator may be configured to measure a voltage on the bitline and compare it to a fixed voltage, and to stop the digital-to-analog converter from adding current to the bitline when the measured voltage exceeds the fixed voltage.

In another embodiment, a system for programming memory devices in an array is provided. The system may include a plurality of memory cells that are organized into an array having two or more rows of memory cells arranged horizontally and two or more columns of memory cells arranged vertically. The system may also include a current-compliance circuit that is electrically coupled to one or more memory cells in the plurality of memory cells. The current-compliance circuit may be configured to limit an amount of current supplied to the one or more memory cells during a programming phase of the one or more memory cells.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

FIG. 1 illustrates an example of a memory system for data storage application;

FIG. 2 illustrates an example of a memory system for in-memory computing application;

FIG. 3 illustrates an example of a memory system with individual temperature- dependent biasing circuit per each row;

FIG. 4 illustrates an example of a memory system with a temperature-dependent biasing circuit shared between multiple rows;

FIG. 5 illustrates an example of a memory system for in-memory computing application with input vectors applied to the temperature-dependent biasing circuits biasing memory cells within the memory array;

FIG. 6 illustrates an example of a memory system with supercell memory devices with individual temperature-dependent biasing circuit per each row;

FIG. 7 illustrates an example of a memory system with supercell memory devices with a temperature-dependent biasing circuit shared between multiple rows;

FIG. 8 illustrates an example of a memory system with supercell memory devices for in-memory computing application with input vectors applied to the temperature-dependent biasing circuits biasing memory cells within the memory array;

FIG. 9 illustrates an implementation example of temperature-dependent biasing circuits using flash transistors;

FIG. 10 illustrates an example of replacing flash transistor with two regular CMOS transistors; FIG. 11 illustrates an example of a current comparator system with assisting pullup and pulldown circuits;

FIG. 12 illustrates another circuit-level example of the current comparator system;

FIG. 13 illustrates an example of a memory system configured for reading device states; FIG. 14 illustrates an example of an ADC measuring the output currents of the memory system in read/operation mode;

FIG. 15 illustrates an example of a memory system consisting of resistive RAM memory devices configured for reading device states;

FIG. 16 illustrates an example of ADCs measuring the output currents of the memory system with resistive RAM memory devices in read/operation mode;

FIG. 17 illustrates an example of a memory system consisting of flash or floating-gate memory devices configured for reading device states;

FIG. 18 illustrates an example of ADCs measuring the output currents of the memory system with flash or floating-gate memory devices in read/operation mode;

FIG. 19 is a flowchart of an example method for analog to digital converters for NVM arrays to read out the analog currents generated by the memory devices within the memory array during read or operation mode;

FIG. 20A illustrates an example environment in which current-compliance circuits may be implemented in NVM memory arrays;

FIG. 20B illustrates an example of a current-compliance circuit that may be implemented in the environment illustrated in FIG. 20A; and

FIG. 21 illustrates another example environment in which current-compliance circuits may be implemented in NVM memory arrays.

DETAILED DESCRIPTION

Embodiments of the invention relate to various systems and methods that can be used, for example, with flash memory arrays that have digital input and analog output or other memory arrays. Embodiments include methods and structures for temperature effect compensation in memory arrays. Other embodiments include current comparators for submicron processes. Other embodiments include analog-to-digital converters for non-volatile memory arrays used for in-memory computation with floating bitlines. Other embodiments include methods and structures for programming non-volatile memory arrays with automatic programming pulse amplitude adjustment using current-limiting circuits. These embodiments will be described in detail hereinafter. 1. TEMPERATURE EFFECT COMPENSATION IN MEMORY ARRAYS

One or more embodiments of the present disclosure may include a memory system including a matrix or array of volatile or non-volatile memory cells. The memory system may include some peripheral circuitries including but not limited to row and column decoders, sense amplifier, ADC, DAC, current to voltage converter, programming circuitry, biasing circuitry, charge pump, pulse generator, high-voltage and low-voltage routing circuitry, etc. The memory system may be configured to be used for data storage or in-memory computing applications. Each single cell or a set of cells may be used in the matrix of memory devices to store digital or analog (multibit) values. Writing to a single memory cell or a set of memory cells in parallel may be performed using a low-voltage and high-voltage peripheral circuitries like how it is done in regular memory arrays. In operation or read phase, the memory array may produce outputs proportional to the given inputs and the data stored in memory cells. In memory applications, inputs to the memory module may be the address and the read enabling signals while the output may be the contents of the memory cells on the row pointed by the address. For in-memory computation like vector-by-matrix multiplication, the inputs of the module may be the vector of analog or digital inputs and the outputs may be the vector of analog or digital outputs where each output may be proportional to all or a subset of input vector and the content of memory cells electrically coupled to that output.

In some embodiments, the memory system may include a temperature-dependent biasing circuit which may bias the memory cells during read or write operation to reduce or remove their sensitivity to temperature. The temperature-dependent biasing circuits may lower the biasing voltage in higher temperatures so the memory cells may produce a current similar or identical to the current they may produce at lower temperatures. The temperature-dependent biasing circuits may increase the biasing voltage in lower temperatures so the memory cells may produce a current similar or identical to the current they may produce at higher temperatures. In some embodiments, there may be one temperature-dependent biasing circuit per each row of the memory array. In some other embodiments, the temperature-dependent biasing circuit may be shared between multiple rows or all the rows of the memory array. Some embodiments may be configured so that the memory cells may accept two or more inputs. In these embodiments, one input may be connected to the temperature-dependent biasing circuit to minimize temperature impacts and the other input may be used to turn on or off the memory cell during read and write operation. For in-memory applications, each row may have its own temperature-dependent biasing circuit and analog inputs may be applied directly to the temperature-dependent biasing circuit. The temperature-dependent biasing circuits may convert these analog currents to voltages which may later be converted back to current with the memory cells inside the memory array. The current produced by the memory cells may be proportional to the amplitude of the analog input current and the state of that memory cell. In some embodiments, pairs of memory cells may share a common source lines forming a supercell configuration to reduce layout area of the memory array.

In some embodiments, the system may include a matrix of memory cells arranged in rows and columns. Each memory cell may be a single device or element like a transistor or may consist of multiple circuit elements. There may be a programming peripheral circuitry like charge pump, pulse generator, row and column decoders, etc. next to the memory system allowing individual or parallel programming of memory cells. Each memory cell may be used to store digital or analog values and may operate in subthreshold, linear or saturation regime. The memory system may also include a row and column decoder to address a single or multiple devices within the memory array for reading or writing purpose. The same or different decoders may be used to route input vector to proper rows of the memory array and route the proper memory array outputs/columns to output vectors.

In some embodiments, the memory cells may include a non-volatile device like a flash transistor, floating-gate transistor, Sonos transistor, resistive RAM, PCM, etc. In some other embodiments, the memory cell may only include volatile or non-programmable elements like NMOS and PMOS transistors.

In some embodiments, the memory devices may have four (e.g. Gate, Drain, Source and substrate), or five (e.g. Gate, Drain, Source, Erase Gate, Substrate), or six (e.g. Gate, Control Gate, Drain, Source, Erase Gate, Substrate) terminals.

The memory system may be used for data storage application. The row decoder may select a row of a memory array based on a given address. The column decoder may select a single or multiple of memory cells on the selected row. In a write phase, the low-voltage and high-voltage programming circuitries, charge pump, etc. may be used to program the selected devices with digital or analog (multibit) values following a device programming procedure/scheme. In a read phase, the selected devices may produce a current proportional to their programmed states. These currents may be routed to the Analog-to-Digital Converter (ADC) or a sense amplifier to be converted to the digital representation of the data stored in the selected memory devices. Based on the type of devices used in memory cells, there may be a need for a biasing circuitry to bias different terminals of the selected and unselected devices with different voltages. Different set of voltages may be used to bias the selected and unselected devices within the memory array during the read and write operations. The current generated by the selected devices during the read or write phase may depend on temperature. The amount of dependency of these currents to temperature may depend on their characteristics, biasing condition and operating region.

In some other embodiments, the memory system may be used for in-memory computing or similar applications. The row and column decoders may respectively select a set of rows and columns of the memory array to be involved in in-memory computation. In an operation phase, a set of digital or analog input signals may be applied to the selected rows. Devices selected by the row and column decoders receiving input signals may produce a current proportional to their programmed states and the input signal they are electrically coupled to. These currents may be summed up on the columns of the memory array and may be routed to the Analog-to- Digital Converter (ADC), Current-to-voltage converter or a sense amplifier to be converted to digital or some other analog representations. Based on the type of devices used in memory cells, there may be a need for a biasing circuitry to bias different terminals of the selected and unselected devices with different voltages. Different sets of voltages may be used to bias the selected and unselected devices within the memory array during the read and write operations. The current generated by the selected devices during the read or write phase may depend on temperature. The amount of dependency of these currents to temperature may depend on their characteristics, biasing condition and operating region.

A memory array using non-volatile memory devices may be programmed by first selecting a single or multiple devices using the row and column decoders and then applying a sequence of programming and/or erasure pulses until the states of the selected devices reach predetermined states at specific read condition. Amplitude and pulse width of the programming and erasure pulses may depend on device characteristics. Terminals of the selected and unselected devices within the memory array may need to be biased with proper voltages for proper operation.

Unselected devices within the memory array may be biased with specific voltages to prevent them from generating current during the read operation or to get programmed during the write operation performed on selected devices.

In some embodiments, pairs of memory devices may form a supercell structure where they share their source terminals to reduce layout area of the memory array.

In some embodiments, there may be a temperature-dependent biasing circuit generating a biasing voltage which may vary by the temperature. The circuit may generate lower voltages or currents in higher temperatures and higher voltages or currents in lower temperatures. The circuit may include devices like regular or flash transistors with temperature-dependent characteristics and I-V curves to sense a temperature. At different temperatures, these devices may have different characteristics like generating different currents at the same biasing condition allowing the temperature-dependent biasing circuit to generate a temperature- dependent biases. The operating temperature ranges of the temperature-dependent biasing circuit may be similar to the operating temperature ranges of the temperature-sensitive devices used to construct the temperature-dependent biasing circuit. The temperature-dependent biasing circuit may be used to bias the memory cells within the memory array to reduce or remove their temperature sensitivity. At higher temperatures, the temperature-dependent biasing circuit may bias the memory cells inside the memory array with lower voltage to reduce the current they may generate in that high temperature. The biasing voltage may change by temperature in such a way that the currents generated by memory cells inside the memory array may have a negligible change with temperature.

In some embodiments, different rows or different set of rows of the memory array may be biased with a separate temperature-dependent biasing circuit.

In some other embodiments, the temperature-dependent biasing circuit may be used to convert the analog input current to a temperature-dependent voltage which may be used to bias the memory cells within the memory array. The memory cells may convert the biasing voltage back to current based on the amplitude of the biasing voltage and the state they have been programmed to. Usage of temperature-dependent biasing circuits to drive the memory array may reduce or remove the temperature sensitivity of the computations like in-memory computations performed in the memory array.

The temperature-dependent biasing circuit may include but not limited to a simple diode-connected regular CMOS or flash transistor converting input current to voltage. The temperature-dependent biasing circuit may use a memory device similar to the memory cells used in the memory array to deliver better temperature insensitivity to memory array. The biasing conditions of the temperature-dependent biasing circuit may be selected to be as close as possible to the biasing conditions of the memory cells within the memory array to minimize the mismatch and to reach a temperature independent design.

In some embodiments, the temperature-dependent biasing circuit may also include a programming circuit to program the devices to states similar to states where memory cells may be programmed to.

These and other embodiments of the present disclosure will be explained with reference to the accompanying figures. In the figures, features with like numbers indicate like structure and function unless described otherwise. FIG. 1 illustrates an example of a memory system 100 with temperature-dependent biasing circuits 104. Like regular memory architectures, the memory system may include a row decoder 102 and a column decoder 101, low- and high-voltage biasing and device programming circuits 103, and an array of memory devices or cells 105. The memory cells may be accesses for a read or write operation using memory interface signals like data and address buses, Wr/Rdn, and Chip Select (CS). The address bus may select a set of devices on a specific row of the memory array to be read or written to. Read or write operation may be selected using the Wr/Rdn signal. During the read operation, data may be delivered on the data bus while during the write operation, data bus may send the data to the memory. The memory system may include a programming circuit and mechanism to program a single or a set of memory cells with the given data. Each memory cell may be used to store digital or analog (multibit) data. The memory system may be used for data storage and retrieval applications. Memory devices within the memory array 105 may be of any type (flash or regular transistor, resistive RAM, PCM, etc.) and may be biased and operate in different operating regions like subthreshold, linear (triode) or saturation. Different biasing conditions may be used for memory devices when the memory array is in read, write or idle phase.

In some embodiments, the memory system 100 may also include a temperature- dependent biasing circuit or module 104. The temperature-dependent biasing circuit 104 may generate biasing voltages or currents which may vary by temperature. The generated biasing voltages or currents may be used to bias the memory devices or cells within the memory array 105 to reduce or remove their sensitivity to temperature variations. In some other embodiments, the temperature-dependent biasing circuits 104 may be implemented by the same memory cells or devices as those used in memory array to have similar temperature dependency which may help reducing the dependency of memory array 105 to temperature. Reducing the temperature dependency of the memory array 105 may increase the speed and the operating temperature range of the memory system 100 while reducing the power consumption and chip area.

FIG. 2 illustrates an example of a memory system 200 having an array of memory devices 205 used for in-memory computation. Similar to memory systems used for data storage application shown in FIG. 1, the memory system of FIG. 2 may include decoders, biasing and programming circuits 203, a row decoder/DAC/switch network 202 and an I-V converter/ ADC/column decoder/sense amplifier 201, through which a single or a set of devices within the memory array 205 may be selected for a read or a write operation. Memory devices within the memory array 205 may be programmed with digital or analog (multibit) value and may produce a current proportional to their programmed state when activated. Memory devices within the memory array 205 may be of any type (flash or regular transistor, resistive RAM, PCM, etc.) and may be biased and operate in different operating regions like subthreshold, linear (triode) or saturation. Different biasing conditions may be used for memory devices when the memory array 205 is in read, write or idle phase.

In some embodiments, the memory array 205 may be used for in-memory computation. A vector of analog or digital input signals [xl, x2, ... , xn] may be applied to the selected rows of the memory array using the low- and/or high-voltage row decoder/D AC/s witch network 202. The row decoder/D AC/switch network 202 may also include a Digital-to-Analog Converter (DAC) to convert the digital inputs to their corresponding analog representation (i.e. analog current or voltage signal) before being applied to the memory array 205. Each memory device may receive a digital or an analog signal and may produce a current with an amplitude proportional to the amplitude of the received signal, the state it is programmed to and the condition it is biased to. The currents generated by selected memory devices may be added together column-wise controlled by the I-V converter/ ADC/column decoder/sense amplifier 201. The I-V converter/ ADC/column decoder/sense amplifier 201 may also include Analog- to-Digital Converters (ADC), current-to-voltage converter, or sense amplifier to measure the sum-of-currents output signals and convert them to the required representation (e.g. voltage, digital, etc.). The output vector [yl, y2, ... , ym] may be result of the computation performed in the memory array.

In some embodiments, the memory system 200 of FIG. 2 may be used to perform in memory computations like vector by matrix multiplication, matrix by matrix multiplication or vector by vector dot product multiplication. In some other embodiments, the memory system 200 of FIG. 2 may be used for analog data storage and retrieval.

In some embodiments, proper biasing voltages or currents may be applied to unselected devices within the memory array 205 to prevent them from producing currents during the operation phase or being programmed during the programming phase.

In some embodiments, the memory system 200 of FIG. 2 may be configured to also include a temperature-dependent biasing circuit 204 which may be used to bias the selected or unselected memory cells in the memory array 205 during read and/or write operation. The biasing condition generated by the temperature-dependent biasing circuit 204 may be such a way that it may reduce or remove the dependency of the current generated by memory cells to temperature. The temperature-dependent biasing circuit 204 may be the sole biasing circuit of memory cells or may be used in conjunction with other circuits to bias memory cells. If at higher temperatures the memory cell produces higher currents when activated, the temperature- dependent biasing circuit may generate lower biasing voltage to reduce the memory cell’s current. The process may be reversed at lower temperatures.

In some other embodiments, the vector of analog or digital input signals may be applied to the temperature-dependent biasing circuits 204 rather than the memory array 205. In these embodiments, the temperature-dependent biasing circuit may convert input signals to a biasing voltage with an amplitude proportional to the amplitude of the input signal which may then be used to bias the memory cells in the memory array 205.

To minimize the dependency of memory cells within the memory array 205 to temperature during the read and write operation, the behavior (e.g. devices specs, channel width and length, device type) and the biasing condition of the temperature-dependent biasing circuit 204 may be kept as similar as possible to the behavior and biasing conditions of the memory cells within the array 205 to minimize the mismatch between the two devices or circuits.

In some embodiments, where memory cells used to create the memory array 105 (FIG. 1) or 205 (FIG. 2) has more than one control gate, one gate may be used as a switch to turn on or off the memory cell while the other one may be used to bias the memory cell with the voltage generated by the temperature-dependent biasing circuit 104 (FIG. 1) or 204 (FIG. 2). The gates used for biasing and for switching may be interchangeable.

In some embodiments where memory cells are floating gate or flash transistors with two control gates (e.g. word-line and control-gate), the biasing voltage generated by the temperature-dependent biasing circuit may be applied to the gate which has the most overlap with the floating gate storing the charge and has the most impact on the current generated by the cell. In other embodiments, the gate receiving the biasing voltage from the temperature- dependent biasing circuit may be the one closest to the source terminal.

FIG. 3 illustrates an example of an array of non-volatile memory devices which may be used for memory storage and retrieval or in-memory computing application. The memory array may include flash or floating-gate memory devices 300a, 300b...300m and memory devices 301a, 301b...300m arranged in rows and columns forming a matrix or array of memory devices. For example, as shown in FIG. 3, memory devices 300a, 300b...300m are in a first row and memory devices 301a, 301b... 301m are in a second row. Each memory device may have multiple terminals including source-lines (SLs), main gates (WLs), control gates (CGs), erase gates, inaccessible floating-gates, and a drain or bitlines (BLs). With regard to the configuration shown in FIG. 3, memory devices 300a, 300b...300m have terminals including a source-line 303a (also labeled SL1), a main gate 305a (also labeled WL1), an erase gate (not shown), and an inaccessible floating-gate 302a. Memory devices 301a, 301b...301m have terminals including a source-line 303b (also labeled SL2), a main gate 305b (also labeled WL2), an erase gate (not shown), and an inaccessible floating-gate 302b. Memory devices 300a and 301a include a drain or bitline 306a (also labeled BL1). Memory devices 300b and 301b include a drain or bitline 306b (also labeled BL2). Memory devices 300m and 301m include a drain or bitline 306m (also labeled BLm).

Main gates, source-lines, control gates, and erase gates of devices located on the same row of the memory array may be electrically coupled to each other. For example, main gates 305a of memory devices 300a, 300b...300m may be electrically coupled to each other since these memory devices are in the same row, while main gates 305b of memory devices 301a, 301b...301m may be electrically coupled to each other since these memory devices are in the same row. Similarly, source-line 303a of memory devices 300a, 300b...300m may be electrically coupled to each other since these memory devices are in the same row, while source-line 303b of memory devices 301a, 301b...301m may be electrically coupled to each other since these memory devices are in the same row. In addition, control gate 304a of memory devices 300a, 300b... 300m may be electrically coupled to each other since these memory devices are in the same row, while control gate 304b of memory devices 301a, 301b...301m may be electrically coupled to each other since these memory devices are in the same row. Drains of memory devices located on the same columns of the memory array may be electrically coupled together forming bitlines. For example, memory devices 300a and 301a share a bitline 306a (also labeled BL1) since these memory devices are in the same column. Similarly, memory devices 300b and 301b share a bitline 306b (also labeled BL2) since these memory devices are in the same column. In addition, memory devices 300m and 301m share a bitline 306m (also labeled BLm) since these memory devices are in the same column. There may be no restriction on the number of rows or columns of the memory array.

The memory system of FIG. 3 may include peripheral column circuitries 307 and peripheral row circuitries 308. Peripheral column circuitries 307 may include a low- and/or high-voltage column decoder and peripheral row circuitries 308 may include a low- and/or high-voltage row decoder , which may be used to select a single or a set of devices within the memory array for read, write or computing operation. Peripheral column and row circuitries 307 and 308 may also include biasing and programming peripheral circuits, which may be used to properly bias different terminals of selected and unselected memory devices during read, write, operation phases and generate necessary programming and erasure pulses to program or erase flash transistors. Erasure or programming of flash transistors in the memory array may be performed one at a time or in parallel. Each memory device 300a, b... m and 301a, b... m may be used to store a digital (binary) or analog (multibit) value.

In some embodiments, control gates 304a of memory devices 300a, b... m may be biased during read or write operations with a voltage bias 315a (also labeled Vbiasl) generated by a voltage-dependent biasing circuit 312a, which is connected to that row. Similarly, control gates 304b of memory devices 301a, b... m may be biased during read or write operations with a voltage bias 315b (also labeled Vbias2) generated by a voltage-dependent biasing circuit 312b, which is connected to that row. All voltage-dependent biasing circuits may be electrically coupled to their corresponding control gate lines by closing SW2 switches 313a and 313b. SW2 switches 313a and 313b may allow the memory array to be disconnected from the voltage- dependent biasing circuits 312a and 312b and the control gates 304a and 304b of memory devices 300 and 301 to be biased with other biases generated by peripheral row circuitry 308.

The voltage-dependent biasing circuit 312a may be configured to receive a fixed input current 314a (also labeled Ibiasl) and convert it linearly or nonlinearly to voltage 315a (Vbiasl). Similarly, the voltage-dependent biasing circuit 312b may be configured to receive a fixed input current 314b (also labeled Ibias2) and convert it linearly or nonlinearly to voltage 315b (Vbias2). In some embodiments, the fixed input current 314a (Ibiasl) applied to voltage- dependent biasing circuit 312a may be the same as or different than (but similar to) the fixed input current 314b (Ibias2) applied to voltage-dependent biasing circuit 312b. The difference between Vbiasl and Vbias2 may be compensated when memory devices 300 and 301 are being programmed using the same Vbias voltages.

With an increase in temperature, the voltage-dependent biasing circuits 312a and 312b may convert the fixed input currents 314a and 314b to slightly lower Vbias voltages. Lowering the voltage on control gates 304a and 304b of the memory devices 300 and 301 may reduce the current they may generate at that particular temperature when their main gates 305a and 305b are enabled. By designing voltage-dependent biasing circuits 312a and 312b with characteristics and behavior similar to memory devices 300 and 301, the current of memory devices 300 and 301 may remain unchanged at different temperatures.

Memory devices at particular row(s) of the memory array may be selected or enabled to generate currents by enabling their main gates. Applying 0 volts to a main gate corresponding to binary number 0 may prevent the memory device from producing the current it is programmed to generate. Applying a non-zero voltage to a main gate corresponding to binary number 1 may enable the memory device to produce the current it is programmed to generate. In some embodiments where the memory architecture of FIG. 3 is used for data storage and retrieval applications, switches 310a and 310b (also labeled SW1) may remain off and a particular row of devices may be enabled by setting the main gate of that row to 1 and keeping the main gates of the remaining rows at 0. This may be done by a row decoder within peripheral row circuitry 308.

In some other embodiments where the memory architecture of FIG. 3 is used for in memory computing applications, main gate voltages may be provided not by the row decoder, but through S W 1 switches 310a and 310b. The elements of the vector of analog or digital input signals may directly be applied to the main gates 305a and 305b of the memory array during the operation phase. Each input signal may be applied to one or multiple main gates. When input signals are digital, they may be stored in registers 311a and 311b. These digital inputs stored in registers may be applied to the main gates 305a and 305b of the memory array one bit at a time while control gates 304a and 304b are biased with the voltage-dependent biasing circuits 312a and 312b. When the computations on least significant bits of all input signals are finished, the next least significant bits of digital input signals may be applied together to the main gates. Those memory devices which receive 1 at their main gate may produce current proportional to the voltage applied to their control gate, states they are programmed to and the biasing voltages applied to other terminals. Those memory devices which receive 0 at their main gate may produce zero or near zero current. Rows of the memory array not used in the computation may be deselected by setting their main gates to zero. Data stored in registers may be shifted to the right by one step after the least significant bits are applied to the memory array.

In some embodiments, at each time step, n>l bits of each digital input signal may be applied to n different rows (main gates) of the memory array to speed up the computation. States to which the memory devices are programmed to in these n different rows of the memory array may be different but proportional to each other. For example, if the weights stored in memory devices located on the first row (out of n) of the memory array to which the leas significant bit is applied be [wl, w2, ... , wm], the weights stored on the memory devices located on the second row (out of n) to which the next least significant bit is applied may be [2*wl, 2*w2, ... , 2*wm]

In some embodiments, the memory system of FIG. 3 may be used to implement the computations used in neural networks and deep neural networks like dot product, vector by matrix multiplication and matrix by matrix multiplication. In these applications, network parameters or weights may be stored in memory devices in analog or digital form. Memory devices located on the same column of the memory array may share the same bitline 306a, b... m. Currents generated by these memory devices when enabled may be summed up on the bitlines. Bitlines 306a, b... m may be biased by the column decoders and biasing circuits 307 and 309, respectively. The accumulative analog currents on bitlines may be measured and converted into voltage or digital using the current-to-voltage converter, sense amplifiers, or analog to digital converter circuit 309 for further processing. Circuits 307 and 309 may also be used to bias bitlines of unselected devices on the selected row(s) to prevent them from being programmed.

In some embodiments, the amplitude of the fixed input current 314a (Ibiasl) may be similar to the amplitudes of currents that memory devices 300a, b... m may generate while in read or operation mode. Changes in fixed input current 314a (Ibiasl) amplitude may change the sensitivity of memory devices within the memory array to temperature with different amounts depending on the state the memory devices are programmed to. In some other embodiments, the generated voltage 315a (Vbiasl) may be such a way that put the memory devices 300a, b... m in subthreshold, linear (triode) or saturation region.

In some embodiments, control gates 304 and main gates 305 may be used interchangeably.

In some embodiments, the main gates 305, source-lines 303, control gates 304, erase gates, drains 306 of memory devices 300, 301 within the memory array may be routed horizontally or vertically connecting similar terminals of devices on the same rows or columns together. The routing configuration of terminals of different devices within the memory array may depend on the application of the memory system.

In some embodiments, different type of memory devices with similar or different number of terminals may be used in the architecture of FIG. 3. In other embodiments, a separate transistor may be placed in series with the memory device without control gate to allow the memory array implemented using these memory devices to reach temperature insensitivity. The gate of the added transistor may act as a control gate.

Reducing the sensitivity of the memory array to temperature may keep the range of currents produced on bitlines almost constant at different temperatures which may result in faster, denser and more power efficient memory or in-memory computing module. Using memory devices with longer channels may improve the accuracy of computation by reducing the sensitivity of memory device current to bitline voltage.

FIG. 4 illustrates a modified version of the system architecture shown in FIG. 3 where all control gates are biased with a single temperature-dependent biasing circuit. The shared temperature-dependent biasing circuit 401 may receive a single fixed current Ibias 402 and convert it to a voltage Vbias 403. Switches sw2 may be used to apply the generated Vbias to control gates of all selected rows of the memory array. The output of the temperature-dependent biasing circuit may have enough driving capability to be able to promptly charge or discharge the control gate lines of the memory array when needed.

FIG. 5 illustrates another modified version of the system architecture shown in FIG. 3 where the memory array is used for in-memory computation and analog input signals are applied to the memory array using the temperature-dependent biasing circuit. Rows of the memory array used for the implementation of the in-memory computation are enabled or selected by setting their main gate to 1 (504) using swl switches 505. Temperature-dependent biasing circuits 501 may convert the analog input current signals 502 to voltages used to drive the control gates of selected rows by closing sw2 switches 503. Activated memory devices withing the memory array may generate the current on their bitlines proportional to the voltage on their control gates and the state they are programmed to. Applying the analog input signals through the temperature-dependent biasing circuits rather than applying them directly to the array may significantly reduce the sensitivity of the array and the computation performed in it to temperature. Since unlike the architecture of FIG. 3 or FIG.4, here the voltages biasing control gates are not fixed at any particular temperature and may vary by the change in the input signal, the temperature-dependent biasing circuits 501 may have a high bandwidth and driving capability to deliver the input signals to all memory devices within the memory array with minimum delays.

In some embodiments, the analog input current signals 502 may be replaced by digital signals.

FIG. 6 illustrates another modified version of the system architecture shown in FIG. 3 where the sources of memory devices on two adjacent rows of the memory array are joined together (601) reducing the total number of source-lines by half. Each of memory devices sharing sources may form a structure called supercell. Using supercell memory devices to form the memory array may result in memory arrays with higher densities. The erase gates of memory devices forming supercells may also be shared (602). The functionality of memory devices and memory architecture may remain intact by replacing every two neighboring memory devices with a supercell structure.

FIG. 7 illustrates another modified version of the system architecture shown in FIG. 4 where the memory array may be implemented using supercell memory devices as explained in the system of FIG. 6. FIG. 8 illustrates another modified version of the system architecture shown in FIG. 5 where the memory array may be implemented using supercell memory devices as explained in the system of FIG. 6.

FIG. 9 illustrates an example of the voltage-dependent biasing circuit 900 implemented using a flash transistor 902. The flash transistor 902 may be the same type of device as used in memory array. The flash transistor 902 may have a diode-connected configuration implemented by connecting the control gate to bitline directly or indirectly (e.g. with a switch). The diode-connected circuit may receive an input current signal Ibias 901 and convert it to voltage Vbias 903 on the control gate terminal. Main gates, erase gates and source-lines of the flash transistor used to implement the voltage-dependent biasing circuit may be biased with the same voltages as used for the memory devices within the memory array to keep their biasing conditions as close as possible. The voltage applied to the main gate should be such a way that it keeps the flash transistor 902 enabled all the time.

In some embodiment, the voltage-dependent biasing circuit may include a buffer 904 to increasing the driving capability of the voltage generated on the control gate when connected to row(s) of the main memory array. Since the same generated voltages on control gates of 900 may be used to program memory devices inside the memory array, the buffer 904 may be designed with low accuracy to save power and chip area.

In some embodiments, the flash transistor 902 may be replaced by a set of flash transistors connected in parallel to reduce the mismatch between the behavior of the transistor 902 and the flash transistors within the main memory array. In this case, the input Ibias current 901 may be scaled by the number of flash transistors connected in parallel.

Main gate and control gate may be used interchangeably. When control gate has more overlap with the floating gate and is closer to the source-line, using control gate to generate voltage may be preferred.

Flash transistor or a set of flash transistors connected in parallel used to implement the system 900 may be separate and isolated transistors or may be a part of the main memory array (e.g. one column or one row of the memory array) configured to the structure shown in FIG. 9 using switches and wire routings to reduce chip area.

There may be a programming and biasing peripheral circuitry (not shown in FIG. 9) for programming the flash transistor(s) 902 and to bias the transistor(s) with proper voltages and currents during the read, write or operation phases.

Better temperature effect compensation may be achieved if the flash transistor(s) 902 is programmed to the state similar to the states of memory devices within the memory array and is biased with conditions similar to what flash transistors in the memory array are biased to. More complicated circuits may be used to force a fixed voltage on the drain of the flash transistor 902 to reduce the sensitivity of the whole memory system to temperature even more.

[0001] In some embodiments, the flash transistor 902 may be replaced with a regular CMOS transistor to convert the input current to voltage. The sizing and the characteristics of the regular transistor may be adjusted to make the behavior of the regular transistor as similar as possible to the behavior of flash transistors to increase the effectiveness of the implemented temperature compensation scheme.

FIG. 10 illustrates how the serial connection of two regular transistors Ml and M2 may be used to replace the flash transistor with 2 controlling gates. A gate closer to the source may be called CG (i.e. gate of transistor M2) and the gate closer to drain may be called WL (i.e. gate of transistor Ml). Transistors Ml and M2 may be sized differently to deliver specific behavior and to reduce the impact of WL on the behavior of the combined transistor (to reduce its functionality to a simple switch).

In some embodiments, the flash transistors of the memory array may be replaced by a 1T-1R memory structure. In these cases, the gate of the transistor in series with the resistive element may be biased with the temperature-dependent biasing circuit to reduce the sensitivity of the memory module to temperature.

2. CURRENT COMPARATORS FOR SUBMICRON PROCESSES

One or more embodiments of the present disclosure may include a system. The system may include a current subtractor, a current-to-voltage converter, a voltage comparator, an operational amplifier, and pulling up and pulling down devices or circuits. The current subtractor may be configured to subtract the two current signals from one another to generate a single current signal equal to the difference of the two input current signals. The current difference may pass through a current-to-voltage converter to be converted into voltage. The current-to-voltage converter may include an operational amplifier forcing a fixed virtual voltage to the output of the current subtractor module. In some embodiments, the current-to- voltage converter may have a capacitor instead of resistor as a feedback element to convert the current-to-voltage. Using the capacitor instead of resistor as a feedback element may filter out the noise and reduce the sensitivity of the converter to process-induced mismatches and variations.

The output of the current-to-voltage converter may be compared with a fixed predetermined voltage to determine which input current is larger than the other one (or whether the current difference is lower or higher than zero). In some embodiments, the described current comparator system may also include pulling-up and pulling-down devices or circuits to help lower the current entering the current-to-voltage converter or integrator to prevent it from getting into saturation. When the converter’s output is small, both of the pulling-up and pulling- down devices or circuits may be off allowing all the current to pass through the converter charging the feedback capacitor. As soon as the output of the convertor reaches the point that the output voltage comparator can make a reliable and correct decision about the sign of the current difference, based on the sign of the current charging the capacitor, one of the pulling- up and pulling-down devices or circuit may be turned on avoiding further currents to go into the converter/integrator keeping its operational amplifier away from the saturation region. Discharging the feedback capacitor may reset the converter to its initial state and ready for the next comparison.

The current comparator may be used in different applications including but not limited to analog-to-digital converters, analog in-memory computing architectures, etc.

In some embodiments, the system may include a current subtractor and a current-to- voltage converter. The current subtractor may accept two or more current signals with similar or different polarities and generate a single current signal equal to the subtraction of current signals with different polarities. The current subtractor circuit may be simple wires electrically coupled together or a more complicated circuit based on current adders and subtractors. In some embodiments, the polarity of some of the input currents may need to be reversed for example by using current mirror circuits. The resultant current of the subtractor circuit may be fed into the current-to-voltage converter. The current-to-voltage converter may accept the input current and convert it into a voltage signal where its amplitude and polarity may be proportional to the amplitude and polarity of the input current signal.

In some embodiments, the current-to-voltage converter may include an operational amplifier. The operational amplifier may help speeding up the current-to-voltage conversion.

In some embodiments, a current integrator circuit may be used as a current-to-voltage converter. Using an integrator for the current-to-voltage conversion may remove a noise from the current generated by the current subtractor module. Larger capacitive feedback elements may be used to remove noise better which may reduce the operating speed of the converter. In some other embodiments, an integrator may be used as a voltage-to-current converter to lower the sensitivity of the converter to device mismatch and device-to-device variations resulting in circuits with smaller layouts. An integrator used for current-to-voltage converter may include a capacitor resetting mechanism to discharge the feedback capacitor between conversions. In some other embodiments, the integration time of each conversion may be adjusted based on the amplitude of the incoming currents.

In some embodiments, the current-to-voltage converter may include an operational amplifier to provide a bias to the output stage of the current subtractor module or to the circuits sourcing currents to the current subtractor modules. Operational amplifiers with higher or lower gains may be used in the current-to-voltage converter to provide more or less accurate and stable biasing voltage for the current subtractor circuit. Operational amplifiers with higher or lower gains may consume more or less power during operation. In some embodiments where the current subtractor circuit or the circuits sourcing the input currents are not sensitive to the accuracy of the bias voltage generated by the current-to-voltage converter, an operational amplifier with low gain may be used to lower the power consumption.

Feedback devices used in the current-to-voltage converter may include a resistor, capacitor, FET transistor, or any other linear or nonlinear device. Capacitive feedbacks may be used in submicron processes with large mismatches and low signal to noise ratio.

The current comparator system may be configured to also include a voltage comparator circuit comparing the output voltage of the current-to-voltage converter with a predetermined voltage. The voltage comparator’s output may be equal to VDD (VSS) if the output of the current-to-voltage converter is higher than the predetermined voltage and may be equal to VSS (VDD) if the output of the current-to-voltage comparator is lower than the predetermined voltage. The voltage comparator may be used to convert the analog output of the converter to digital to be used in digital circuits. In some other embodiments, the voltage comparator may be used as a gain amplifier to amplify the output of the converter. The voltage comparator may include an operational amplifier.

In some embodiments, the voltage comparator may be removed from the current comparator system and the output of the current-to-voltage converter may be directly connected to and used in digital systems.

In some other embodiments, the current comparator system may be configured to include a pullup and pulldown circuits connected to the input of the current-to-voltage converter. The pullup and pulldown circuits may be used to limit the maximum amplitude of the current that may enter the current-to-voltage converter. When the current amplitude entering the current-to-voltage converter is large enough, the output voltage of the converter may be big enough for making an accurate comparison between the input currents. In this situation, allowing more current to enter the current-to-voltage converter may just increase the power consumption of the whole system. When the output voltage of the converter is higher or lower than some threshold values, one of the pullup or pulldown circuits may be turned on to limit the current entering the converter and preventing the converter’s output from getting larger or smaller anymore.

In some embodiments, the pullup and pulldown circuits may be used to reduce the power consumption of the current-to-voltage converter and the current comparator system.

In some other embodiments, the pullup and pulldown circuits may be used to speed up the current-to-voltage conversion process by preventing the output of the converter circuit to become too large or too small and entering the saturation region. The threshold voltages at which the pullup or pulldown circuits may turn on may depend on the levels of voltages that the voltage comparator or digital circuits can correctly recognize as low or high. Whenever the output voltage of the converter is small (compared to its idle voltage), both pullup and pulldown circuits will remain off allowing all the current generated by the current subtractor to enter the current-to-voltage converter.

The pullup and pulldown circuits may reduce the maximum current the current-to- voltage converter may need to provide resulting in lower chip area and lower power consumption. In some embodiments, the pullup and pulldown circuits may consume power only if they are turned on which may happen when only when the amplitude of the current entering the converter is large. The higher the output of the converter gets, the more the pullup or pulldown circuit may be turned on until their current may become equal to the current generated by the current subtractor module.

In some embodiments where the current integrator is used as a current-to-voltage converter, the pullup or pulldown circuits may be used to limit the maximum integral of current in a given period of time which may enter the current-to-voltage converter.

These and other embodiments of the present disclosure will be explained with reference to the accompanying figures. In the figures, features with like numbers indicate like structure and function unless described otherwise.

FIG. 11 illustrates an example of a current comparator system which may include a first current sources 1106a, a second current source 1106b, a current subtractor 1101, a current-to- voltage converter or a current integrator 1102, a voltage comparator 1104, a pullup circuit 1104 and a pulldown circuit 1105.

The current sources 1106a and 1106b may any circuit or device that may sink or source currents when activated. In some embodiments, more than two current sources may enter the current subtractor 1101. Alternatively, current sources 1106a and 1106b may include more than two current sources. For example, current source 1106a may include the sum of multiple currents with the same polarity. Current source 1106b may also include the sum of multiple currents with the same polarity. Current sources 1106a and 1106b may have opposite polarities.

Because the polarity and amplitude of the output of the current comparator system depends on the polarity and amplitude of the current entering the system, the system may work even with a single current source or when all the sources are sinking or sourcing currents. The currents 1106a and 1106b generated by the current source modules may enter the current subtractor circuit 1101 which may subtract the sum of sourcing currents from the sum of sinking currents or vice versa. The current subtractor module may include any type of current subtractor circuits like current mirror based subtractors. It may even be implemented by just electrically coupling the outputs of the current sources 1106 together. The current subtractor module 1101 may generate an output current with a polarity and amplitude proportional to the polarity and amplitude of resultant of all currents entered the subtractor. The generated current may enter the current-to-voltage converter module 1102 to be converted into voltage.

In some embodiments, the current-to-voltage converter module 1102 may receive a resultant current from the current subtractor 1101 and convert it to a voltage with an amplitude and polarity proportional to the received current. The current-to-voltage converter module 1102 may use a linear or nonlinear conversion. In some embodiments, the current-to-voltage converter 1102 may include an operational amplifier with a feedback element. The feedback element may be a simple resistor, capacitor, FET transistor, or a more complicated circuit. The operational amplifier used in the current-to-voltage converter may be used to bias the output stage of the current subtractor 1101 or input current sources 1106. For zero current, the output of the converter may be at a fixed voltage close to the middle of the swing range and determined by the biasing condition of the operational amplifier. By the increase of the amplitude of the entering current, the output voltage of the converter may become higher or lower than this middle voltage allowing the next stage to correctly decide about the polarity of the resultant current. In some embodiments, a current integrator may be used as a current-to-voltage converter 1102 to increase the accuracy of conversion and to reduce the chip area in submicron processes with large mismatches and device-to-device variations. The integrator may include a reset mechanism to discharge the integrator after each conversion.

In some embodiments, the current comparator system of FIG. 11 may include a voltage comparator or a gain amplifier 1104 to amplify the output voltage of the current-to-voltage converter 1102. The output of the voltage comparator 1104 may directly be connected to the input of a digital gate and used in digital systems (not shown in FIG. 11). In some embodiments, the voltage comparator may include an open-loop operational amplifier and may compare the output voltage of the current-to-voltage converter 1102 with a fixed predetermined value equal or close to the output voltage of the current-to-voltage converter module when its input current is zero. In some other embodiments, the voltage comparator 1104 may be removed and the output voltage of the current-to-voltage converter 1102 may be directly used instead.

The current comparator system of FIG. 11 may be configured to also include a pullup and pulldown circuits 1104 and 1105 to lower the power consumption of the system and the chip area. The pullup circuit 1104 may source a current to the node connecting the current subtractor 1101 to the current-to-voltage converter 1102 when activated. The amplitude of the current sourced by the pullup circuit 1104 to the common node may be proportional to the amplitude of the voltage applied to its control gate or terminal. When the amplitude of the voltage applied to the gate of the pullup circuit 1104 is lower than the threshold voltage, the pullup circuit 1104 may source zero or negligible current. By increasing the voltage on the control gate, the pullup circuit 1104 may generate more and more currents to the common node. The pulldown circuit 1105 may sink a current from the node connecting the current subtractor 1101 to the current-to-voltage converter 1102 when activated. The amplitude of the current sank by the pulldown circuit 1105 from the common node may be proportional to the amplitude of the voltage applied to its control gate or terminal. When the amplitude of the voltage applied to the gate of the pulldown circuit 1105 is higher than the threshold voltage, the pulldown circuit 1105 may sink zero or negligible current. By decreasing the voltage on the control gate, the pulldown circuit 1105 may generate more and more currents taken from the common node. The currents generated by either the pullup circuit 1104 or the pulldown circuit 1105 may reduce or completely stop the current from entering the current-to-voltage converter 1102. When the difference of the output voltage of the current-to-voltage converter 1102 and subsequently the output of the voltage comparator from their idle voltage is large enough that allows correct and fast detection of the polarity of the current entering the current-to-voltage converter 1102, the pullup circuit 1104 or the pulldown circuit 1105 may be turned on (based on the amplitude of the output voltage of the current-to-voltage converter) to prevent the output voltages of blocks 1102 and 1104 to further increase or decrease.

In some embodiments, the pullup circuit 1104 or the pulldown circuit 1105 may be a resistor, simple FET transistor or a more complicated circuit.

In some embodiments, the pullup circuit 1104 and the pulldown circuit 1105 may be controlled directly or indirectly by the output voltage of the current-to-voltage converter 1102 or the voltage comparator 1104. In some embodiments, the pullup circuit 1104 or the pulldown circuit 1105 may be used to prevent the current-to-voltage converter 1102 and/or the voltage comparator 1104 to enter the saturation which may reduce the response time and speed of the current comparator system.

In some embodiments, a big portion of the large currents generated by the current subtractor 1101 may be provided by either the pullup or pulldown circuits (depending the polarity of the output current of the current subtractor module 1101) rather than the current-to- voltage converter 1102 reducing the power consumption and chip area of the current-to-voltage converter while increasing its speed.

FIG. 12 illustrates an example of the current comparator circuit that may be implemented in the environment of FIG. 11, in accordance with at least one embodiment described in the present disclosure. In this configuration, one or multiple input currents 1210 and 1211 with equal or different polarities may be subtracted from one another using a simple current subtractor 1201 which may be implemented by electrical coupling of the outputs of the current sources 1210 and 1211. The current subtractor 1201 may subtract the sum of currents entering the subtractor 1201 from the sum of currents exiting the subtractor and generate a current equal to the subtraction of these two sets of currents. The current subtractor’s resultant current may exit the subtractor if the sum of currents entering the subtractor is larger than the currents exiting the subtractor and vice versa. The subtractor’s output current may enter a current integrator circuit which may include an operational amplifier 1202, a capacitive feedback element 1209, integrator discharging mechanism 1207.

In some embodiments, the capacitor 1209 may first be discharged by the activation of reset control signal 1207 forcing the output voltage of the operational amplifier to its idle voltage Vbias 1203. Vbias may be a voltage between VSS and VDD and may be close to the middle of the voltage range between VSS and VDD. In some embodiments, the bias voltage 1208 with a voltage value of Vbias may be applied to terminals of the capacitor 1209 to increase the speed of the resetting or capacitor discharging process. The reset control signal 1207 may be deactivate afterward allowing the capacitor 1209 to be charged entering the current integrator (i.e. the output current of the current subtractor).

If the current charging the capacitor is entering the integrator, the output voltage of the operational amplifier may gradually move from Vbias toward VSS with the speed proportional to the capacitance of the feedback capacitor 1209 and the amplitude of the current. If the current charging the capacitor is exiting the integrator, the output voltage of the operational amplifier may gradually move from Vbias toward VDD. If the output voltage of the operational amplifier 1202 gets too close to VSS or VDD, the amplifier may get into saturation resulting in slower operation and loosing the feedback which forces Vbias to the negative terminal of the operational amplifier. In some embodiments, the feedback capacitor 1209 may be reset preventing the operational amplifier 1202 from entering saturation.

In some embodiments, there may be a pullup NMOS transistor 1205 with a threshold voltage of Vthn and its gate connected to the output of the operational amplifier 1202 or the voltage comparator, its source to the input of the integrator and its drain to the voltage like VDD which is higher than Vbias. whenever the output voltage of the operational amplifier 1102 while charging the capacitor gets higher than the Vbias+Vthn, the NMOS transistor 1205 may gradually start turning on and sourcing current to the input of the integrator. The current generated by the pullup transistor 1205 may reduce the current entering the integrator till the current entering the integrator may become equal to zero. Having zero current entering the integrator may stop the output voltage of the integrator 1202 to increase further preventing it from entering the saturation. In some embodiments, a resistor R1 may be placed in between the source terminal of transistor Ml and the input of the integrator to adjust the voltage at which the transistor Ml may start to turn on.

In some other embodiments, there may be a pulldown PMOS transistor 1204 with a threshold voltage of Vthp and its gate connected to the output of the operational amplifier 1202 or the voltage comparator, its source to the input of the integrator and its drain to the voltage like VSS which is lower than Vbias. whenever the output voltage of the operational amplifier 1102 while charging the capacitor gets lower than the Vbias-Vthp, the PMOS transistor 1204 may gradually start turning on and sinking current from the input of the integrator. The current generated by the pulldown transistor 1204 may reduce the current entering the integrator till the current entering the integrator may become equal to zero. Having zero current entering the integrator may stop the output voltage of the integrator 1202 to reduce further preventing it from entering the saturation. In some embodiments, a resistor R2 may be placed in between the source terminal of transistor M2 and the input of the integrator to adjust the voltage at which the transistor M2 may start to turn on.

In some other embodiments, the feedback capacitor 1209 may be replaced with a resistor or a FET transistor, or a PMOS and NMOS transistors connected together in parallel, or a more complicated circuit. The reset mechanism 1207 and 1208 may be removed if the current-to-voltage converter is not a current integrator.

In some other embodiments, the operational amplifier 1202 wit ha feedback element may be used to also bias the circuits generating the input currents 1210 and 1211 with a Vbias voltage applied to the positive terminal of the operational amplifier 1202. In some other embodiments, there may be a voltage comparator or an open-loop gain amplifier (not shown in FIG. 12) connected to the output of the operational amplifier 1202 comparing its output with a fixed voltage equal or close to Vbias amplifying the output of the integrator. The output of the integrator or the voltage comparator may be directly or indirectly used in other analog or digital circuits.

In some embodiments, the pullup and pulldown circuits may be used to prevent the operational amplifier 1202 from entering the saturation which may result in the negative terminal of the operational amplifier to have a voltage other than the Vbias. Any change in the voltage of the negative terminal of the operational amplifier may change the biasing condition of the input current sourcing circuits 1210 and 1211 which may also change the amplitudes of the currents entering the current comparator system.

The pullup and pulldown transistors Ml and M2 may be resized carefully so they can provide the maximum current of 11-12 or 12-11.

In some embodiments, the exact value and the accuracy or the feedback capacitor may not be important since the comparator may just need to detect the sign of the current entering the integrator.

When comparing large currents, a resistive feedback element may be used instead of capacitor to increase the speed of the current comparator system. When dealing with small and noisy currents, a large capacitor may be used as a feedback element to filter out the noise.

In some embodiments, the pullup and pulldown transistors may be replaced with other circuits with similar functionalities.

3. ANALOG-TO-DIGITAL CONVERTERS FOR NON-VOLATILE

MEMORY ARRAYS USED FOR IN-MEMORY COMPUTATION WITH FLOATING BITLINES

One or more embodiments of the present disclosure may include a memory system including a matrix of non-volatile memory cells. Each memory cell may be a single element like a flash or floating-gate transistor or may consist of multiple elements creating more complicated structures like 1T-1R (one transistor, one resistive RAM). Binary or analog (multibit) values may be stored in each memory cells. Like other memory system, the memory array may be surrounded by other peripheral circuitries required for proper functionality of the memory system during, read, write or program, or operation modes. These peripheral circuits may include but are not limited to row and column decoders, sense amplifier, ADC, DAC, current to voltage converter, programming circuitry, biasing circuitry, charge pump, pulse generator, high-voltage and low-voltage routing circuitry, etc. The memory system may be used for data storage and retrieval application or may be used for more advanced applications like in-memory computation. During write or programming phase, single or multiple devices may be programmed to particular states by applying a single or a sequence of programming pulses. The programming pulses may have short or long duration and may have large or small amplitudes depending on the type of the memory cells used to create the memory arrays. During programming, proper voltages may be needed to be applied to other terminals of the memory devices. In read or operation mode, single or multiple memory devices in a single row or in multiple rows within the memory array may be activated or selected. Selected memory devices may produce a current proportional to the input signals applied to them and the states they are programmed to. The generated currents may then be summed up on the bitline wires which then may be measured and converted to digital for further processing. In memory application, multiple devices on a single row may be selected while in in-memory applications, like vector- by -matrix multiplication multiple, rows may be selected to be involved in the computation.

In some embodiments and during the programming of memory devices, the current state of the memory device may first be measured by biasing it with signals used during the read phase. In the read mode, that terminal of the memory cell electrically coupled with a bitline may be biased by a voltage Vbias used for device reading or for in-memory computation. If the current state of the device is not close enough to the target current, the memory system may be switched to the programming or write state and a single or a sequence of the pulses may be applied to the device to bring its state closer to the target state. The memory array may then be switched back to the read mode again to check the closeness of the device state to the target state. This process may be repeated until the maximum number of programming pulses is applied or the device state gets close enough to the target state. Now a memory device programmed to generate a current equal to Itarget when switched to read or operation mode may generate this current if and only if the voltage Vbias is applied to its bitline. This property may be used to simplify the ADC circuit used to measure and convert the bitline currents into digital.

In some embodiments, after programming all memory devices with target states, the memory array may be configured to be used in read or operation mode. In read or operation mode, multiple devices may be enabled or selected and may receive input signals. Activated memory devices may produce currents proportional to the received inputs and the states they are programmed to. Unselected devices may remain inactive producing zero or negligible currents. To measure the current generated by the selected memory devices and summed up on the bitlines, a current-output Digital-to-Analog Converter (DAC) connected to the bitline (BL) may start generating currents ranging from 0 to Imax where Imax may be the maximum current which may appear on the BL. The generated current may pass through the selected memory devices resulting in the increase of BL voltage. The BL voltage may reach a Vbias voltage if and only if the current generated by the DAC is equal to the sum of the currents generated by the selected memory devices. Therefore, a comparator comparing the BL voltage with Vbias may be used to notify the time the DAC current is equal to the sum of currents generated by memory devices and to stop the DAC from increasing its current further. The input digital code of the DAC circuit resulting in this current may be the digital representation of the sum of currents generated by memory devices. The proposed methodology of measuring analog currents in NVM arrays may have low power consumption and area due to the lack of any high- gain amplifier and may have very low sensitivity to device mismatch or process variations. Using long-channel memory devices may reduce the sensitivity to device mismatch or process variations even further.

In some embodiments, the system may include an array of memory devices arranged in rows and columns. Each memory cell may include a single or multiple non-volatile memory devices and may consist of multiple elements forming a complex structure. Some or all terminals of the memory devices located on a same row may be electrically coupled to each other. Some or all terminals of the devices located on the same column of the memory array may be electrically coupled together forming the bitlines of the memory. Currents of the activated memory devices located on the same column may be added up together and appear on the common bitline. There may be peripheral circuitries around the main memory to enable proper functionality of the memory array in write or programming, read or operation phase. These peripheral circuitries may include but not limited to charge pump, pulse generator, highl and low-voltage row and column decoders, biasing circuits, etc. These peripheral circuitries may be used to select a single or multiple devices in the memory array and read from or write to them one at a time or in parallel. Each memory device may operate in different regimes like subthreshold, triode (linear) or saturation in the case of flash or floating-gate devices. The NVM devices may be used to store analog (multibit) or binary values. The memory system may be used in variety of different applications like data storage and retrieval or in-memory computing. Rows and column decoders may route a vector of input signals to proper rows of the memory array and route bitlines of memory array to proper outputs.

In some embodiments, the memory cells may include a non-volatile device like a flash transistor, floating-gate transistor, Sonos transistor, resistive RAM, PCM, etc. In some embodiments, the memory devices may have four (e.g. Gate, Drain, Source and substrate), or five (e.g. Gate, Drain, Source, Erase Gate, Substrate), or six (e.g. Gate, Control Gate, Drain, Source, Erase Gate, Substrate) terminals.

In some embodiments, a single or a set of memory devices may be selected to be programmed through a row and column decoders. A single or a sequence of programming pulses may be applied to the selected devices to program them to the desired state or to bring their state closer to the desired state. The pulse duration and the amplitude of the programming pulses may depend on the type of NVM device used as memory device. After each or a set of programming pulses, the memory array may be switched to the read or operation mode where the new states of the memory devices may be checked to see whether they have reached close enough to the desired states. In the read or operation mode, the selected NVM devices may be biased with the read biases and the bitlines may be biased with a read voltage Vbias. Each selected memory device may produce a current proportional to its biasing condition, applied input signal, voltage on the bitline, and the current state of the device. If the produced current of a particular device is close enough to the desired current, the programming may be stopped. Otherwise the procedure may be repeated until the stopping conditions are met. Terminals of the selected and unselected devices within the memory array may need to be biased with proper voltages in programming mode.

In some embodiments, proper voltages may be applied to terminals of the unselected memory devices in the memory array to prevent them from getting programmed when the array is in the programming mode or to prevent them from generating any noticeable current when the array is in the read or operation mode.

In some embodiments, the memory array may be used for data storage and retrieval application. In this application, the row decoder may activate multiple devices on a specific row and the selected devices may produce currents on their corresponding bitlines proportional to the state they have been programmed to. In some other embodiments, the memory array may be used for in-memory application. The row decoder or other circuitry may apply a vector of analog or digital input signals to the selected rows of the memory array. Memory devices receiving these input signals may produce currents on their corresponding bitlines proportional to the amplitude or width of the received input signals and their programmed states. Currents of different devices connected to the same bitline may be summed up on the bitlines. Based on the type of devices used in memory cells, there may be a need for a biasing circuitry to bias different terminals of the selected and unselected devices with different voltages. Different sets of voltages may be used to bias the selected and unselected devices within the memory array during the read and write operations.

In some embodiments, pairs of memory devices may form a supercell structure where they share their source terminals to reduce layout area of the memory array.

In some embodiments, the memory system may also include a Current Measuring System (CMS) which may receive an analog input current from the bitline it is connected to and convert that analog signal into its corresponding digital representation. The CMS may act as an ADC. The CMS may include a current-output DAC and a comparator. Each bitline of the memory array may be connected to a separate CMS circuit converting analog currents generated by memory devices on the bitlines to their digital representation in parallel. The CMS may work at different precisions and therefore different speeds determined mainly by the precision of the internal DAC.

When inputs are applied to the selected memory devices within the memory array, the bitlines may be left unbiased by connecting the output of the DACs to their corresponding bitlines. Unbiasing bitlines may prevent selected memory devices from generating any current. Each bitline is also connected to the input of the voltage comparator which may compare the bitline voltage with a Vbias voltage (i.e. a voltage on the bitline during the read phase of programming). To measure the currents on each bitline at operation mode, the DAC may start generating analog currents which may pass through selected memory devices connected to the same bitline. By the increase of the current generated by the DAC, the voltage on the bitline may rise. When the voltage on the bitline reaches Vbias, the comparator’s output may switch indicating that the current generated by the DAC is equal to the sum of currents of selected devices in read mode (i.e. when bitlines are biased with a fixed Vbias voltage). The switching of the comparator may stop the DAC’s current from increasing more and the last input digital signal applied to the input of the DAC and resulted in the switching of the comparator’s output may be the digital representation of the bitline current (result of the conversion from analog to digital).

In some embodiments, NVM devices which their currents have less sensitivity to the bitline voltage may be used to reach faster and more accurate analog to digital conversion of bitline current.

In some embodiments, in memory arrays using flash or floating-gate memory devices, transistors with longer channels may be used to reduce the dependency of channel current to bitline voltage. In some other embodiments, in memory arrays using flash or floating-gate memory devices, transistors may be biased in subthreshold to reduce the dependency of channel current to bitline voltage.

In some other embodiments, in memory arrays using flash or floating-gate memory devices, transistors may be programmed to states close to fully programmed to reduce the dependency of channel current to bitline voltage.

In some embodiments, reducing the dependency of a memory device’s channel current to bitline voltage may allow comparators to have larger input offsets and therefore consume less area.

In some embodiments, the digital input signals of DACs may be shared. In other embodiments, DACs may work independently.

Different DACs with different architectures may be used to generate the currents. To generate a current from 0 to Imax (or from Imin to Imax), an N bit DAC may sequentially generate 2 ^L N different currents, one slightly larger than the previous one. Other DAC architectures like binary search, binary weighted, current steering may be used to speed up the conversion process (e.g. to reduce it to N steps).

In some embodiments, the presented architecture may reduce the power consumption of the analog-to-digital converter by avoiding the usage of power-hungry operational amplifiers. It may also reduce the chip area by reducing the sensitivity of the circuit’s accuracy to device mismatches and process variations.

These and other embodiments of the present disclosure will be explained with reference to the accompanying figures. In the figures, features with like numbers indicate like structure and function unless described otherwise.

FIG. 13 illustrates an example of a memory array configuration for device state verification after the application of a single or a sequence of programming pulses. The memory array may include a matrix ofNVM devices 2101 and 2102 arranged in rows and columns. The memory devices may have multiple terminals depending on a type of the NVM device used in the memory array. There may be multiple peripheral circuits around the memory array managing the functionality of the memory in different modes like read, write or operation. Each memory array or a set of memory arrays may be selected for being programmed with binary and analog (multibit) values. A single or a sequence of programming pulses may be applied to the selected devices to program their state with the predetermined values. After the application of pulses, the states of selected devices may be checked to see whether further pulses are needed or not. Memory devices 2101 may be selected for reading by applying proper voltages to their terminals. Voltage Vread 2103 may be applied to the horizontal wires and voltage Vbias 2104 may be applied to the vertical wires of the selected devices. Other terminals of the memory array may be biased with voltages like Vusl 2105 and Vus2 2106. These voltages may bias the unselected memory devices 2102 such a way that they may produce zero or negligible currents. The exact values of these Vusl and Vus2 voltages may depend on the memory device characteristics, and the value of voltages Vbias and Vread. More voltages may be applied to selected or unselected memory devices with more terminal to bias them in read or off conditions. The biasing scheme during device state verification may reduce the current of unselected devices Iusl (2107) and Ius2 (2108) to zero so the current on each bitline may only be the current of the selected memory devices Is (2109). These currents may be measured and verified with any circuits like ADCs. If the current of selected devices are still far away from the desired currents, a new set of programming pulses may be applied to them to bring them closer to the desired state. The process may be repeated until all the selected devices are programmed with acceptable accuracy.

FIG. 14 illustrated the already programmed memory array of FIG. 1 in operation mode.

Memory devices 2201 may be selected for operation by applying proper voltages to their terminals. During operation, a vector of input signals 2202 may be applied to the selected rows of the memory array. For in-memory computing applications, these signals may be the vector of analog or digital signals. In data storage applications, one or multiple rows of the memory array may be selected using the row decoders for data retrieval. Each selected memory device may produce a current proportional to the amplitude or width of the received input, voltage bias of bitlines and the state it is programmed to. These generated currents may be summed up on the common bitlines 2204 forming a combined current Ibl 2203. The current 2203 may then be measured and converted to digital using the Current Measuring System (CMS) 2200.

The CMS circuit 2200 may include a current-output DAC 2206 and a voltage comparator 2205. Output of the current-output DAC 2206 and the input of the voltage comparator 2205 may be connected to the bitline. The voltage comparator 2205 may compare the voltage on the bitline with a fixed voltage Vbias and switch its output sign whenever one gets higher or lower than the other one. For each measurement of the output current of the memory array during operation, the current-output DAC 2206 may start by generating a smallest possible current and step by step increase the generated currents. The amplitude of each step depends on the resolution of the DAC. Finer steps may be generated using DACs with higher resolutions. The current generated by the DAC (IDAC) may pass through the selected devices sharing the same bitline. The passage of current may increase the bitline voltage Vbl. As soon as the bitline voltage Vbl passes Vbias, the output of the comparator may switch stopping the DAC from increasing its current further. The last digital input applied to the DAC switching the sign of the comparator output may be the digital representation of the bitline current generated by memory devices of the memory array when bitline voltage is equal to Vbias.

In some embodiments, different DAC circuits with different architectures may be used for the implementation of 2206. This may include but not limited to DAC architectures like binary search, current steering, binary weighted, etc... Some of these DAC architectures may reduce the number of steps by which the DAC current may be incremented from 2 ^L N to N where N is the resolution of the DAC in bits.

In some embodiments, different circuits with different architectures may be used for the implementation of the comparator 2205. Low-gain amplifiers may be used to implement the comparator to reduce its power consumption.

Allowing the bitlines to fluctuate may remove the need for high-gain operational amplifiers to constantly keep the Vbias voltage on bitlines, reducing the power consumption and chip area of the system considerably.

In some embodiments, dependency of memory device current to bitline voltage may be reduced to increase the accuracy of converting bitline analog current to digital. For example, flash or floating-gate transistors with longer channels may be used to reduce the impact of bitline voltage.

In some embodiments using flash or floating-gate transistors as memory devices, transistors may be biased in subthreshold to reduce the dependency of device current to bitline voltage which may increase the accuracy of conversion.

In some embodiments, different CMS circuits connected to different bitlines may be controlled together. In some other embodiments, these CMS circuits may operate independent from one another. CMS of unselected bitlines may be turned off to save power.

FIG. 15 illustrates an example of memory array configured for the verification of the states of the selected devices after programming where memory devices are resistive switching elements. Each memory device 2301 may consist of a non-volatile resistive switching element 2303 like a PCM, memristor, resistive RAM, etc. which its resistance can be programmed through the application of programming signals. The memory cells may have an optional selector device 2302 connected in series with the resistive switching device 2303 facilitating the selected and deselection of individual memory cells inside the memory array. Devices on each row may be selected by applying a high voltage on a corresponding WL 2306. Setting the gate of pass transistors 2302 by applying a low voltage to the corresponding WL may deselect the devices on that row. The other terminal of the resistive switching elements on each row may share a common line called SL (2307) where input signals 2304 may also be applied to. Memory cells located on the same columns of the memory array may share a common bitline 2308 through which their current may be measured.

To verify the state or read current of each programmed memory device, A Vread voltage may be applied to the SL of the selected devices while the WL of the row is set to high. The other rows and all the column (BLs) may be biased with Vbias (2305). This biasing scheme may set the current in most of the unselected devices to zero. On the bitlines connected to the selected devices, the current Ibl may be just the current of the selected memory devices biased in read condition. This current may be equal to the conductance of the memory device (G) multiplied by the voltage dropped on the device (e.g. Vread-Vbias). If the current is not close enough to the desired current, the array may be configured again to the programming mode and a new set of programming pulses may be applied to the selected devices.

FIG. 16 illustrates how CMS circuits 2403 may be used with a memory array of resistive switching devices to read the output currents of the array in read and/or operation mode and convert it to digital. Different rows of the memory array may be selected for by setting the corresponding WLs 2401 to high. A vector of analog or digital input signals 2402 may be applied to the SLs of the memory array. The CMS circuits 2403 connected to BLs may then measure the current on BLs and convert them to their corresponding digital representation.

FIG. 17 illustrates an example of memory array configured for the verification of the states of the selected devices after programming where memory devices are flash or floating- gate transistors. Each flash memory transistor 2501 may have multiple terminals like WL (2505), CG (2508), SL (2506), EG (2507) and BL (2509) besides the substrate. Memory devices located on the same row may share WL, CG, SL, and EG while BLs are shared between memory devices located on the same column. Every two nearby memory devices may share the SL and EG forming a structure known as supercell. The memory array may be connected to multiple peripheral circuitries enabling proper operation of the memory array in read, write/programming and operation modes. These peripheral circuitries may include but not limited to column decoder and biasing circuits 2502, low- and high-voltage row decoders and programming circuits 2503, and sense amplifier, ADCs, and current to voltage converters 2504. The state of any device within the memory array may be verified after the application of a set of programming pulses by first selecting the device through the application of Vw_read, Veg_read and Vcg_read to its WL, EG and CG terminals respectively while keeping the SL at ground. Other devices on the shared BL may be deselected by applying zero to their CG and/or WL. Unselected devices on other columns may also be unselected by setting the voltage of their BL to zero. The current of the selected transistor may be measured by setting the BL of the selected transistor to Vbias. Different set of voltages may be applied to the memory array to bias the transistors for the read purpose.

FIG. 18 illustrates how CMS circuits 2601 may be used with a memory array of flash or floating-gate transistor devices to read the output currents of the array in read and/or operation mode and convert it to digital. Proper voltages may be applied to WL or CG to select the rows involved in the operation (or reading). Unselected rows of the memory array may be deselected by applying low voltages on CG or WL. SL and EG of the rows involved in the operation may be biased by 0 and Veg_read respectively. WL or CG of the selected devices not used for the selection of the row may receive an analog or a digital input signal 2602. Selected devices on each column receiving input signals may generate currents proportional to the input signal and, voltage bias applied to BL, and the state they are programmed to. CMS circuits 2601 connected to BLs may be used to read the sum of memory device currents on BLs and convert it into their corresponding digital representations.

In some embodiments, different flash transistors with different number of terminals and functionalities may be used to construct a memory array. In some other embodiments, the nearby flash transistors may have separate EGs and SLs.

In some other embodiments, flash memory devices may be used in different configurations to form the memory array.

In this or other embodiments, current of the selected transistor may be read from the source lines instead of bitlines.

FIG. 19 is a flowchart of an example method 2700 for analog to digital converters for NVM arrays to read out the analog currents generated by the memory devices within the memory array during read or operation mode. The method may include, at action 2702, programming one or more non-volatile memory (NVM) cells within an array to a target state. In this stage, selected devices inside the memory array may be programmed to generate predetermined analog currents when biased with particular biasing conditions identical to those used in read or operation mode. The bitline (BL) of the selected columns may be biased with Vbias when the states of memory devices are verified after the application of each set of programming pulses.

The method may include, at action 2704, selecting one or more of the NVM cells within the array to receive input signals. Based on the application, single or multiple rows of the memory array may be selected to receive digital or analog signals when configured for read or operation mode. Selected memory devices may produce the same currents they are programmed to at action 2702 if their BLs are biased with Vbias. The BLs of the selected columns may be left floating.

The method may include, at action 2706, connecting a current-output digital -to-analog converter (DAC) to a bitline (BL) and generating a current on the BL. The DAC may produce a current proportional to the digital code it receives. It may start by generating the smallest current and which may be then increased step by step. The current generated by the DAC may pass through the selected memory devices sharing the same BL. The portion of the DAC current which may pass through each of the selected and activated memory devices may depend on the device state and the input it receives.

The method may include, at action 2708, comparing the BL voltage with a fixed voltage (Vbias) using a comparator having an input connected to the BL. A comparator connected to the BL may monitor the BL voltage and switch its output when the BL voltage passes the fixed voltage Vbias. The switching of the comparator output may stop the DAC output current from further increasing.

The method may include, at action 2710, determining whether the BL voltage has reached Vbias. When the BL voltage reaches the Vbias, the current generated by the DAC may be equal to the total current generated by the selected devices at the read or operation condition when BL voltage is Vbias.

The method may include, at action 2712, if the current generated by the DAC is equal to the sum of the currents selected memory devices are programmed to, stopping the DAC from increasing current to BL and at action 2714 DAC’s digital input is the ADC’s output. If the BL voltage reaches Vbias, the output of the comparator may switch stopping the DAC output current from increasing further. At this stage, the last digital input code applied to the DAC may be the digital representation of the total current generated by the selected memory devices on the BL.

Alternatively, if the current generated by the DAC is not equal to the sum of the currents selected memory devices are programmed to, the method may include, at action 2716, increasing the current generated by DAC and adding that current to the BL. Steps 2708 and 2710 may then be repeated until the current generated by the DAC is equal to the sum of the currents generated by the selected memory devices. 4. PROGRAMMING NON-VOLATILE MEMORY ARRAYS WITH

AUTOMATIC PROGRAMMING PULSE AMPLITUDE ADJUSTMENT USING CURRENT-LIMITING CIRCUITS

One or more embodiments of the present disclosure may include a system. The system may include a single or multiple memory arrays and may be used in operation or programming phase. The memory array may be configured to be used for digital or analog data storage or in memory computing such as vector by matrix multiplication (VMM). The memory array may include a matrix of devices. Each device of the matrix of devices may be configured to receive a sequence of programming signals or pulses. Each device may retain its state until the new set of programming signals or pulses are applied. The programming signals may be used to program a single or multiple bits of information, which may cause the memory array to store digital data. In other embodiments, the programming signals may be used to program a weight of the corresponding device, which may cause the memory array to store a matrix of weights.

Each device may have two or more terminals used differently in programming and operation modes. Each device of the matrix of devices may also be configured to receive other digital or analog input signals on its terminals which may have different values in operating and programming modes. In each matrix of devices, devices located on the same rows or columns may share one or more terminals and may be read or get programmed in parallel. A large current may pass through devices getting programmed due to the application of programming signals or pulses.

The system may also include multiple Current-Compliance (CC) circuits. Each CC circuit may be electrically coupled to a corresponding device or common rows or columns of a matrix of devices. In addition, each CC may be configured to limit the corresponding current passing through the circuit. Each CC circuit may have multiple inputs by which the amplitude of the current which can pass through the circuit can be adjusted. Each CC circuit may be disconnected from the matrix of devices in the operation mode.

In some embodiments, a system may include one or more non-volatile memory arrays. In some systems, the memory arrays may be used to work as memory to store digital or analog data. In some other systems, the memory array may store analog parameters and may be used for in-memory computation. In memory arrays, there may be peripheral circuitries such as charge pump, pulse generator, buffers, row and column decoders which may be used to select and read or program one or more rows and columns for devices. In some memory arrays, devices in the memory array may be weighted or programmed with an analog or digital values by applying a sequence of pulses to device terminals (with properly adjusted amplitude). In addition, in some memory arrays, there may be current-compliance circuits connected to the rows and/or columns of the memory array. The current-compliance circuits may be used during programming to limit the maximum current passing through the devices being programmed.

In some embodiments, proper voltages or currents may be applied to terminals of the memory array to allow parallel programming of multiple devices in the array.

In some embodiments, proper voltages or currents may be applied to terminals of the memory array to avoid unselected devices in the array from getting programmed.

In some embodiments, the CC circuit is connected to the terminal of the array to which the programming pulse may be applied. In other embodiments, the CC circuit may be connected to other terminals of the array from which the programming current may pass.

In some embodiments, the CC circuits may limit the current of an individual device inside the array selected to be programmed. In other embodiments, the CC circuit may limit the accumulative currents of devices being programmed in parallel.

In some embodiments, the memory array may include non-volatile memory device. For example, the memory array may include a flash memory device, a memristive memory device, a phase change memory (PCM) device, etc.

In some embodiments, the CC circuit may consist of passive devices like resistors. In some other embodiments, the CC circuit may consist of active devices like FET transistors where the channel conductance is adjusted by the voltage applied to the gate.

Some embodiments described in the present disclosure may permit the CC circuit to limit the maximum current which may pass the selected devices being programmed. The CC may reduce the amplitude of the programming pulses to reduce the maximum current passing through the NVM devices at the beginning. With the devices getting more and more programmed, the CC circuit may allow larger and larger programming pulses to be applied to the selected NVM devices being programmed.

In some embodiments, the CC circuit may allow a fixed maximum current to pass through during the whole programming phase. In some other embodiments, the biasing condition and the maximum current the CC circuit passes may be varied and adjusted during the programming phase to allow less or more current or smaller or larger programming pulses to pass.

These and other embodiments of the present disclosure will be explained with reference to the accompanying figures. In the figures, features with like numbers indicate like structure and function unless described otherwise. FIG. 20A illustrates an example environment in which a CC circuit 3106 may be implemented, in accordance with at least one embodiment described in the present disclosure.

The environment may include matrix ofNVM devices 3100.

The matrix ofNVM devices 3100 may consist of rows and columns ofNVM devices 3101. The memory array may store binary data or a matrix of weights. The memory array may include two terminal devices or devices with more than two terminals. The memory array may include a flash memory array, a memristor memory array, or any other appropriate memory array. Memory devices located on the same column within the memory array may share a common terminal 3102. In addition, memory devices located on the same row within the memory array may share one or multiple common terminals 3103, 3104, and 3105. The memory array 3100 may include any number of devices 3101 in each row or column, for example, thousands or more devices 3101. In addition, the memory array 3100 may include a two-dimensional or three-dimensional matrix of devices 3101.

The devices 3101 may form a matrix configured to receive a sequence of programming pulses signals (e.g., programming signals) at device terminals (e.g. gates, drain and source) with properly adjusted amplitude to store a weight value. In some embodiments, a device state (e.g., the weight of the devices 3101) may be measured. If the device state is not within a target state, another programming pulse may be applied to the devices 3101. In some embodiments, the weight value may include a positive value or a negative value. In addition, in some embodiments, the weight values stored on the devices 3101 may include an analog value or a digital value. In some embodiments, the gate of the devices 3101 may include a floating gate.

In some embodiments, the devices 3101 may include transistors configured to store bits of data as a charge, for example, on floating gate transistors. The devices 3101 may include single-level cell (SLC) devices. Additionally or alternatively, the devices 3101 may include multi-level cell (MLC), triple-level cell (TLC) or quad-level cell (QLC) devices. In some embodiments, the memory array 3100 may be used to perform neural network operations (e.g., the memory array 3100 may be used in read mode to execute functionality of synapses of the neural network like vector by matrix multiplication).

In some embodiments, multiple devices 3101 one a single row or column may be programmed in parallel. The sequence of programming pulses applied to the programming terminal 3103 of the selected row and the biasing voltages or current applied to other terminals of the devices 3102, 3104, 3105 may be seen by all devices electrically coupled to the same terminals. Devices 3101 electrically coupled to the terminal receiving the sequence of programming pulses may be programmed in parallel. In some embodiments, some devices 3101 on one row or column of the array getting programmed in parallel may be stopped from being programmed more by applying proper voltages or current to uncommon terminals (for example terminals 3102 in Fig. 20A). In some other embodiments, the same process may be applied to avoid devices in unselected rows and columns from getting programmed.

During the programming of the NVM devices 3101 in memory array 3100, the speed and amount of programming happening in selected devices may depend on the type of NVM device and the voltages or currents applied to other terminals of the memory devices 3102, 3103, 3104, and 3105.

In some embodiments, a CC circuit 3106 may be added to the memory array during the programming phase to limit the current passing through each of the device 3101 which are being programmed in parallel to extend device endurance and lifetime. The CC may reduce the power consumed to program the devices 3101 and may reduce the area of the charge pump needed to generate the sequence of programming pulses. With the usage of the CC circuit, the biasing of the array terminal 3102 may be provided by the voltage applied to terminal 3107.

In some embodiments, the CC circuit may also be used for analog programming of NVM devices 3101 by limiting the amount of change in device conductance per each applied programming pulse. In these embodiments, the CC circuit may make the change in device conductance due to the programming pulse independent of the pulse amplitude.

In other embodiments, the CC may be used to change and adjust the speed of programming in devices 3101 which are getting programmed. Allowing more current to pass may result in faster and coarser NVM device programming while reducing the current may yield to slower but more accurate NVM device programming. In addition, the CC circuit may be used to get uniform gradual programming in multiple devices with device-to-device mismatch when they are getting programmed in parallel.

The CC circuits 3106 may be controlled together or individually.

The memory array 3100 may be used as a memory or for implementing other applications like in-memory computation in operation or read mode without the CC circuits 3106 by applying proper inputs from input sources to some terminals of the array (e.g. 3104 and 3105) and reading currents from other terminals (e.g. 3102) while other terminals are biased with proper voltages (e.g. setting 3103 to GND).

Although not shown in FIG. 20A, there may be other peripheral blocks around the memory array necessary for the proper operation of the block like row and column decoders, sense amplifiers, pulse generator, low-voltage and high-voltage decoders, charge pump, etc. In some embodiment, the CC circuit may include a passive resistor. In other embodiments, a single FET transistor may be used to limit the current passing between terminals 3102 and 3107 where the current allowed to flow through the FET channel is set by the voltage applied to the gate of the FET transistor.

FIG. 20B illustrates an example of CC circuit 3106 that may be implemented in the environment of FIG. 20 A, in accordance with at least one embodiment described in the present disclosure. The FET transistor 3108 may be used as a CC to limit the current passing through a selected NVM device in the memory array 3100 by limiting the current passing through terminals 3102 and 3107. Voltage 3112 may be applied to terminal 3107 to bias the NVM devices in the memory array during programming. The current allowed to pass through the CC FET transistor 3108 may be determined by the voltage applied to the gate 3109 of the FET transistor 3108. The voltage of the FET gate 3109 may be generated with a diode-connected transistor 3111 derived by the current source 3110 which may limit the maximum current of the FET 3108 to be equal to the current produced by the current source 3110.

In some embodiments, the diode-connected FET transistor 3111 may be shared between multiple CC circuits 3106. In some other embodiments, the current generated by current source 3110 may be adjusted during the time a sequence of pulses is being applied to the memory array 3100.

FIG. 21 illustrates another example of how the CC circuit may be used in memory array to limit the current passing through NVM devices during parallel programming. Memory array 3200 may correspond to the memory array 3100 in FIG. 1A. Memory device 3201 may correspond to the memory device 3101 in FIG. 20A. In addition, memory array terminals 3202, 3203, 3204 and 3205 may respectively correspond to the memory array terminals 3102, 3103, 3104, and 3105 in FIG. 1A.

The CC circuit 3206 may be placed between the memory array 3200 and the pulse generator 3207 generating the sequence of programming pulse used to program NVM devices 3201. The CC circuit 3206 may limit the sum of currents of the selected NVM devices 3201 located on the same row that the sequence of programming pulse is being applied. The NVM devices 3201 on the selected row may be avoided from further programming by applying proper voltage to terminals 3202.

In some embodiments, the pulse generator circuit 3207 and the CC circuit 3206 may be shared between multiple rows to reduce chip area. In some other embodiments, there may be other peripheral circuitry like row decoder located between the CC circuit and the memory array. In another embodiments, the row decoder and CC may be merged into a single circuit. When used to limit the current of multiple devices during programming, the current of CC circuit may mostly pass through NVM devices 3201 with lower threshold voltage, program them more than other devices and increase their threshold voltages. The same process may get repeated when the subsequent programming pulses are getting applied to the memory array 3200.

When more and more selected devices 3201 get programmed with the sequence of programming pulses, the sum of current passing through the CC circuit may decrease resulting in a reduction of the voltage dropped on the CC circuit. Having smaller drop on the CC circuit may increase the amplitude of the pulse seen by the NVM memory devices 3201 which may increase the programming speed. In this positive feedback, the amplitude of the programming pulses seen by internal NVM devices 3201 may be automatically adjusted and increased when devices being programmed in parallel get more and more programmed. The CC circuit 3206 may automatically account for the problem of device-to-device variations between NVM memory devices 3201 during the programming phase.

In accordance with common practice, the various features illustrated in the drawings may not be drawn to scale. The illustrations presented in the present disclosure are not meant to be actual views of any particular apparatus (e.g., device, system, etc.) or method, but are merely example representations that are employed to describe various embodiments of the disclosure. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may be simplified for clarity. Thus, the drawings may not depict all of the components of a given apparatus (e.g., device) or all operations of a particular method.

Terms used herein and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as“open” terms (e.g., the term“including” should be interpreted as“including, but not limited to,” the term“having” should be interpreted as“having at least,” the term“includes” should be interpreted as“includes, but is not limited to,” etc.).

Additionally, if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and“one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles“a” or“an” limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases“one or more” or“at least one” and indefinite articles such as“a” or“an” (e.g.,“a” and/or“an” should be interpreted to mean“at least one” or“one or more”); the same holds true for the use of definite articles used to introduce claim recitations.

In addition, even if a specific number of an introduced claim recitation is explicitly recited, it is understood that such recitation should be interpreted to mean at least the recited number (e.g., the bare recitation of“two recitations,” without other modifiers, means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to“at least one of A, B, and C, etc.” or“one or more of A, B, and C, etc.” is used, in general such a construction is intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, etc. For example, the use of the term“and/or” is intended to be construed in this manner.

Further, any disjunctive word or phrase presenting two or more alternative terms, whether in the summary, detailed description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase“A or B” should be understood to include the possibilities of“A” or “B” or“A and B.”

Additionally, the use of the terms“first,”“second,”“third,” etc., are not necessarily used herein to connote a specific order or number of elements. Generally, the terms“first,” “second,”“third,” etc., are used to distinguish between different elements as generic identifiers. Absence a showing that the terms“first,”“second,”“third,” etc., connote a specific order, these terms should not be understood to connote a specific order. Furthermore, absence a showing that the terms first,”“second,”“third,” etc., connote a specific number of elements, these terms should not be understood to connote a specific number of elements. For example, a first widget may be described as having a first side and a second widget may be described as having a second side. The use of the term“second side” with respect to the second widget may be to distinguish such side of the second widget from the“first side” of the first widget and not to connote that the second widget has two sides.

The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention as claimed to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described to explain practical applications, to thereby enable others skilled in the art to utilize the invention as claimed and various embodiments with various modifications as may be suited to the particular use contemplated.