Title:
HOLD TIME MARGIN DETECTION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2022/041154
Kind Code:
A1
Abstract:
Embodiments of the present application relate to the technical field of circuits. Disclosed is a hold time margin detection circuit, mitigating the problem in the prior art of poor precision in detection for a hold time margin in a chip. The specific solution is that: the detection circuit comprises: a generator and a decision circuit; the generator comprises at least one testing circuit; each testing circuit comprises N first flip flops, N second flip flops, and N data delay units; the delay of the N data delay units increases gradually in sequence; a delay difference between two adjacent data delay units is less than or equal to a preset value; data output ends of the N first flip flops are respectively connected to input ends of the N data delay units; output ends of the N data delay units are respectively connected to data input ends of the N second flip flops; data output ends of the N second flip flops are connected to the decision circuit.
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Inventors:
WANG ZHUO (CN)
DONG ZIJIAN (CN)
LI MEI (CN)
DONG ZIJIAN (CN)
LI MEI (CN)
Application Number:
PCT/CN2020/112289
Publication Date:
March 03, 2022
Filing Date:
August 28, 2020
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
H03K19/00; G01R31/317
Foreign References:
| TW201245732A | 2012-11-16 | |||
| US20080201675A1 | 2008-08-21 | |||
| US7138829B1 | 2006-11-21 | |||
| US20030028835A1 | 2003-02-06 |
Attorney, Agent or Firm:
BEIJING ZBSD PATENT&TRADEMARK AGENT LTD. (CN)
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