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Title:
HYBRID SUPERCONDUCTING-FERROMAGNET RANDOM ACCESS MEMORY ELEMENT
Document Type and Number:
WIPO Patent Application WO/2019/096416
Kind Code:
A1
Abstract:
A superconducting memory cell device suitable for a superconducting computer is described. The memory cell comprises two superconducting electrodes and a ferromagnetic component coupled between the two superconducting electrodes to form weak link between the superconducting electrodes, thereby to provide a Josephson junction such that, when the Josephson junction is in use, a supercurrent can be generated between the superconducting electrodes. The ferromagnetic component provides a magnetic state configurable by operation of an external bit setting control means into at least a first and a second magnetic state. In at least one of the first and second magnetic states, the ferromagnetic component is configured to convert, when in use, spin singlet electron pairs to spin triplet electron pairs at locations on the Josephson junction to tunnel between the superconducting electrodes via the weak link, to generate a supercurrent having a critical current. The critical current of the first magnetic state is definable as a first bit state of the superconducting memory cell. The critical current of the second magnetic state is different from the critical current of the first magnetic state and definable as a second bit state of the superconducting memory cell. A method of writing to the superconducting memory cell, a method of reading from the superconducting memory cell, systems, controllers and a computer-readable medium are also provided.

Inventors:
AARTS JAN (NL)
LAHABI KAVEH (NL)
Application Number:
PCT/EP2017/079697
Publication Date:
May 23, 2019
Filing Date:
November 18, 2017
Export Citation:
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Assignee:
UNIV LEIDEN (NL)
International Classes:
G11C11/16; G11C11/44
Foreign References:
EP2945160A12015-11-18
US20120184445A12012-07-19
US8270209B22012-09-18
US20150094207A12015-04-02
Other References:
S VOLTAN: "Inducing spin triplet superconductivity in a ferromagnet", SCIENCE, 29 September 2016 (2016-09-29), Netherlands, pages 1 - 172, XP055494010, ISBN: 978-90-85-93265-9, Retrieved from the Internet [retrieved on 20180719]
Attorney, Agent or Firm:
HGF LIMITED (London EC2Y 5DN, GB)
Download PDF:
Claims:
Claims

1. A superconducting memory cell comprising:

two superconducting electrodes; and

a ferromagnetic component coupled between the two superconducting electrodes to form a weak link between the superconducting electrodes, thereby to provide a Josephson junction such that, when the Josephson junction is in use, a supercurrent can be generated between the superconducting electrodes; wherein the ferromagnetic component provides a magnetic state configurable by operation of an external bit setting means into at least a first and a second magnetic state,

wherein in at least one of the first and second magnetic states, the ferromagnetic component is configured to convert, in use, spin singlet electron pairs to spin triplet electron pairs at locations on the Josephson junction to tunnel between the superconducting electrodes via the weak link, to generate a supercurrent having a critical current, and

wherein the critical current of the first magnetic state is definable as a first bit state of the superconducting memory cell, and wherein the critical current of the second magnetic state is different to the critical current of the first magnetic state and definable as a second bit state of the superconducting memory cell.

2. The superconducting memory cell of claim 1 , wherein the ferromagnetic component comprises a layer arranged adjacent to the superconducting electrodes.

3. The superconducting memory cell of any of the preceding claims, wherein the superconducting electrodes are atop the ferromagnetic component.

4. The superconducting memory cell of any of the preceding claims, wherein the ferromagnetic component provides a non-homogeneous spin configuration such that an in-plane exchange field gradient of a resulting magnetic vortex converts spin singlet electron pairs to spin triplet electron pairs.

5. The superconducting memory cell of any of the preceding claims, wherein the device further comprises a non-ferromagnetic metal spacer layer each atop the ferromagnetic component, and an additional thin film ferromagnetic layer atop the spacer layer, wherein the superconducting electrodes are atop the additional thin film ferromagnetic layer, wherein the superconducting memory cell further comprises a trench formed to extend through and separate the two superconducting electrodes, through the additional thin film ferromagnetic layer and through the non-ferromagnetic spacer layer, the trench not extending into the ferromagnetic component, to thereby form the junction.

6. The superconducting memory cell of claim 5, wherein the magnetic spins of the additional ferromagnetic layer and the magnetic spins of the ferromagnetic component are non-collinear in the first or the second magnetic states of the ferromagnetic component, at least at locations along the region of the trench, wherein the magnetic non-collinearity converts further spin electron singlet pairs into spin electron triplet pairs.

7. The superconducting memory cell of any of the preceding claims, wherein the ferromagnetic component contains at least one localised magnetic vortex core.

8. The superconducting memory cell of claim 7, wherein the at least one localised magnetic vortex core suppresses the conversion of spin electron triplet pairs such that they are not generated at the location of the at least one localised magnetic vortex core.

9. The superconducting memory cell of either of claims 7 or 8, wherein no supercurrent is generated at the location of the at least one localised magnetic vortex core.

10. The superconducting memory cell of any of claims 7 to 9, wherein a supercurrent channel exists across the junction on either side of the at least one localised magnetic vortex core.

1 1. The superconducting memory cell of any of claims 7 to 10, wherein the at least one localised magnetic vortex core has at least one stable position.

12. The superconducting memory cell of any of claims 7 to 1 1 , wherein the at least one localised magnetic vortex core may comprise at least one of an out-of-plane magnetic vortex, a magnetic domain wall configuration, a skyrmion, or an in-plane magnetic defect.

13. The superconducting memory cell of any of the preceding claims, wherein the amount of supercurrent carried by the junction is dependent upon the magnetic state of the ferromagnetic component.

14. The superconducting memory cell of any of the preceding claims, wherein at least two distinct critical current values are reliably generated.

15. The superconducting memory cell of any of the preceding claims, wherein the external bit setting control means includes at least one of an applied magnetic field or an applied electromagnetic wave.

16. The superconducting memory cell of any of the preceding claims, wherein the first and second magnetic states are stable at non-cryogenic temperatures.

17. The superconducting memory cell of any of the preceding claims, wherein the superconducting electrodes are comprised of niobium, optionally with a thickness of between 35 to 60nm, optionally 45 nm.

18. The superconducting memory cell of any of the preceding claims, wherein the ferromagnetic component is comprised of a cobalt disk with a thickness and a diameter to ensure stabilization of the at least one localised magnetic vortex core, optionally with a thickness of between 50nm and 70nm, optionally 60 nm.

19. The superconducting memory cell of any of claims 5 to 18, wherein the non- ferromagnetic metal spacer layer is comprised of copper, optionally with a thickness of between 3 and 7nm, optionally 5 nm.

20. The superconducting memory cell of any of claims 5 to 19, wherein the thickness of the additional thin film ferromagnetic layer is optimized for the generation of spin triplet electron pairs, wherein the thin film ferromagnetic layer is comprised of nickel and the thickness is optionally 1.5 nm.

21. The superconducting memory cell of any of claims 1 to 20, wherein ferromagnetic component further comprises at least a third magnetic state, wherein the critical current of the third magnetic state is different to the critical current of the first magnetic state and the critical current of the second magnetic state, and wherein the critical current of the third magnetic state is definable as a third bit state of the superconducting memory cell.

22. A superconducting memory cell system comprising the superconducting memory cell of any of claims 1 to 21 , further comprising the external bit setting control means, wherein the external bit setting control means is operable to reliably reconfigure the magnetic state of the ferromagnetic component between at least the first and second magnetic states.

23. The superconducting memory cell system of claim 22, wherein the external bit setting control means is arranged to apply a magnetic field in the plane of the ferromagnetic component, or to apply an electromagnetic wave to the ferromagnetic component.

24. A superconducting memory cell system as claimed in claim 22 or 23, further comprising an external read out means, wherein the external readout means is operable to measure the critical current of the superconducting memory cell.

25. The superconducting memory cell system of claim 24, wherein the external readout means is further configured to evaluate the bit state of the superconducting memory cell based on the measured critical current.

26. A superconducting memory unit comprising a plurality of superconducting memory cells of any of claims 1 to 25, arranged to together be operable to store a plurality of data bits.

27. A controller configured to write to and/or read from a superconducting memory cell as claimed in any of claims 1 to 21 , the controller comprising: a bit write control mean means configured to receive information to store in a superconducting memory cell, and to operate a bit setting means to configure the magnetic state of the ferromagnetic component of the superconducting memory cell to a first or a second state to cause the superconducting memory cell to provide a critical current corresponding to a given bit state for encoding the information; and/or

a bit readout control means configured to operate an external readout means to measure the critical current of the superconducting memory cell and to evaluate the bit state of the superconducting memory cell based on the measured critical current.

28. A method of writing to a superconducting memory cell according to any of claims 1 to 21 , the method comprising:

receiving information to store a superconducting memory cell,

operating a bit setting means to configure the magnetic state of the ferromagnetic component of the superconducting memory cell to a first or a second state to cause the superconducting memory cell to provide a critical current corresponding to a given bit state for encoding the information.

29. A method of reading from a superconducting memory cell according to any of claims 1 to 21 , the method comprising:

operating an external readout means to measure the critical current of the superconducting memory cell; and

evaluating the bit state of the superconducting memory cell based on the measured critical current.

30. The method of claim 29, wherein if the measured critical current is a low value then the bit state is determined to be a first bit value, whereas if the measured critical current is a high value then the bit state is determined to be a second bit value.

31. The method of claim 29, wherein if the measured critical current is below a predetermined threshold level then the bit state is determined to be a first bit value, whereas if the measured critical current is above a predetermined threshold level then the bit state is determined to be a second bit value.

32. A computer-readable medium having instructions stored thereon which, when executed by a controller means, cause the controller to perform a method according to any of claims 28 to 31.

Description:
HYBRID SUPERCONDUCTING-FERROMAGNET RANDOM ACCESS MEMORY

ELEMENT

TECHNICAL FIELD

The present disclosure relates to hybrid superconducting-ferromagnet random access memory elements and particularly, but not exclusively, to a device and method for providing hybrid superconducting-ferromagnet random access memory elements which can be integrated with other superconducting electronic elements to allow for a superconducting computer system. Aspects of the invention relate to a device, a writing method, a reading method, systems, controllers and a computer readable medium.

BACKGROUND

In the field of superconducting computing there is an unresolved need for superconducting memory; that is, memory which can be integrated with other superconducting electronic components to allow for the development of superconducting computing.

A previous approach to providing a superconducting memory element is detailed in US 8270209 B2 and US 20150094207 A1 in which a phase-hysteretic magnetic Josephson junction is used to generate digital states based on the phase difference between the two superconductors at the junction. This requires a word-write current provided on a word-write line and a bit-write current provided on a bit-write line to set a logic state, wherein a superconducting phase is generated according to the stored logic state. However, this approach does not provide a stable state, and so does not provide reliable bit retention, particularly if the temperature of the cell rises, for example, to room temperature.

It is in the above context that the present invention has been devised.

SUMMARY OF THE INVENTION

Aspects and embodiments of the invention provide a device, methods, systems, controllers and a computer readable medium as claimed in the appended claims.

According to an aspect of the present disclosure, there is provided a superconducting memory cell suitable for a superconducting computer. The memory cell comprises two superconducting electrodes and a ferromagnetic component coupled between the two superconducting electrodes to form weak link between the superconducting electrodes, thereby to provide a Josephson junction such that, when the Josephson junction is in use, a supercurrent can be generated between the superconducting electrodes. The ferromagnetic component provides a magnetic state configurable, by operating an external bit setting control means, into at least a first and a second magnetic state. In at least one of the first and second magnetic states, the ferromagnetic component is configured to convert, when in use, spin singlet electron pairs to spin triplet electron pairs at locations on the Josephson junction to tunnel between the superconducting electrodes via the weak link, which generates a supercurrent having a critical current. The critical current of the first magnetic state is definable as a first bit state of the superconducting memory cell. The critical current of the second magnetic state is different to the critical current of the first magnetic state and definable as a second bit state of the superconducting memory cell.

According to another aspect of the present disclosure, there is provided a method writing to a superconducting memory cell as described herein. The method comprises: receiving information to store a superconducting memory cell, operating a bit setting means to configure the magnetic state of the ferromagnetic component of the superconducting memory cell to a first or a second state to cause the superconducting memory cell to provide a critical current corresponding to a given bit state for encoding the information.

According to another aspect of the present disclosure, there is provided method of reading from a superconducting memory cell as described herein. The method comprises: operating an external readout means to measure the critical current of the superconducting memory cell; and evaluating the bit state of the superconducting memory cell based on the measured critical current. In embodiments, if the measured critical current is a low value then the bit state may be determined to be a first bit value, whereas if the measured critical current is a high value then the bit state may be determined to be a second bit value. In embodiments, if the measured critical current is below a predetermined threshold level then the bit state may be determined to be a first bit value, whereas if the measured critical current is above a predetermined threshold level then the bit state may be determined to be a second bit value.

Advantageously, by providing a superconducting memory cell and/or a method as described herein, a superconducting memory cell can be provided which can be used to store data, and which can be integrated with other superconducting electronic components to allow for the development of superconducting computing.

In embodiments, the ferromagnetic component may comprise a ferromagnetic layer arranged adjacent to the superconducting electrodes. In embodiments, the superconducting electrodes may be provided atop the ferromagnetic component.

In embodiments, the ferromagnetic component may provide a non-homogeneous spin configuration such that an in-plane exchange field gradient of a resulting magnetic vortex converts spin singlet electron pairs to spin triplet electron pairs.

In embodiments, the device may comprise a non-ferromagnetic metal spacer layer atop the ferromagnetic component. There may also be provided an additional thin film ferromagnetic layer atop the spacer layer, wherein the superconducting electrodes are atop the additional thin film ferromagnetic layer. The superconducting memory cell may further comprise a trench formed to extend through and separate the two superconducting electrodes, through the additional thin film ferromagnetic layer and through the non-ferromagnetic spacer layer, the trench not extending into the ferromagnetic component, to thereby form the junction.

Advantageously, in this embodiment the additional thin film ferromagnetic layer provides additional triplet generation, so a larger current can be generated. Further advantageously, the non-ferromagnetic metal spacer layer prevents exchange coupling between the ferromagnetic component and the additional ferromagnetic layer.

In embodiments, the magnetic spins of the additional ferromagnetic layer and the magnetic spins of the ferromagnetic component may be non-collinear in the first or the second magnetic states of the ferromagnetic component, absence of a localised magnetic vortexlocalised magnetic vortex coreat least at locations along the region of the trench, wherein the magnetic non-collinearity converts further spin electron singlet pairs into spin electron triplet pairs.

In embodiments, the ferromagnetic component may contain at least one localised magnetic vortex core.

In embodiments, the at least one localised magnetic vortex core may suppress the conversion of spin electron triplet pairs such that they are not generated at the location of the at least one localised magnetic vortex core.

In embodiments, no supercurrent may be generated at the location of the at least one localised magnetic vortex core. In embodiments, a supercurrent channel may exist across the junction on either side of the at least one localised magnetic vortex.

In embodiments, the at least one localised magnetic vortex core may have at least one stable position.

Advantageously, this allows a bit state to be determined according to whether the at least one localised magnetic vortex core is located in the at least one stable position or not. In the case of more than one stable position, the bit state can be determined according to which stable position the at least one localised magnetic vortex core is in.

In embodiments, at least one of the first, second and further magnetic states of the ferromagnetic components can be stably held by the ferromagnetic component in absence of continued influence of external bit setting means. Plural stable magnetic states facilitate provision of non-volatile superconducting memory, where the bit state is maintained in the absence of power or external influence from the bit setting means. The stable states may be maintained even if temperature of the superconducting memory cell rises to non-cryogenic temperatures.

In embodiments, the at least one localised magnetic vortex core may comprise at least one of an out-of-plane vortex, a magnetic domain wall configuration, a skyrmion, or an in-plane magnetic defect.

In embodiments, the amount of supercurrent carried by the junction may be dependent upon the magnetic state of the ferromagnetic component.

In embodiments, at least two distinct critical current values may be reliably generated.

In embodiments, the external bit setting control means may include at least one of an applied magnetic field or an applied electromagnetic wave.

Advantageously, this provides a reliable, controllable and measurable means of controlling the magnetic state of the ferromagnetic component, wherein the magnetic state of the ferromagnetic component determines the bit state.

In embodiments, the first and second magnetic states, and optionally the position of the at least one localised magnetic vortex core, may be stable at non-cryogenic temperatures. Advantageously, this allows the stored information to be retained even during a system failure which results in the device being warmed to non-cryogenic temperatures, or during a planned warming of the device.

In embodiments, the superconducting electrodes may be comprised of niobium, optionally with a thickness of between 35 to 60nm, optionally 45 nm.

In embodiments, the ferromagnetic component may be comprised of a cobalt disk with a thickness and a diameter to ensure stabilization of the at least one localised magnetic vortex core, optionally with a thickness of between 50nm and 70nm, optionally 60 nm.

In embodiments, the non-ferromagnetic metal spacer layer may be comprised of copper, optionally with a thickness of between 3 and 7nm, optionally 5 nm.

In embodiments, the thickness of the additional thin film ferromagnetic layer may be optimized for the generation of spin triplet electron pairs, wherein the thin film ferromagnetic layer is comprised of nickel and the thickness is optionally 1.5 nm.

In embodiments, the ferromagnetic component may further comprise at least a third magnetic state, wherein the critical current of the third magnetic state is different to the critical current of the first magnetic state and the critical current of the second magnetic state, and wherein the critical current of the third magnetic state is definable as a third bit state of the superconducting memory cell.

Viewed from another aspect, the present disclosure provides a superconducting memory cell system comprising a superconducting memory cell as described herein, further comprising the external bit setting control means, wherein the external bit setting control means is operable to reliably reconfigure the magnetic state of the ferromagnetic component between at least the first and second magnetic states.

In embodiments, the external bit setting control means may be arranged to apply a magnetic field in the plane of the ferromagnetic component, or to apply an electromagnetic wave to the ferromagnetic component. In embodiments, the superconducting memory cell system may further comprise an external read out means, wherein the external readout means is operable to measure the critical current of the superconducting memory cell.

In embodiments, the external readout means may be further configured to evaluate the bit state of the superconducting memory cell based on the measured critical current.

Viewed from another aspect, the present disclosure provides a superconducting memory unit comprising a plurality of superconducting memory cells as described herein, arranged to together be operable to store a plurality of data bits.

Viewed from another aspect, the present disclosure provides a controller configured to write to and/or read from a superconducting memory cell as described herein. The controller comprising: a bit write control mean means configured to receive information to store in a superconducting memory cell, and to operate a bit setting means to configure the magnetic state of the ferromagnetic component of the superconducting memory cell to a first or a second state to cause the superconducting memory cell to provide a critical current corresponding to a given bit state for encoding the information; and/or a bit readout control means configured to operate an external readout means to measure the critical current of the superconducting memory cell and to evaluate the bit state of the superconducting memory cell based on the measured critical current.

Within the scope of this application it is expressly intended that the various aspects, embodiments, examples and alternatives set out in the preceding paragraphs, in the claims and/or in the following description and drawings, and in particular the individual features thereof, may be taken independently or in any combination. That is, all embodiments and/or features of any embodiment can be combined in any way and/or combination, unless such features are incompatible. The applicant reserves the right to change any originally filed claim or file any new claim accordingly, including the right to amend any originally filed claim to depend from and/or incorporate any feature of any other claim although not originally claimed in that manner.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 illustrates two different embodiments of a superconducting memory cell in accordance with the disclosure;

Figure 2 shows a magnetic configuration of the ferromagnetic component of the first and second embodiments and the resulting localised magnetic vortex core;

Figure 3 provides examples of how a critical current varies according to an applied magnetic field for different embodiments of the superconducting memory cell;

Figure 4 shows additional critical current against applied magnetic field measurements, along with the corresponding magnetic states from micromagnetic simulations, for an embodiment of the superconducting memory cell; and

Figure 5 shows schematic diagram of an embodiment of a superconducting memory cell in accordance with an embodiment.

Throughout the description and the drawings, like reference numerals refer to like parts.

DETAILED DESCRIPTION

Throughout the description and claims of this specification, the words“comprise” and“contain” and variations of them mean“including but not limited to”, and they are not intended to (and do not) exclude other moieties, additives, components, integers or steps. Throughout the description and claims of this specification, the singular encompasses the plural unless the context otherwise requires. In particular, where the indefinite article is used, the specification is to be understood as contemplating plurality as well as singularity, unless the context requires otherwise.

Features, integers, characteristics, compounds, chemical moieties or groups described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive. The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

Figure 1 illustrates a first and a different second embodiment of the superconducting memory cell device.

Figure 1a shows a first embodiment of a superconducting memory cell device (100) comprising a ferromagnetic component (1 10), a non-ferromagnetic spacer layer (120), an additional ferromagnetic layer (130) and two superconducting electrodes (140).

The superconducting electrodes (140) are separated by a gap (150). The gap (150) could be a trench between the two superconducting electrodes (140), or could comprise a non- ferromagnetic spacer component between the two superconducting electrodes (140). In a further embodiment, the two superconducting electrodes (140) may be separated by the ferromagnetic component (1 10), such that the two superconducting electrodes (140) are located on different sides of the ferromagnetic component (140).

Each superconducting electrode (140) could be comprised of a 45 nm layer of niobium, although the thickness and material are not limited thereto.

The ferromagnetic component (1 10) may be a layer of a ferromagnetic material. The ferromagnetic component (110) is coupled between the two superconducting electrodes (140) to form a weak link between the superconducting electrodes (140). This configuration thereby forms a Josephson junction, wherein Cooper pairs (160) located in the superconducting electrodes (140) tunnel between the superconducting electrodes (140) via the ferromagnetic component (110) to form a supercurrent. The ferromagnetic component (1 10) provides a magnetic state configurable by an external bit setting means (as shown in the superconducting memory cell system of Figure 5), such as an external applied magnetic field or electromagnetic wave, into at least a first and second magnetic state.

In at least one of the first and second magnetic states, the ferromagnetic component is configured to convert, in use, spin singlet electron pairs to spin triplet electron pairs at locations on the Josephson junction to tunnel between the superconducting electrodes via the weak link, to generate a supercurrent having a critical current. The critical current of the first magnetic state is definable as a first bit state of the superconducting memory cell. The critical current of the second magnetic state is different from the critical current of the first magnetic state, and definable as a second bit state of the superconducting memory cell. In embodiments, the different magnetic states are defined so as to produce appropriately different measurable critical currents from the junction. Third or further definable magnetic states may be configured if the cell can reliably be entered into those states and three or more definably measurably different critical currents are provided by the different states.

The ferromagnetic component (1 10) provides a non-homogeneous spin configuration such that an in-plane exchange field gradient of a resulting magnetic vortex converts spin singlet electron pairs to spin triplet electron pairs. The ferromagnetic component (1 10) may contain at least one localised magnetic vortex core. A non-exhaustive list of examples of localised magnetic vortices include an out-of-plane magnetic vortex, a magnetic domain wall configuration, a skyrmion, or an in-plane magnetic defect.

The thickness, shape, form or another intrinsic or extrinsic characteristic of the ferromagnetic component (110) may be chosen to ensure stabilization of the at least one localised magnetic vortex core, such that the vortex is stable at rest or in absence of an external factor, such as an influence from the external bit setting means, or otherwise power to the memory cell. That is, where the magnetic states of the ferromagnetic component are stable, the cell may be pushed into that stable state by operation of the external bit setting means, but after the bit setting means ceases to operate or exert an influence on the ferromagnetic component, the ferromagnetic component retains its bit state.

Additionally, the at least one localised magnetic vortex core may have two or more stable positions. Multiple stable positions may be obtained by inserting one or more artificial defects in the ferromagnetic component (1 10), although the method of provision of multiple stable positions is not limited thereto. The ferromagnetic component may comprise a 60 nm thick disk of cobalt, although the shape, thickness and material are not limited thereto.

The additional ferromagnetic layer (130) generates triplet electron pairs and may be optimized for the triplet electron pair generation. The ferromagnetic layer may comprise a 1.5 nm thick layer of nickel, although the thickness and material are not limited thereto.

The non-ferromagnetic spacer layer (120) prevents exchange coupling between the additional ferromagnetic layer (130) and the ferromagnetic component (1 10). The non-ferromagnetic spacer layer may comprise a 5 nm thick layer of copper, although the thickness and material are not limited thereto. The Cooper pairs (160) in the superconducting electrodes (140) are converted into triplet pairs (170) in the ferromagnetic component (1 10) using the magnetization of the ferromagnetic component (1 10). In this embodiment, the magnetic spins of the additional ferromagnetic layer (130) and the magnetic spins of the ferromagnetic component (1 10) are non-collinear (in at least the magnetic configuration of the ferromagnetic component in which supercurrent is conducted by the junction), and it is this magnetic non-collinearity (MNC) which converts the Cooper pairs into spin electron triplet pairs to create the supercurrent.

Figure 1 b shows another embodiment of a superconducting memory cell device (180). Two superconducting electrodes (140) are directly atop a ferromagnetic component (1 10) which acts as a weak link between the superconducting electrodes (140). The superconducting electrodes (140) are separated by a gap (150) to form a Josephson junction. The superconducting electrodes (140), ferromagnetic component (1 10) and gap (150) work in the same manner as described above for Figure 1a. In this embodiment, a non-ferromagnetic spacer layer (120) and an additional ferromagnetic layer (130) are omitted.

In this embodiment, a non-homogeneous spin configuration of the magnetic moments in the ferromagnetic component (1 10) results in an in-plane exchange field gradient at a magnetic vortex, which generates the triplet pairs.

Figure 2a shows one possible embodiment of a magnetic configuration of a ferromagnetic component (210). In this embodiment, the magnetic spins (220) of the ferromagnetic component (210) are represented by arrows. The magnetic spins (220) lie in-plane and orthogonal to the gap (150) between the superconducting electrodes (140). In this instance, the shape of the disk of the ferromagnetic component results in a strong out of plane component in the centre of the disk (not shown) owing to the in-plane spins in the centre of the disk becoming frustrated and driven out-of-plane.

In a corresponding magnetic configuration of the additional ferromagnetic layer (130) (not shown), the magnetic spins would also lie in-plane but would be parallel to the gap (150). Micromagnetic simulations show that this geometry results in a well-defined ground state with a high degree of magnetic non-collinearity (MNC) - a condition optimal for generating spin triplet electron pairs.

Figure 2b shows another representation of the information shown in Figure 2a. The magnetization profile (230) is circular and in-plane across most of the ferromagnetic component (1 10). However, in the centre where the spins become frustrated, there is a localised magnetic vortex core (240) with a strong out-of-plane component. More than one localised magnetic vortex core may be present in the ferromagnetic component (1 10).

At the at least one localised magnetic vortex core, the MNC is strongly suppressed so no supercurrent is generated by the Josephson junction in that location. Therefore, two channels of supercurrent are generated - one on each side of the at least one localised magnetic vortex core. The MNC suppression is due to the local out-of-plane magnetization at the vortex core, which turns the magnetic spins in the additional ferromagnetic layer (130) out-of-plane, and hence collinear to the magnetic spins in the ferromagnetic component (1 10). For a system without the additional ferromagnetic layer (130), the in-plane exchange field gradient of the magnetic vortex generates spin triplet electron pairs.

The position of the at least one localised magnetic vortex core can be controlled using an external bit setting control means, wherein the external bit setting control means may include an external applied magnetic field or an applied electromagnetic wave. The amount of current generated by the device is therefore dependent upon the position of the at least one localised magnetic vortex core.

Additionally, the magnetic state of the entire ferromagnetic component can be controlled by operation of the external bit setting means into at least a first and a second magnetic state, wherein the first and second magnetic states are different magnetic states. When in use, the ferromagnetic component is configured such that in at least one of the first and second magnetic states, spin singlet electron pairs are converted to spin triplet electron pairs at locations on the Josephson junction to tunnel between the superconducting electrodes via the weak link, in order to generate a supercurrent having a critical current. The critical current of the first magnetic state is definable as a first bit state of the superconducting memory cell. The critical current of the second magnetic state is different from the critical current of the first magnetic state, and definable as a second bit state of the superconducting memory cell.

Figure 3a shows an example of how the maximum amount of generated supercurrent, otherwise known as the critical current, varies according to the size of a magnetic field applied, e.g. by an external bit setting means, in a superconducting memory cell comprising Nb superconducting electrodes (140), a Co ferromagnetic component (1 10), a Cu non- ferromagnetic spacer layer (120) and a Ni ferromagnetic layer (130) in accordance with the embodiment shown in Figure 1 a. The critical current is the maximum amount of supercurrent that can be generated before the supercurrent reverts to a normal resistive current and the Josephson junction is no longer in a superconducting state. The applied magnetic field alters the position of the localised magnetic vortex core, and so affects the location and size of the supercurrent channel generated on either side of the localised magnetic vortex core.

As the magnetic field increases applied by the external bit setting means, the localised magnetic vortex core may be pushed out of the device, which results in the critical current falling to zero as the supercurrent disappears (310). The critical current shows hysteretic behaviour, since the critical current in zero field for the reverse field sweep is quenched at zero amps, in contrast to the high critical current at zero field at the beginning of the first forward field sweep.

The critical current may be restored by sweeping the applied magnetic field to a negative magnetic field. The critical current increases to a first definable critical current (320) as the localised magnetic vortex core reaches a first definable state. The critical current then increases to a second definable critical current (330) as the localised magnetic vortex core reaches a second definable state. A zero critical current value could also be considered to be a definable critical current.

When the device is used as a storage device, if the critical current measured using a read-out means is determined to be a low critical current then this may equate to a bit state of 0. However, a high measured critical current value may equate to a bit state of 1 , or vice versa. Alternatively, if the measured critical current is determined to be above a predetermined threshold value then the bit state may be deemed to be 1 , whereas if the measured critical current is determined to be below a predetermined threshold value then the bit state may be deemed to be 0, or vice versa.

Figure 3b shows another example of hysteretic behaviour in the critical current at zero applied magnetic field in a superconducting memory cell device. In this embodiment, the superconducting memory cell is comprised of Nb superconducting electrodes (140) and a Co ferromagnetic component (1 10), but does not contain a non-ferromagnetic spacer layer (120) or an additional ferromagnetic layer (130), in accordance with the embodiment shown in Figure 1 b. In this embodiment, a first definable critical current (340) and a second definable critical current (350) can again be identified. The zero critical current value (360) could also be considered a definable critical current. Figure 4 shows additional critical current against applied magnetic field strengths, overlaid with images generated by micromagnetic simulations representing the corresponding degree of magnetic non collinearity (MNC) at locations across the surface of the junction disc. These measurements are performed in a superconducting memory cell comprising two Nb superconducting electrodes (140), a Co ferromagnetic component (1 10), a Cu non- ferromagnetic spacer layer (120) and a Ni ferromagnetic layer (130) which is configured to provide a high degree of magnetic non-collinearity with the ferromagnetic layer.

Figure 4a shows magnetic non-collinearity (MNC) simulations for the various magnetic states of the ferromagnetic component (1 10) and how they correspond to the different measured critical current values.

In the first section (410) of the critical current measurement, the vortex core (415) moves along the junction (150) of the superconducting memory cell, in a direction perpendicular to the magnetic field direction, towards the side of the ferromagnetic component (110). In the second section (420), the applied external magnetic field is sufficiently strong to push the vortex out of the ferromagnetic component (1 10). The vortex configuration, which has previously been effective in suppressing stray magnetic fields vanishes as the ferromagnetic component (110) continues to magnetise. This leads to a negative dipole field from the ferromagnetic component (110) which dominates the effective field acting on the additional ferromagnetic layer (130). As a result, the additional ferromagnetic layer (130) gets magnetized anti-parallel to the ferromagnetic component (1 10), and so the critical current and MNC are suppressed.

In the third section (430), the increasing applied magnetic field begins to compensate the contribution of the stray fields of the ferromagnetic component (1 10), which ultimately reverses the magnetization of the additional ferromagnetic layer (130). The change in the magnetic orientation associated with the reversal leads to a distinct re-emergence of MNC, and the critical current, which reduces above 60mT, as the magnetization of the additional ferromagnetic layer (130) aligns with the magnetization of the ferromagnetic component (1 10).

Figure 4b shows how the critical current varies for the device described in Figure 4a when the applied magnetic field is swept from a high positive field to a negative field and back. Hysteretic behaviour is clearly observed, with noticeable variations in the critical current values. The features of this pattern again correspond to the variation in MNC as different magnetic states are switched between, as described for Figure 4a. Figure 5 shows an example of an embodiment of a superconducting memory cell system (500) comprising the superconducting memory cell device (510) configured according to any of the embodiments described above. The system (500) further comprises a power supply device (520) that provides the current I for the superconducting memory cell device (510).

The system (500) may also comprise an external bit setting means (530) suitable for setting the bit state of the superconducting memory cell device (510). The external bit setting means (530) may use at least one of an external applied magnetic field or an applied electromagnetic wave in order to control the magnetic state of the ferromagnetic component (1 10), and thus the position of the at least one localised magnetic vortex core, and so set the bit state.

The superconducting memory cell system (500) may additionally comprise a read out means (540) for determining the bit state of the superconducting memory cell (510). The read out means (540) may measure the critical current generated across the superconducting memory cell (510). The read out means (540) may then determine the bit state of the superconducting memory cell (510) using the measured critical current value. In another embodiment, the critical current value measured by the read out means (540) may be transmitted to a determination means (not shown), wherein the determination means may determine the bit state of the superconducting memory cell (510) using the critical current value measured by the read out means (540).

One or more controllers may also be provided, configured to operate the bit setting means and the read out means to write to and read from the superconducting memory cell.

A plurality of superconducting memory cells (510) or cell systems (500) may be provided together to form a superconducting memory unit for storing multiple bits, wherein the plurality of superconducting memory cells (510) together form a superconducting memory unit capable of storing a plurality of bits. In this embodiment, the external bit setting means (530) may set the bit state of each of the plurality of superconducting memory cell devices (530). The read out means (540) may measure the critical current generated across each of the superconducting memory cells (510), from which the bit state of each of the superconducting memory cells (510) may be determined.

The above embodiments have been described by way of example only, and the described embodiments are to be considered in all respects only as illustrative and not restrictive. It will be appreciated that variations of the described embodiments may be made without departing from the scope of the invention which is indicated by the appended claims rather than by the foregoing description.