Title:
HYBRID-TYPE DATA TRANSMISSION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2010/131306
Kind Code:
A1
Abstract:
A data transmission unit (100) having a parallel/serial conversion function is supplied with a clock by a PLL circuit unit (200). In the PLL circuit unit (200), a first multi-phase clock to be given to a first parallel/serial conversion circuit (20a) is generated and outputted by a multi-phase VCO circuit (70), while a second multi-phase clock to be given to a second parallel/serial conversion circuit (20b) is generated and outputted by a multi-phase clock generation unit (80). The multi-phase clock generation unit (80) generates the second multi-phase clock based on the clock that is outputted from the multi-phase VCO circuit (70).
Inventors:
EBUCHI TSUYOSHI
KOMATSU YOSHIHIDE
KOMATSU YOSHIHIDE
Application Number:
PCT/JP2009/005458
Publication Date:
November 18, 2010
Filing Date:
October 19, 2009
Export Citation:
Assignee:
PANASONIC CORP (JP)
EBUCHI TSUYOSHI
KOMATSU YOSHIHIDE
EBUCHI TSUYOSHI
KOMATSU YOSHIHIDE
International Classes:
H04L25/02; H03M9/00
Foreign References:
| JP2007509522A | 2007-04-12 | |||
| JP2001209454A | 2001-08-03 | |||
| JP2001007686A | 2001-01-12 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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