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Patent Searching and Data


Title:
IMPROVED ARCHITECTURE WITH SHARED MEMORY
Document Type and Number:
WIPO Patent Application WO2003041119
Kind Code:
A3
Abstract:
A system with multiple processors sharing a single memory module without noticeable performance degradation is described. The memory module is divided into n independently addressable banks, where n is at least 2 and mapped such that sequential addresses are rotated between the banks. Such a mapping causes sequential data bytes to be stored in alternate banks. Each bank may be further divided into a plurality of blocks. By staggering or synchronizing the processors to execute the computer program such that each processor access a different block during the same cycle, the processors can access the memory simultaneously.

Inventors:
FRENZEL RUDI (DE)
HORAK CHRISTIAN (DE)
JAIN RAJ KUMAR (SG)
TERSCHLUSE MARKUS (DE)
UHLEMANN STEFAN (DE)
Application Number:
PCT/EP2002/012398
Publication Date:
January 29, 2004
Filing Date:
November 06, 2002
Export Citation:
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Assignee:
INFINEON TECHNOLOGIES AG (DE)
FRENZEL RUDI (DE)
HORAK CHRISTIAN (DE)
JAIN RAJ KUMAR (SG)
TERSCHLUSE MARKUS (DE)
UHLEMANN STEFAN (DE)
International Classes:
G06F9/46; G06F12/00; G06F12/06; H01L; (IPC1-7): G06F9/46; G06F12/06
Foreign References:
US3931613A1976-01-06
US5857110A1999-01-05
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