CROSS REFERENCE TO RELATED APPLICATION

[1] The present application claims priority to provisional application US 62/892,246 filed on August 27, 2019, and non-provisional application US 16/999,657 filed on August 21, 2020, which are hereby expressly incorporated by reference, in their entirety, into the present application.

BACKGROUND

1. Field

[2] The present disclosure is directed to improving bit-efficiency by a set of advanced video coding technologies including improved QT/BT/TT size syntaxes.

2. Description of Related Art

[3] ITU-T VCEG (Q6/16) and ISO/IEC MPEG (JTC 1/SC 29/WG 11) published the H.265/HEVC (High Efficiency Video Coding) standard in 2013 (version 1) 2014 (version 2) 2015 (version 3) and 2016 (version 4). In 2015, these two standard organizations jointly formed the JVET (Joint Video Exploration Team) to explore the potential of developing the next video coding standard beyond HEVC In October 2017, they issued the Joint Call for Proposals on Video Compression with Capability beyond HEVC (CfP). By February 15, 2018, total 22 CfP responses on standard dynamic range (SDR), 12 CfP responses on high dynamic range (HDR), and 12 CfP responses on 360 video categories were submitted, respectively. In April 2018, all received CfP responses were evaluated in the 122 MPEG / 10th JVET meeting. As a result of this meeting, JVET formally launched the standardization process of next-generation video coding beyond HEVC. The new standard was named Versatile Video Coding (VVC), and JVET was renamed as Joint Video Expert Team. The current version of VTM (VVC Test Model), i.e., VTM 6.

[4] In VVC Draft 6, there are some syntax elements which describe the size of QT/BT/TT, as shown in highlighted area in Table 1 and 2 below. Each of the aforementioned syntaxes specifies the default difference between the base 2 logarithm of two numbers.

Table 1. JVET-02001-vE “Sequence parameter set RBSP syntax”.

Table 2. JVET-02001-vE “General slice header syntax”.

[5] Viewing the above, consider taking syntax sps_log2_diff_min_qt_min_cb_intra_slice_luma as an example specifying the default difference between the base 2 logarithm of the minimum size in luma samples of a luma leaf block resulting from quadtree splitting of a CTU and the base 2 logarithm of the minimum coding block size in luma samples for luma CUs in slices. Thus, it shall be in the range of 0 to CtbLog2SizeY - MinCbLog2SizeY, inclusive. CtbLog2SizeY is derived as log2_ctu_size_minus5 + 5, so its value is within [5, 6, 7] when CTU size is 32x32, 64x64, and 128x128 respectively. Meanwhile, VVC Draft 6 specifies that the value of MinCbLog2SizeY is 2. Thus, the maximum value of sps_log2_diff_min_qt_min_cb_intra_slice_luma is within [3, 4, 5] depending on the CTU size.

[6] However, signaling a difference between max QT/BT/TT and min QT/CB is not bit- efficient, because the max value of QT/BT/TT is typically set to CTU size.

[7] Therefore, there is a desire for a technical solution to such problems. SUMMARY

[8] To address one or more different technical problems, this disclosure described new syntaxes and use thereof designed to describe QT/TT/BT size. According to embodiments, these syntaxes change the base from min CB/QT to CTU, and embodiments allow QT/TT/BT size to be signaled using smaller numbers. Thus, improved coding efficiency can be achieved.

[9] There is included a method and apparatus comprising memory configured to store computer program code and a processor or processors configured to access the computer program code and operate as instructed by the computer program code. The computer program code includes obtaining code configured to cause the at least one processor to obtain a coding tree unit (CTU) from video data, partitioning code configured to cause the at least one processor to partition the CTU by a quadtree structure, further partitioning code configured to cause the at least one processor to partition leaf nodes of the partitioned CTU by at least one of a binary tree structure and a ternary tree structure, and signaling code configured to cause the at least one processor to signal a difference, in base 2 logarithm, between at least one value and a size of a sample resulting from at least one of partitioning the CTU by the quadtree structure and partitioning leaf nodes of the partitioned CTU by the at least one of the binary tree structure and the ternary tree structure.

[10] According to embodiments, the at least one value comprises a size of the CTU.

[11] According to embodiments, the size of the sample is a base 2 logarithm of a minimum size in luma samples of a luma leaf block resulting from partitioning the CTU by the quadtree structure. [12] According to embodiments, the size of the sample is a base 2 logarithm of a maximum size in luma samples of a luma coding block resulting from partitioning the leaf nodes of the partitioned CTU by the binary tree structure.

[13] According to embodiments, the size of the sample is a base 2 logarithm of a maximum size in luma samples of a luma coding block resulting from partitioning the leaf nodes of the partitioned CTU by the ternary tree structure.

[14] According to embodiments, the size of the sample is a base 2 logarithm of a maximum size of a chroma coding block resulting from partitioning the leaf nodes of the partitioned CTU by the binary tree structure.

[15] According to embodiments, the size of the sample is a base 2 logarithm of a maximum size of a chroma coding block resulting from partitioning the leaf nodes of the partitioned CTU by the ternary tree structure.

[16] According to embodiments, wherein the size of the sample is a base 2 logarithm of a minimum size of a chroma leaf block resulting from partitioning the CTU by the quadtree structure.

[17] According to embodiments, wherein the at least one value comprises minimum size of a coding block (CB) of the CTU.

[18] According to embodiments, the at least one value is a predetermined value.

BRIEF DESCRIPTION OF THE DRAWINGS

[19] Further features, nature, and various advantages of the disclosed subject matter will be more apparent from the following detailed description and the accompanying drawings in which:

[20] Fig. l is a simplified illustration of in accordance with embodiments. [21] Fig. 2 is a schematic diagram in accordance with embodiments.

[22] Fig. 3 is a schematic diagram in accordance with embodiments.

[23] Fig. 4 is a schematic diagram in accordance with embodiments.

[24] Fig. 5 is a simplified illustration in accordance with embodiments.

[25] Fig. 6 is a simplified illustration in accordance with embodiments.

[26] Fig. 7 is a simplified illustration in accordance with embodiments.

[27] Fig. 8 is a simplified illustration in accordance with embodiments.

[28] Fig. 9A is a simplified illustration in accordance with embodiments.

[29] Fig. 9B is a simplified illustration in accordance with embodiments.

[30] Fig. 10A is a simplified illustration in accordance with embodiments.

[31] Fig. 1 OB is a simplified illustration in accordance with embodiments.

[32] Fig. IOC is a simplified illustration in accordance with embodiments.

[33] Fig. 11 is a simplified flow illustration in accordance with embodiments.

[34] Fig. 12 is a schematic illustration of a diagram in accordance with embodiments.

DETAILED DESCRIPTION

[35] The proposed features discussed below may be used separately or combined in any order. Further, the embodiments may be implemented by processing circuitry (e.g., one or more processors or one or more integrated circuits). In one example, the one or more processors execute a program that is stored in a non-transitory computer-readable medium. [36] Fig. 1 illustrates a simplified block diagram of a communication system 100 according to an embodiment of the present disclosure. The communication system 100 may include at least two terminals 102 and 103 interconnected via a network 105. For unidirectional transmission of data, a first terminal 103 may code video data at a local location for transmission to the other terminal 102 via the network 105. The second terminal 102 may receive the coded video data of the other terminal from the network 105, decode the coded data and display the recovered video data. Unidirectional data transmission may be common in media serving applications and the like.

[37] Fig. 1 illustrates a second pair of terminals 101 and 104 provided to support bidirectional transmission of coded video that may occur, for example, during videoconferencing. For bidirectional transmission of data, each terminal 101 and 104 may code video data captured at a local location for transmission to the other terminal via the network 105. Each terminal 101 and 104 also may receive the coded video data transmitted by the other terminal, may decode the coded data and may display the recovered video data at a local display device.

[38] In Fig. 1, the terminals 101, 102, 103 and 104 may be illustrated as servers, personal computers and smart phones but the principles of the present disclosure are not so limited. Embodiments of the present disclosure find application with laptop computers, tablet computers, media players and/or dedicated video conferencing equipment. The network 105 represents any number of networks that convey coded video data among the terminals 101, 102, 103 and 104, including for example wireline and/or wireless communication networks. The communication network 105 may exchange data in circuit-switched and/or packet-switched channels. Representative networks include telecommunications networks, local area networks, wide area networks and/or the Internet. For the purposes of the present discussion, the architecture and topology of the network 105 may be immaterial to the operation of the present disclosure unless explained herein below.

[39] Fig. 2 illustrates, as an example for an application for the disclosed subject matter, the placement of a video encoder and decoder in a streaming environment. The disclosed subject matter can be equally applicable to other video enabled applications, including, for example, video conferencing, digital TV, storing of compressed video on digital media including CD, DVD, memory stick and the like, and so on.

[40] A streaming system may include a capture subsystem 203, that can include a video source 201, for example a digital camera, creating, for example, an uncompressed video sample stream 213. That sample stream 213 may be emphasized as a high data volume when compared to encoded video bitstreams and can be processed by an encoder 202 coupled to the camera 201. The encoder 202 can include hardware, software, or a combination thereof to enable or implement aspects of the disclosed subject matter as described in more detail below. The encoded video bitstream 204, which may be emphasized as a lower data volume when compared to the sample stream, can be stored on a streaming server 205 for future use. One or more streaming clients 212 and 207 can access the streaming server 205 to retrieve copies 208 and 206 of the encoded video bitstream 204. A client 212 can include a video decoder 211 which decodes the incoming copy of the encoded video bitstream 208 and creates an outgoing video sample stream 210 that can be rendered on a display 209 or other rendering device (not depicted). In some streaming systems, the video bitstreams 204, 206 and 208 can be encoded according to certain video coding/compression standards. Examples of those standards are noted above and described further herein. [41] Fig. 3 may be a functional block diagram of a video decoder 300 according to an embodiment of the present invention.

[42] A receiver 302 may receive one or more codec video sequences to be decoded by the decoder 300; in the same or another embodiment, one coded video sequence at a time, where the decoding of each coded video sequence is independent from other coded video sequences. The coded video sequence may be received from a channel 301, which may be a hardware/software link to a storage device which stores the encoded video data. The receiver 302 may receive the encoded video data with other data, for example, coded audio data and/or ancillary data streams, that may be forwarded to their respective using entities (not depicted). The receiver 302 may separate the coded video sequence from the other data. To combat network jitter, a buffer memory 303 may be coupled in between receiver 302 and entropy decoder / parser 304 (“parser” henceforth). When receiver 302 is receiving data from a store/forward device of sufficient bandwidth and controllability, or from an isosychronous network, the buffer 303 may not be needed, or can be small. For use on best effort packet networks such as the Internet, the buffer 303 may be required, can be comparatively large and can advantageously of adaptive size.

[43] The video decoder 300 may include a parser 304 to reconstruct symbols 313 from the entropy coded video sequence. Categories of those symbols include information used to manage operation of the decoder 300, and potentially information to control a rendering device such as a display 312 that is not an integral part of the decoder but can be coupled to it. The control information for the rendering device(s) may be in the form of Supplementary Enhancement Information (SEI messages) or Video Usability Information parameter set fragments (not depicted). The parser 304 may parse / entropy-decode the coded video sequence received. The coding of the coded video sequence can be in accordance with a video coding technology or standard, and can follow principles well known to a person skilled in the art, including variable length coding, Huffman coding, arithmetic coding with or without context sensitivity, and so forth. The parser 304 may extract from the coded video sequence, a set of subgroup parameters for at least one of the subgroups of pixels in the video decoder, based upon at least one parameters corresponding to the group. Subgroups can include Groups of Pictures (GOPs), pictures, tiles, slices, macroblocks, Coding Units (CUs), blocks, Transform Units (TUs), Prediction Units (PUs) and so forth. The entropy decoder / parser may also extract from the coded video sequence information such as transform coefficients, quantizer parameter values, motion vectors, and so forth.

[44] The parser 304 may perform entropy decoding / parsing operation on the video sequence received from the buffer 303, so to create symbols 313. The parser 304 may receive encoded data, and selectively decode particular symbols 313. Further, the parser 304 may determine whether the particular symbols 313 are to be provided to a Motion Compensation Prediction unit 306, a scaler / inverse transform unit 305, an Intra Prediction Unit 307, or a loop filter 311.

[45] Reconstruction of the symbols 313 can involve multiple different units depending on the type of the coded video picture or parts thereof (such as: inter and intra picture, inter and intra block), and other factors. Which units are involved, and how, can be controlled by the subgroup control information that was parsed from the coded video sequence by the parser 304. The flow of such subgroup control information between the parser 304 and the multiple units below is not depicted for clarity.

[46] Beyond the functional blocks already mentioned, decoder 300 can be conceptually subdivided into a number of functional units as described below. In a practical implementation operating under commercial constraints, many of these units interact closely with each other and can, at least partly, be integrated into each other. However, for the purpose of describing the disclosed subject matter, the conceptual subdivision into the functional units below is appropriate.

[47] A first unit is the scaler / inverse transform unit 305. The scaler / inverse transform unit 305 receives quantized transform coefficient as well as control information, including which transform to use, block size, quantization factor, quantization scaling matrices, etc. as symbol(s) 313 from the parser 304. It can output blocks comprising sample values, that can be input into aggregator 310.

[48] In some cases, the output samples of the scaler / inverse transform 305 can pertain to an intra coded block; that is: a block that is not using predictive information from previously reconstructed pictures, but can use predictive information from previously reconstructed parts of the current picture. Such predictive information can be provided by an intra picture prediction unit 307. In some cases, the intra picture prediction unit 307 generates a block of the same size and shape of the block under reconstruction, using surrounding already reconstructed information fetched from the current (partly reconstructed) picture 309. The aggregator 310, in some cases, adds, on a per sample basis, the prediction information the intra prediction unit 307 has generated to the output sample information as provided by the scaler / inverse transform unit 305.

[49] In other cases, the output samples of the scaler / inverse transform unit 305 can pertain to an inter coded, and potentially motion compensated block. In such a case, a Motion Compensation Prediction unit 306 can access reference picture memory 308 to fetch samples used for prediction. After motion compensating the fetched samples in accordance with the symbols 313 pertaining to the block, these samples can be added by the aggregator 310 to the output of the scaler / inverse transform unit (in this case called the residual samples or residual signal) so to generate output sample information. The addresses within the reference picture memory form where the motion compensation unit fetches prediction samples can be controlled by motion vectors, available to the motion compensation unit in the form of symbols 313 that can have, for example X, Y, and reference picture components. Motion compensation also can include interpolation of sample values as fetched from the reference picture memory when sub sample exact motion vectors are in use, motion vector prediction mechanisms, and so forth.

[50] The output samples of the aggregator 310 can be subject to various loop filtering techniques in the loop filter unit 311. Video compression technologies can include in-loop filter technologies that are controlled by parameters included in the coded video bitstream and made available to the loop filter unit 311 as symbols 313 from the parser 304, but can also be responsive to meta-information obtained during the decoding of previous (in decoding order) parts of the coded picture or coded video sequence, as well as responsive to previously reconstructed and loop-filtered sample values.

[51] The output of the loop filter unit 311 can be a sample stream that can be output to the render device 312 as well as stored in the reference picture memory 557 for use in future inter picture prediction.

[52] Certain coded pictures, once fully reconstructed, can be used as reference pictures for future prediction. Once a coded picture is fully reconstructed and the coded picture has been identified as a reference picture (by, for example, parser 304), the current reference picture 309 can become part of the reference picture buffer 308, and a fresh current picture memory can be reallocated before commencing the reconstruction of the following coded picture. [53] The video decoder 300 may perform decoding operations according to a predetermined video compression technology that may be documented in a standard, such as ITU-T Rec. H.265. The coded video sequence may conform to a syntax specified by the video compression technology or standard being used, in the sense that it adheres to the syntax of the video compression technology or standard, as specified in the video compression technology document or standard and specifically in the profiles document therein. Also necessary for compliance can be that the complexity of the coded video sequence is within bounds as defined by the level of the video compression technology or standard. In some cases, levels restrict the maximum picture size, maximum frame rate, maximum reconstruction sample rate (measured in, for example megasamples per second), maximum reference picture size, and so on. Limits set by levels can, in some cases, be further restricted through Hypothetical Reference Decoder (HRD) specifications and metadata for HRD buffer management signaled in the coded video sequence.

[54] In an embodiment, the receiver 302 may receive additional (redundant) data with the encoded video. The additional data may be included as part of the coded video sequence(s). The additional data may be used by the video decoder 300 to properly decode the data and/or to more accurately reconstruct the original video data. Additional data can be in the form of, for example, temporal, spatial, or signal-to-noise ratio (SNR) enhancement layers, redundant slices, redundant pictures, forward error correction codes, and so on.

[55] Fig. 4 may be a functional block diagram of a video encoder 400 according to an embodiment of the present disclosure.

[56] The encoder 400 may receive video samples from a video source 401 (that is not part of the encoder) that may capture video image(s) to be coded by the encoder 400. [57] The video source 401 may provide the source video sequence to be coded by the encoder (303) in the form of a digital video sample stream that can be of any suitable bit depth (for example: 8 bit, 10 bit, 12 bit, ...), any colorspace (for example, BT.601 Y CrCB, RGB, ...) and any suitable sampling structure (for example Y CrCb 4:2:0, Y CrCb 4:4:4). In a media serving system, the video source 401 may be a storage device storing previously prepared video. In a videoconferencing system, the video source 401 may be a camera that captures local image information as a video sequence. Video data may be provided as a plurality of individual pictures that impart motion when viewed in sequence. The pictures themselves may be organized as a spatial array of pixels, wherein each pixel can comprise one or more samples depending on the sampling structure, color space, etc. in use. A person skilled in the art can readily understand the relationship between pixels and samples. The description below focuses on samples.

[58] According to an embodiment, the encoder 400 may code and compress the pictures of the source video sequence into a coded video sequence 410 in real time or under any other time constraints as required by the application. Enforcing appropriate coding speed is one function of Controller 402. Controller controls other functional units as described below and is functionally coupled to these units. The coupling is not depicted for clarity. Parameters set by controller can include rate control related parameters (picture skip, quantizer, lambda value of rate-distortion optimization techniques, ...), picture size, group of pictures (GOP) layout, maximum motion vector search range, and so forth. A person skilled in the art can readily identify other functions of controller 402 as they may pertain to video encoder 400 optimized for a certain system design.

[59] Some video encoders operate in what a person skilled in the art readily recognizes as a “coding loop.” As an oversimplified description, a coding loop can consist of the encoding part of an encoder 402 (“source coder” henceforth) (responsible for creating symbols based on an input picture to be coded, and a reference picture(s)), and a (local) decoder 406 embedded in the encoder 400 that reconstructs the symbols to create the sample data that a (remote) decoder also would create (as any compression between symbols and coded video bitstream is lossless in the video compression technologies considered in the disclosed subject matter). That reconstructed sample stream is input to the reference picture memory 405. As the decoding of a symbol stream leads to bit-exact results independent of decoder location (local or remote), the reference picture buffer content is also bit exact between local encoder and remote encoder. In other words, the prediction part of an encoder “sees” as reference picture samples exactly the same sample values as a decoder would “see” when using prediction during decoding. This fundamental principle of reference picture synchronicity (and resulting drift, if synchronicity cannot be maintained, for example because of channel errors) is well known to a person skilled in the art.

[60] The operation of the “local” decoder 406 can be the same as of a “remote” decoder 300, which has already been described in detail above in conjunction with Fig. 3. Briefly referring also to Fig. 4, however, as symbols are available and en/decoding of symbols to a coded video sequence by entropy coder 408 and parser 304 can be lossless, the entropy decoding parts of decoder 300, including channel 301, receiver 302, buffer 303, and parser 304 may not be fully implemented in local decoder 406.

[61] An observation that can be made at this point is that any decoder technology except the parsing/entropy decoding that is present in a decoder also necessarily needs to be present, in substantially identical functional form, in a corresponding encoder. The description of encoder technologies can be abbreviated as they are the inverse of the comprehensively described decoder technologies. Only in certain areas a more detail description is required and provided below.

[62] As part of its operation, the source coder 403 may perform motion compensated predictive coding, which codes an input frame predictively with reference to one or more previously-coded frames from the video sequence that were designated as “reference frames.” In this manner, the coding engine 407 codes differences between pixel blocks of an input frame and pixel blocks of reference frame(s) that may be selected as prediction reference(s) to the input frame.

[63] The local video decoder 406 may decode coded video data of frames that may be designated as reference frames, based on symbols created by the source coder 403. Operations of the coding engine 407 may advantageously be lossy processes. When the coded video data may be decoded at a video decoder (not shown in Fig. 4), the reconstructed video sequence typically may be a replica of the source video sequence with some errors. The local video decoder 406 replicates decoding processes that may be performed by the video decoder on reference frames and may cause reconstructed reference frames to be stored in the reference picture cache 405. In this manner, the encoder 400 may store copies of reconstructed reference frames locally that have common content as the reconstructed reference frames that will be obtained by a far-end video decoder (absent transmission errors).

[64] The predictor 404 may perform prediction searches for the coding engine 407. That is, for a new frame to be coded, the predictor 404 may search the reference picture memory 405 for sample data (as candidate reference pixel blocks) or certain metadata such as reference picture motion vectors, block shapes, and so on, that may serve as an appropriate prediction reference for the new pictures. The predictor 404 may operate on a sample block-by-pixel block basis to find appropriate prediction references. In some cases, as determined by search results obtained by the predictor 404, an input picture may have prediction references drawn from multiple reference pictures stored in the reference picture memory 405.

[65] The controller 402 may manage coding operations of the video coder 403, including, for example, setting of parameters and subgroup parameters used for encoding the video data.

[66] Output of all aforementioned functional units may be subjected to entropy coding in the entropy coder 408. The entropy coder translates the symbols as generated by the various functional units into a coded video sequence, by lossdess compressing the symbols according to technologies known to a person skilled in the art as, for example Huffman coding, variable length coding, arithmetic coding, and so forth.

[67] The transmitter 409 may buffer the coded video sequence(s) as created by the entropy coder 408 to prepare it for transmission via a communication channel 411, which may be a hardware/software link to a storage device which would store the encoded video data. The transmitter 409 may merge coded video data from the video coder 403 with other data to be transmitted, for example, coded audio data and/or ancillary data streams (sources not shown).

[68] The controller 402 may manage operation of the encoder 400. During coding, the controller 405 may assign to each coded picture a certain coded picture type, which may affect the coding techniques that may be applied to the respective picture. For example, pictures often may be assigned as one of the following frame types:

[69] An Intra Picture (I picture) may be one that may be coded and decoded without using any other frame in the sequence as a source of prediction. Some video codecs allow for different types of Intra pictures, including, for example Independent Decoder Refresh Pictures. A person skilled in the art is aware of those variants of I pictures and their respective applications and features.

[70] A Predictive picture (P picture) may be one that may be coded and decoded using intra prediction or inter prediction using at most one motion vector and reference index to predict the sample values of each block.

[71] A Bi-directionally Predictive Picture (B Picture) may be one that may be coded and decoded using intra prediction or inter prediction using at most two motion vectors and reference indices to predict the sample values of each block. Similarly, multiple-predictive pictures can use more than two reference pictures and associated metadata for the reconstruction of a single block.

[72] Source pictures commonly may be subdivided spatially into a plurality of sample blocks (for example, blocks of 4 x 4, 8 x 8, 4 x 8, or 16 x 16 samples each) and coded on a block-by block basis. Blocks may be coded predictively with reference to other (already coded) blocks as determined by the coding assignment applied to the blocks’ respective pictures. For example, blocks of I pictures may be coded non-predictively or they may be coded predictively with reference to already coded blocks of the same picture (spatial prediction or intra prediction).

Pixel blocks of P pictures may be coded non-predictively, via spatial prediction or via temporal prediction with reference to one previously coded reference pictures. Blocks of B pictures may be coded non-predictively, via spatial prediction or via temporal prediction with reference to one or two previously coded reference pictures.

[73] The video coder 400 may perform coding operations according to a predetermined video coding technology or standard, such as ITU-T Rec. H.265. In its operation, the video coder 400 may perform various compression operations, including predictive coding operations that exploit temporal and spatial redundancies in the input video sequence. The coded video data, therefore, may conform to a syntax specified by the video coding technology or standard being used.

[74] In an embodiment, the transmitter 409 may transmit additional data with the encoded video. The source coder 403 may include such data as part of the coded video sequence. Additional data may comprise temporal/spatial/SNR enhancement layers, other forms of redundant data such as redundant pictures and slices, Supplementary Enhancement Information (SEI) messages, Visual Usability Information (VUI) parameter set fragments, and so on.

[75] Fig. 5 illustrates intra prediction modes used in HEVC and JEM. To capture the arbitrary edge directions presented in natural video, the number of directional intra modes is extended from 33, as used in HEVC, to 65. The additional directional modes in JEM on top of HEVC are depicted as dotted arrows in Figure 1 (b), and the planar and DC modes remain the same. These denser directional intra prediction modes apply for all block sizes and for both luma and chroma intra predictions. As shown in Fig. 5, the directional intra prediction modes as identified by dotted arrows, which is associated with an odd intra prediction mode index, are called odd intra prediction modes. The directional intra prediction modes as identified by solid arrows, which are associated with an even intra prediction mode index, are called even intra prediction modes. In this document, the directional intra prediction modes, as indicated by solid or dotted arrows in Fig. 5 are also referred as angular modes.

[76] In JEM, a total of 67 intra prediction modes are used for luma intra prediction. To code an intra mode, an most probable mode (MPM) list of size 6 is built based on the intra modes of the neighboring blocks. If intra mode is not from the MPM list, a flag is signaled to indicate whether intra mode belongs to the selected modes. In JEM-3.0, there are 16 selected modes, which are chosen uniformly as every fourth angular mode. In JVET-D0114 and JVET-G0060,

16 secondary MPMs are derived to replace the uniformly selected modes.

[77] Fig. 6 illustrates N reference tiers exploited for intra directional modes. There is a block unit 611, a segment A 601, a segment B 602, a segment C 603, a segment D 604, a segment E 605, a segment F 606, a first reference tier 610, a second reference tier 609, a third reference tier 608 and a fourth reference tier 607.

[78] In both HEVC and JEM, as well as some other standards such as H.264/AVC, the reference samples used for predicting the current block are restricted to a nearest reference line (row or column). In the method of multiple reference line intra prediction, the number of candidate reference lines (row or columns) are increased from one (i.e. the nearest) to N for the intra directional modes, where N is an integer greater than or equal to one. Fig. 2 takes 4x4 prediction unit (PU) as an example to show the concept of the multiple line intra directional prediction method. An intra-directi onal mode could arbitrarily choose one of N reference tiers to generate the predictors. In other words, the predictor p(x,y) is generated from one of the reference samples SI, S2, ..., and SN. A flag is signaled to indicate which reference tier is chosen for an intra-directional mode. If N is set as 1, the intra directional prediction method is the same as the traditional method in JEM 2.0. In Fig. 6, the reference lines 610, 609, 608 and 607 are composed of six segments 601, 602, 603, 604, 605 and 606 together with the top-left reference sample. In this document, a reference tier is also called a reference line. The coordinate of the top-left pixel within current block unit is (0,0) and the top left pixel in the 1st reference line is (-1,-1).

[79] In JEM, for the luma component, the neighboring samples used for intra prediction sample generations are filtered before the generation process. The filtering is controlled by the given intra prediction mode and transform block size. If the intra prediction mode is DC or the transform block size is equal to 4x4, neighboring samples are not filtered. If the distance between the given intra prediction mode and vertical mode (or horizontal mode) is larger than predefined threshold, the filtering process is enabled. For neighboring sample filtering, [1, 2, 1] filter and bi-linear filters are used.

[80] A position dependent intra prediction combination (PDPC) method is an intra prediction method which invokes a combination of the un-filtered boundary reference samples and HEVC style intra prediction with filtered boundary reference samples. Each prediction sample pred[x\\y\ located at (x,y) is calculated as follows: where R _x, -i,R-i _,y represent the unfiltered reference samples located at top and left of current sample (x, y), respectively, and R-i _, -i represents the unfiltered reference sample located at the top-left corner of the current block. The weightings are calculated as below, wT = 32 » ((y « 1) » shift ) (Eq. 2-2) wL = 32 » ((x « 1) » shift ) (Eq. 2-3) wTL = —(yvL » 4) — (wT » 4) (Eq. 2-4) shift = Qog2(width ) + log2(height ) + 2) » 2 (Eq. 2-5).

[81] Fig. 7 illustrates a diagram 700 in which DC mode PDPC weights (wL, wT, wTL) for (0, 0) and (1, 0) positions inside one 4x4 block. If PDPC is applied to DC, planar, horizontal, and vertical intra modes, additional boundary filters are not needed, such as the HEVC DC mode boundary filter or horizontal/vertical mode edge filters. Fig. 7 illustrates the definition of reference samples Rx,-1, R-l,y and R-1,-1 for PDPC applied to the top-right diagonal mode. The prediction sample pred(x’, y’) is located at (x’, y’) within the prediction block. The coordinate x of the reference sample Rx,-1 is given by: x = x’ + y’ + 1, and the coordinate y of the reference sample R-l,y is similarly given by: y = x’ + y’ + 1.

[82] Fig. 8 illustrates a Local Illumination Compensation (LIC) diagram 800 and is based on a linear model for illumination changes, using a scaling factor a and an offset b. And it is enabled or disabled adaptively for each inter-mode coded coding unit (CU).

[83] When LIC applies for a CU, a least square error method is employed to derive the parameters a and b by using the neighboring samples of the current CU and their corresponding reference samples. More specifically, as illustrated in Figure 8, the subsampled (2:1 subsampling) neighboring samples of the CU and the corresponding samples (identified by motion information of the current CU or sub-CU) in the reference picture are used. The IC parameters are derived and applied for each prediction direction separately.

[84] When a CU is coded with merge mode, the LIC flag is copied from neighboring blocks, in a way similar to motion information copy in merge mode; otherwise, an LIC flag is signaled for the CU to indicate whether LIC applies or not.

[85] Fig. 9A illustrates intra prediction modes 900 used in HEVC. In HEVC, there are total 35 intra prediction modes, among which mode 10 is horizontal mode, mode 26 is vertical mode, and mode 2, mode 18 and mode 34 are diagonal modes. The intra prediction modes are signaled by three most probable modes (MPMs) and 32 remaining modes.

[86] Fig. 9B illustrates, in embodiments of VVC, there are total 87 intra prediction modes where mode 18 is horizontal mode, mode 50 is vertical mode, and mode 2, mode 34 and mode 66 are diagonal modes. Modes -1 ~ -10 and Modes 67 ~ 76 are called Wide-Angle Intra Prediction (WAIP) modes. [87] The prediction sample pred(x,y) located at position (x, y) is predicted using an intra prediction mode (DC, planar, angular) and a linear combination of reference samples according to the PDPC expression: pred(x,y) = ( wL x R-l,y + wT x Rx,-1 - wTL x R-1,-1 + (64 - wL - wT + wTL) x pred(x,y) + 32 ) » 6 where Rx,-1, R-l,y represent the reference samples located at the top and left of current sample (x, y), respectively, and R-1,-1 represents the reference sample located at the top-left comer of the current block.

[88] For the DC mode the weights are calculated as follows for a block with dimensions width and height: wT = 32 » ( ( y«l ) » nScale ), wL = 32 » ( ( x«l ) » nScale ), wTL = ( wL»4 ) + ( wT»4 ), with nScale = ( log2( width ) - 2 + log2( height ) - 2 + 2 ) » 2, where wT denotes the weighting factor for the reference sample located in the above reference line with the same horizontal coordinate, wL denotes the weighting factor for the reference sample located in the left reference line with the same vertical coordinate, and wTL denotes the weighting factor for the top-left reference sample of the current block, nScale specifies how fast weighting factors decrease along the axis (wL decreasing from left to right or wT decreasing from top to bottom), namely weighting factor decrement rate, and it is the same along x-axis (from left to right) and y- axis (from top to bottom) in current design. And 32 denotes the initial weighting factors for the neighboring samples, and the initial weighting factor is also the top (left or top-left) weightings assigned to top-left sample in current CB, and the weighting factors of neighboring samples in PDPC process should be equal to or less than this initial weighting factor. [89] For planar mode wTL = 0, while for horizontal mode wTL = wT and for vertical mode wTL = wL. The PDPC weights can be calculated with adds and shifts only. The value of pred(x,y) can be computed in a single step using Eq. 1.

[90] Herein the proposed methods may be used separately or combined in any order. Further, each of the methods (or embodiments), encoder, and decoder may be implemented by processing circuitry (e.g., one or more processors or one or more integrated circuits). In one example, the one or more processors execute a program that is stored in a non-transitory computer-readable medium. In the following, the term block may be interpreted as a prediction block, a coding block, or a coding unit, i.e. CU.

[91] Fig. 10A illustrates an example 1000 of block partitioning by using QTBT, and Fig. 10B illustrates the corresponding tree representation 1001. The solid lines indicate quadtree splitting and dotted lines indicate binary tree splitting. In each splitting (i.e., non-leaf) node of the binary tree, one flag is signaled to indicate which splitting type (i.e., horizontal or vertical) is used, where 0 indicates horizontal splitting and 1 indicates vertical splitting. For the quadtree splitting, there is no need to indicate the splitting type since quadtree splitting always splits a block both horizontally and vertically to produce 4 sub-blocks with an equal size.

[92] In HEVC, a CTU is split into CUs by using a quadtree structure denoted as coding tree to adapt to various local characteristics. The decision on whether to code a picture area using inter picture (temporal) or intra-picture (spatial) prediction is made at the CU level. Each CU can be further split into one, two or four PUs according to the PU splitting type. Inside one PU, the same prediction process is applied and the relevant information is transmitted to the decoder on a PU basis. After obtaining the residual block by applying the prediction process based on the PU splitting type, a CU can be partitioned into transform units (TUs) according to another quadtree structure like the coding tree for the CU. One of key features of the HEVC structure is that it has the multiple partition conceptions including CU, PU, and TU.

[93] According to embodiments, the QTBT structure removes the concepts of multiple partition types, i.e. it removes the separation of the CU, PU and TU concepts, and supports more flexibility for CU partition shapes. In the QTBT block structure, a CU can have either a square or rectangular shape. At the flow diagram 1100 of Fig. 11, according to exemplary embodiments, a coding tree unit (CTU) or CU, obtained at SI 1, is first partitioned by a quadtree structure at S12. The quadtree leaf nodes are further determined whether to be partitioned by a binary tree structure at S14, and if so, at S15, as described with Fig. IOC for example, there are two splitting types, symmetric horizontal splitting and symmetric vertical splitting, in the binary tree splitting. The binary tree leaf nodes are called coding units (CUs), and that segmentation is used for prediction and transform processing without any further partitioning. This means that the CU, PU and TU have the same block size in the QTBT coding block structure. In VVC, a CU sometimes consists of coding blocks (CBs) of different color components, e.g. one CU contains one luma CB and two chroma CBs in the case of P and B slices of the 4:2:0 chroma format and sometimes consists of a CB of a single component, e.g., one CU contains only one luma CB or just two chroma CBs in the case of I slices.

[94] According to embodiments, the following parameters are defined for the QTBT partitioning scheme:

- CTU size: the root node size of a quadtree, the same concept as in HEVC,

- MinQTSize: the minimum allowed quadtree leaf node size,

- MaxBTSize: the maximum allowed binary tree root node size,

- MaxBTDepth: the maximum allowed binary tree depth, and - MinBTSize: the minimum allowed binary tree leaf node size.

[95] In one example of the QTBT partitioning structure, the CTU size is set as 128x128 luma samples with two corresponding 64x64 blocks of chroma samples, the MinQTSize, where QT is Quad Tree, is set as 16x16, the MaxBTSize is set as 64x64, the MinBTSize (for both width and height) is set as 4x4, and the MaxBTDepth is set as 4. The quadtree partitioning is applied to the CTU first to generate quadtree leaf nodes at S 12 or SI 5. The quadtree leaf nodes may have a size from 16x16 (i.e., the MinQTSize) to 128x128 (i.e., the CTU size). If the leaf quadtree node is 128x128, it will not be further split by the binary tree since the size exceeds the MaxBTSize (i.e., 64x64) as checked at S14. Otherwise, the leaf quadtree node could be further partitioned by the binary tree at S15. Therefore, the quadtree leaf node is also the root node for the binary tree and it has the binary tree depth as 0. When the binary tree depth reaches MaxBTDepth (i.e., 4), no further splitting is considered at S14. When the binary tree node has width equal to MinBTSize (i.e., 4), no further horizontal splitting is considered at S14. Similarly, when the binary tree node has height equal to MinBTSize, no further vertical splitting is considered at S14. Signals at S16 are provided, as discussed below with respect to syntaxes which describe QT/TT/BT size, for the procession such as for the leaf nodes of the binary tree that are further processed by prediction and transform processing, at S17 and similarly as discussed herein with respect to such prediction and transform processing, without any further partitioning. Such signaling may also be provided at S13 after S12 as shown in Fig. 11 according to exemplary embodiments. In the JEM, the maximum CTU size is 256x256 luma samples.

[96] In addition according to embodiments, a QTBT scheme supports the ability/flexibility for the luma and chroma to have a separate QTBT structure. Currently, for P and B slices, the luma and chroma coding tree blocks (CTBs) in one CTU share the same QTBT structure. However, for I slices, the luma CTB is partitioned into CUs by a QTBT structure, and the chroma CTBs are partitioned into chroma CUs by another QTBT structure. This means that a CU in an I slice consists of a coding block of the luma component or coding blocks of two chroma components, and a CU in a P or B slice consists of coding blocks of all three color components.

[97] In HEVC, inter prediction for small blocks is restricted to reduce the memory access of motion compensation, such that bi-prediction is not supported for 4x8 and 8x4 blocks, and inter prediction is not supported for 4x4 blocks. In the QTBT as implemented in the JEM-7.0, these restrictions are removed.

[98] Fig. IOC represents a simplified block diagram 1100 VVC with respect to a Multi -type- tree (MTT) structure 1002 that is included, which is a combination of the illustrated a quadtree (QT) with nested binary trees (BT) and triple- / ternary trees (TT), a QT/BT/TT. A CTU or CU is first partitioned recursively by a QT into square shaped blocks. Each QT leaf may then be further partitioned by a BT or TT, where BT and TT splits can be applied recursively and interleaved but no further QT partitioning can be applied. In all relevant proposals, the TT splits a rectangular block vertically or horizontally into three blocks using a 1:2:1 ratio (thus avoiding non-power-of-two widths and heights). For partition emulation prevention, additional split constraints are typically imposed on the MTT, as shown in the simplified diagram 1002 of Fig. IOC, QT/BT/TT block partitioning in VVC, with respect to blocks 1103 (quad), 1104 (binary, JEM), and 1105 (ternary) to avoid duplicated partitions (e.g. prohibiting a vertical/horizontal binary split on the middle partition resulting from a vertical/horizontal ternary split). Further limitations may be set to the maximum depth of the BT and TT.

[99] Herein, new syntaxes are designed to describe QT/TT/BT size according to exemplary embodiments. These syntaxes change the base from min CB/QT to CTU. The proposed method allows QT/TT/BT size to be signaled using smaller numbers according to exemplary embodiments, and thus, improved coding efficiency, such as bit-efficiency, can be achieved.

[100] According to exemplary embodiments, the syntaxes which describe QT/TT/BT size, as noted with S16 according to exemplary embodiments, are changed, and it will be understood that in this disclosure, when saying signaling the delta values between A and B, it may also mean signaling the base 2 logarithm of the delta values between A and B. Also, in this disclosure, when saying signaling the absolute value of A, it may also mean signaling the base 2 logarithm of the absolute value of A.

[101] According to exemplary embodiments, signaling may include signaling the delta values between QT/TT/BT sizes and CTU size.

[102] According to exemplary embodiments, signaling may include explicitly signaling the absolute values of QT/TT/BT, without delta signaling.

[103] According to exemplary embodiments, signaling may include signaling the delta values between QT/TT/BT sizes and min CB size.

[104] According to exemplary embodiments, signaling may include signaling the delta values between QT/TT/BT sizes and min QT size.

[105] According to exemplary embodiments, signaling may include signaling the delta values between QT/TT/BT sizes and any predefined value.

[106] According to exemplary embodiments, signaling may include signaling the delta values between QT/TT/BT sizes and any values signaled in any parameter set (decoding parameter set (DPS), video parameter set (VPS), sequence parameter set (SPS), picture parameter set (PPS) and/or adaptation parameter set (APS)). [107] According to exemplary embodiments, modified VVC Draft 6 regarding SPS and slice header are shown below with changes highlighted in bold and with texts with strikethrough indicating deleted texts.

Table 3. Sequence parameter set RBSP syntax.

Table 4. General slice header syntax.

[108] According to exemplary embodiments, sps_log2_diff_ctu_min_qt_intra_slice_luma specifies the default difference between the base 2 logarithm of ctu size and the base 2 logarithm of the minimum size in luma samples of a luma leaf block resulting from quadtree splitting of a CTU (and with or without the base 2 logarithm of the minimum coding block size in luma samples for luma CUs in slices with slice type equal to 2 (I)) referring to the SPS. When partition constraints override flag is equal to 1, the default difference can be overridden by slice_log2_diff_ctu_min_qt_luma present in the slice header of the slices referring to the SPS. The value of sps_log2_diff_ctu_min_qt_intra_slice_luma shall be in the range of 0 to CtbLog2SizeY - MinCbLog2SizeY, inclusive. The base 2 logarithm of the minimum size in luma samples of a luma leaf block resulting from quadtree splitting of a CTU is derived as follows:

MinQtLog2SizeIntraY = log2_ctu_size_minus5 + 5 - sps_log2_diff_ctu_min_qt_intra_slice_luma - Eq. (7-24) [109] According to exemplary embodiments, sps_log2_diff_ctu_min_qt_inter_slice specifies the default difference between the base 2 logarithm of ctu size and the base 2 logarithm of the minimum size in luma samples of a luma leaf block resulting from quadtree splitting and referring to the SPS. When partition_constraints_override_ flag is equal to 1, the default difference can be overridden by slice_log2_diff_ctu_min_qt_luma present in the slice header of the slices referring to the SPS. The value of sps_log2_diff_ctu_min_qt_inter_slice shall be in the range of 0 to CtbLog2SizeY - MinCbLog2SizeY, inclusive. The base 2 logarithm of the minimum size in luma samples of a luma leaf block resulting from quadtree splitting of a CTU is derived as follows:

MinQtLog2SizeInterY = log2_ctu_size_minus5 + 5 - sps_log2_diff_ctu_min_qt_inter_slice - Eq. (7-25)

[110] According to exemplary embodiments, sps_log2_diff_ctu_max_bt_intra_slice_luma specifies the default difference between the base 2 logarithm of ctu size and the base 2 logarithm of the maximum size (width or height) in luma samples of a luma coding block that can be split using a binary split (and with or without the minimum size (width or height) in luma samples of a luma leaf block resulting from quadtree splitting of a CTU in slices with slice type equal to 2 (I)) referring to the SPS. When partition_constraints_override_ flag is equal to 1, the default difference can be overridden by slice_log2_diff_ctu_max_bt_luma present in the slice header of the slices referring to the SPS. The value of sps_log2_diff_ctu_max_bt_intra_slice_luma shall be in the range of 0 to CtbLog2SizeY - MinQtLog2SizeIntraY, inclusive. When sps_log2_diff_ctu_max_bt_intra_slice_luma is not present, the value of sps_log2_diff_ctu_max_bt_intra_slice_luma is inferred to be equal to 0. [111] According to exemplary embodiments, sps_log2_diff_ctu_max_tt_intra_slice_luma specifies the default difference between the base 2 logarithm of ctu size and the base 2 logarithm of the maximum size (width or height) in luma samples of a luma coding block that can be split using a ternary split (and with or without the minimum size (width or height) in luma samples of a luma leaf block resulting from quadtree splitting of a CTU in slices with slice type equal to 2 (I)) referring to the SPS. When partition_constraints_override_ flag is equal to 1, the default difference can be overridden by slice_log2_diff_ctu_max_tt_luma present in the slice header of the slices referring to the SPS. The value of sps_log2_diff_ctu_max_tt_intra_slice_luma shall be in the range of 0 to CtbLog2SizeY - MinQtLog2SizeIntraY, inclusive. When sps_log2_diff_ctu_max_tt_intra_slice_luma is not present, the value of sps_log2_diff_ctu_max_tt_intra_slice_luma is inferred to be equal to 0.

[112] According to exemplary embodiments, sps_log2_diff_ctu_max_bt_inter_slice specifies the default difference between the base 2 logarithm of ctu size and the base 2 logarithm of the maximum size (width or height) in luma samples of a luma coding block that can be split using a binary split (and with or without the minimum size (width or height) in luma samples of a luma leaf block resulting from quadtree splitting of a CTU in slices with slice type equal to 0 (B) or 1 (P)) referring to the SPS. When partition_constraints_override_ flag is equal to 1, the default difference can be overridden by slice_log2_diff_ctu_max_bt_luma present in the slice header of the slices referring to the SPS. The value of sps_log2_diff_ctu_max_bt_inter_slice shall be in the range of 0 to CtbLog2SizeY - MinQtLog2SizeInterY, inclusive. When sps_log2_diff_ctu_max_bt_inter_slice is not present, the value of sps_log2_diff_ctu_max_bt_inter_slice is inferred to be equal to 0. [113] According to exemplary embodiments, sps_log2_diff_ctu_max_tt_inter_slice specifies the default difference between the base 2 logarithm of ctu size and the base 2 logarithm of the maximum size (width or height) in luma samples of a luma coding block that can be split using a ternary split (and the minimum size (width or height) in luma samples of a luma leaf block resulting from quadtree splitting of a CTU in slices with slice type equal to 0 (B) or 1 (P)) referring to the SPS. When partition_constraints_override_ flag is equal to 1, the default difference can be overridden by slice_log2_diff_ctu_max_tt_luma present in the slice header of the slices referring to the SPS. The value of sps_log2_diff_ctu_max_tt_inter_slice shall be in the range of 0 to CtbLog2SizeY - MinQtLog2SizeInterY, inclusive. When sps_log2_diff_ctu_max_tt_inter_slice is not present, the value of sps_log2_diff_ctu_max_tt_inter_slice is inferred to be equal to 0.

[114] According to exemplary embodiments, sps_log2_diff_ctu_max_bt_intra_slice_chroma specifies the default difference between the base 2 logarithm of ctu size and the base 2 logarithm of the maximum size (width or height) in luma samples of a chroma coding block that can be split using a binary split (and with or without the minimum size (width or height) in luma samples of a chroma leaf block resulting from quadtree splitting of a chroma CTU with treeType equal to DUAL TREE CHROMA in slices with slice type equal to 2 (I)) referring to the SPS. When partition constraints override flag is equal to 1, the default difference can be overridden by slice_log2_diff_ctu_max_bt_chroma present in the slice header of the slices referring to the SPS. The value of sps_log2_diff_ctu_max_bt_intra_slice_chroma shall be in the range of 0 to CtbLog2SizeY - MinQtLog2SizeIntraC, inclusive. When sps_log2_diff_ctu_max_bt_intra_slice_chroma is not present, the value of sps_log2_diff_ctu_max_bt_intra_slice_chroma is inferred to be equal to 0. [115] According to exemplary embodiments, sps_log2_diff_ctu_max_tt_intra_slice_chroma specifies the default difference between the base 2 logarithm of ctu size and the base 2 logarithm of the maximum size (width or height) in luma samples of a chroma coding block that can be split using a ternary split (and with or without the minimum size (width or height) in luma samples of a chroma leaf block resulting from quadtree splitting of a chroma CTU with treeType equal to DUAL TREE CHROMA in slices with slice type equal to 2 (I)) referring to the SPS. When partition constraints override flag is equal to 1, the default difference can be overridden by slice_log2_diff_ctu_max_tt_chroma present in the slice header of the slices referring to the SPS. The value of sps_log2_diff_ctu_max_tt_intra_slice_chroma shall be in the range of 0 to CtbLog2SizeY - MinQtLog2SizeIntraC, inclusive. When sps_log2_diff_ctu_max_tt_intra_slice_chroma is not present, the value of sps_log2_diff_ctu_max_tt_intra_slice_chroma is inferred to be equal to 0.

[116] According to exemplary embodiments, slice_log2_diff_ctu_min_qt_luma specifies the difference between the base 2 logarithm of ctu size and the base 2 logarithm of the minimum size in luma samples of a luma leaf block resulting from quadtree splitting of a CTU (and with or without the base 2 logarithm of the minimum coding block size in luma samples for luma CUs) in the current slice. The value of slice_log2_diff_ctu_min_qt_luma shall be in the range of 0 to CtbLog2SizeY - MinCbLog2SizeY, inclusive. When not present, the value of slice_log2_diff_ctu_min_qt_luma is inferred as follows:

If slice type equal to 2 (I), the value of slice_log2_diff_ctu_min_qt_luma is inferred to be equal to sps_log2_diff_ctu_min_qt_intra_slice_luma Otherwise (slice type equal to 0 (B) or 1 (P)), the value of slice_log2_diff_ctu_min_qt_luma is inferred to be equal to sps_log2_diff_ctu_min_qt_inter_slice.

[117] According to exemplary embodiments, slice_log2_diff_ctu_max_bt_luma specifies the difference between the base 2 logarithm of ctu size and the base 2 logarithm of the maximum size (width or height) in luma samples of a luma coding block that can be split using a binary split and the minimum size (width or height) in luma samples of a luma leaf block resulting from quadtree splitting of a CTU in the current slice. The value of slice_log2_diff_ctu_max_bt_luma shall be in the range of 0 to CtbLog2SizeY - MinQtLog2SizeY, inclusive. When not present, the value of slice_log2_diff_ctu_max_bt_luma is inferred as follows:

If slice type equal to 2 (I), the value of slice_log2_diff_ctu_max_bt_luma is inferred to be equal to sps_log2_diff_ctu_max_bt_intra_slice_luma Otherwise (slice type equal to 0 (B) or 1 (P)), the value of slice_log2_diff_ctu_max_bt_luma is inferred to be equal to sps_log2_diff_ctu_max_bt_inter_slice.

[118] According to exemplary embodiments, slice_log2_diff_ctu_max_tt_luma specifies the difference between the base 2 logarithm of ctu size and the base 2 logarithm of the maximum size (width or height) in luma samples of a luma coding block that can be split using a ternary split (and with or without the minimum size (width or height) in luma samples of a luma leaf block resulting from quadtree splitting of a CTU) in the current slice. The value of slice_log2_diff_ctu_max_tt_luma shall be in the range of 0 to CtbLog2SizeY - MinQtLog2SizeY, inclusive. When not present, the value of slice_log2_diff_ctu_max_tt_luma is inferred as follows: If slice type equal to 2 (I), the value of slice_log2_diff_ctu_max_tt_luma is inferred to be equal to sps_log2_diff_ctu_max_tt_intra_slice_luma Otherwise (slice type equal to 0 (B) or 1 (P)), the value of slice_log2_diff_ctu_max_tt_luma is inferred to be equal to sps_log2_diff_ctu_max_tt_inter_slice.

[119] According to exemplary embodiments, slice_log2_diff_ctu_min_qt_chroma specifies the difference between the base 2 logarithm of ctu size and the base 2 logarithm of the minimum size in luma samples of a chroma leaf block resulting from quadtree splitting of a chroma CTU with treeType equal to DUAL TREE CHROMA (and with or without the base 2 logarithm of the minimum coding block size in luma samples for chroma CUs with treeType equal to

DUAL TREE CHROMA) in the current slice. The value of slice_log2_diff_ctu_min_qt_chroma shall be in the range of 0 to CtbLog2SizeY - MinCbLog2SizeY, inclusive. When not present, the value of slice_log2_diff_ctu_min_qt_chroma is inferred to be equal to sps_log2_diff_ctu_min_qt_intra_slice_chroma.

[120] According to exemplary embodiments, slice_log2_diff_ctu_max_bt_chroma specifies the difference between the base 2 logarithm of ctu size and the base 2 logarithm of the maximum size (width or height) in luma samples of a chroma coding block that can be split using a binary split (and with or without the minimum size (width or height) in luma samples of a chroma leaf block resulting from quadtree splitting of a chroma CTU with treeType equal to

DUAL TREE CHROMA) in the current slice. The value of slice_log2_diff_ctu_max_bt_chroma shall be in the range of 0 to CtbLog2SizeY - MinQtLog2SizeC, inclusive. When not present, the value of slice_log2_diff_ctu_max_bt_chroma is inferred to be equal to sps_log2_diff_ctu_max_bt_intra_slice_chroma.

[121] According to exemplary embodiments, slice_log2_diff_ctu_max_tt_chroma specifies the difference between the base 2 logarithm of ctu size and the base 2 logarithm of the maximum size (width or height) in luma samples of a chroma coding block that can be split using a ternary split (and the minimum size (width or height) in luma samples of a chroma leaf block resulting from quadtree splitting of a chroma CTU with treeType equal to DUAL TREE CHROMA) in the current slice. The value of slice_log2_diff_ctu_max_tt_chroma shall be in the range of 0 to CtbLog2SizeY - MinQtLog2SizeC, inclusive. When not present, the value of slice_log2_diff_ctu_max_tt_chroma is inferred to be equal to sps_log2_diff_ctu_max_tt_intra_slice_chroma.

[122] As described herein, there may be one or more hardware processor and computer components, such as buffers, arithmetic logic units, memory instructions, configured to determine or store predetermined delta values (differences) between ones of the values described herein according to exemplary embodiments.

[123] Accordingly, by exemplary embodiments described herein, the technical problems noted above may be advantageously improved upon by one or more of these technical solutions. That is, according to embodiments, to address one or more different technical problems, this disclosure described new syntaxes and use thereof designed to describe QT/TT/BT size. According to embodiments, these syntaxes change the base from min CB/QT to CTU, and embodiments allow QT/TT/BT size to be signaled using smaller numbers. Thus, improved coding efficiency can be achieved. [124] The techniques described above, can be implemented as computer software using computer-readable instructions and physically stored in one or more computer-readable media or by a specifically configured one or more hardware processors. For example, FIG. 12 shows a computer system 1200 suitable for implementing certain embodiments of the disclosed subject matter.

[125] The computer software can be coded using any suitable machine code or computer language, that may be subject to assembly, compilation, linking, or like mechanisms to create code comprising instructions that can be executed directly, or through interpretation, micro-code execution, and the like, by computer central processing units (CPUs), Graphics Processing Units (GPUs), and the like.

[126] The instructions can be executed on various types of computers or components thereof, including, for example, personal computers, tablet computers, servers, smartphones, gaming devices, internet of things devices, and the like.

[127] The components shown in FIG. 12 for computer system 1200 are exemplary in nature and are not intended to suggest any limitation as to the scope of use or functionality of the computer software implementing embodiments of the present disclosure. Neither should the configuration of components be interpreted as having any dependency or requirement relating to any one or combination of components illustrated in the exemplary embodiment of a computer system 1200.

[128] Computer system 1200 may include certain human interface input devices. Such a human interface input device may be responsive to input by one or more human users through, for example, tactile input (such as: keystrokes, swipes, data glove movements), audio input (such as: voice, clapping), visual input (such as: gestures), olfactory input (not depicted). The human interface devices can also be used to capture certain media not necessarily directly related to conscious input by a human, such as audio (such as: speech, music, ambient sound), images (such as: scanned images, photographic images obtain from a still image camera), video (such as two-dimensional video, three-dimensional video including stereoscopic video).

[129] Input human interface devices may include one or more of (only one of each depicted): keyboard 1201, mouse 1202, trackpad 1203, touch screen 1210, joystick 1205, microphone 1206, scanner 1208, camera 1207.

[130] Computer system 1200 may also include certain human interface output devices. Such human interface output devices may be stimulating the senses of one or more human users through, for example, tactile output, sound, light, and smell/taste. Such human interface output devices may include tactile output devices (for example tactile feedback by the touch-screen 1210, or joystick 1205, but there can also be tactile feedback devices that do not serve as input devices), audio output devices (such as: speakers 1209, headphones (not depicted)), visual output devices (such as screens 1210 to include CRT screens, LCD screens, plasma screens, OLED screens, each with or without touch-screen input capability, each with or without tactile feedback capability — some of which may be capable to output two dimensional visual output or more than three dimensional output through means such as stereographic output; virtual-reality glasses (not depicted), holographic displays and smoke tanks (not depicted)), and printers (not depicted).

[131] Computer system 1200 can also include human accessible storage devices and their associated media such as optical media including CD/DVD ROM/RW 1220 with CD/DVD 1211 or the like media, thumb-drive 1222, removable hard drive or solid state drive 1223, legacy magnetic media such as tape and floppy disc (not depicted), specialized ROM/ASIC/PLD based devices such as security dongles (not depicted), and the like. [132] Those skilled in the art should also understand that term “computer readable media” as used in connection with the presently disclosed subject matter does not encompass transmission media, carrier waves, or other transitory signals.

[133] Computer system 1200 can also include interface 1299 to one or more communication networks 1298. Networks 1298 can for example be wireless, wireline, optical. Networks 1298 can further be local, wide-area, metropolitan, vehicular and industrial, real-time, delay-tolerant, and so on. Examples of networks 1298 include local area networks such as Ethernet, wireless LANs, cellular networks to include GSM, 3G, 4G, 5G, LTE and the like, TV wireline or wireless wide area digital networks to include cable TV, satellite TV, and terrestrial broadcast TV, vehicular and industrial to include CANBus, and so forth. Certain networks 1298 commonly require external network interface adapters that attached to certain general-purpose data ports or peripheral buses (1250 and 1251) (such as, for example USB ports of the computer system 1200; others are commonly integrated into the core of the computer system 1200 by attachment to a system bus as described below (for example Ethernet interface into a PC computer system or cellular network interface into a smartphone computer system). Using any of these networks 1298, computer system 1200 can communicate with other entities. Such communication can be uni-directional, receive only (for example, broadcast TV), uni-directional send-only (for example CANbusto certain CANbus devices), or bi-directional, for example to other computer systems using local or wide area digital networks. Certain protocols and protocol stacks can be used on each of those networks and network interfaces as described above.

[134] Aforementioned human interface devices, human-accessible storage devices, and network interfaces can be attached to a core 1240 of the computer system 1200. [135] The core 1240 can include one or more Central Processing Units (CPU) 1241, Graphics Processing Units (GPU) 1242, a graphics adapter 1217, specialized programmable processing units in the form of Field Programmable Gate Areas (FPGA) 1243, hardware accelerators for certain tasks 1244, and so forth. These devices, along with Read-only memory (ROM) 1245, Random-access memory 1246, internal mass storage such as internal non-user accessible hard drives, SSDs, and the like 1247, may be connected through a system bus 1248. In some computer systems, the system bus 1248 can be accessible in the form of one or more physical plugs to enable extensions by additional CPUs, GPU, and the like. The peripheral devices can be attached either directly to the core’s system bus 1248, or through a peripheral bus 1251. Architectures for a peripheral bus include PCI, USB, and the like.

[136] CPUs 1241, GPUs 1242, FPGAs 1243, and accelerators 1244 can execute certain instructions that, in combination, can make up the aforementioned computer code. That computer code can be stored in ROM 1245 or RAM 1246. Transitional data can be also be stored in RAM 1246, whereas permanent data can be stored for example, in the internal mass storage 1247. Fast storage and retrieval to any of the memory devices can be enabled through the use of cache memory, that can be closely associated with one or more CPU 1241, GPU 1242, mass storage 1247, ROM 1245, RAM 1246, and the like.

[137] The computer readable media can have computer code thereon for performing various computer-implemented operations. The media and computer code can be those specially designed and constructed for the purposes of the present disclosure, or they can be of the kind well known and available to those having skill in the computer software arts.

[138] As an example and not by way of limitation, the computer system having architecture 1200, and specifically the core 1240 can provide functionality as a result of processor(s) (including CPUs, GPUs, FPGA, accelerators, and the like) executing software embodied in one or more tangible, computer-readable media. Such computer-readable media can be media associated with user-accessible mass storage as introduced above, as well as certain storage of the core 1240 that are of non-transitory nature, such as core-internal mass storage 1247 or ROM 1245. The software implementing various embodiments of the present disclosure can be stored in such devices and executed by core 1240. A computer-readable medium can include one or more memory devices or chips, according to particular needs. The software can cause the core 1240 and specifically the processors therein (including CPU, GPU, FPGA, and the like) to execute particular processes or particular parts of particular processes described herein, including defining data structures stored in RAM 1246 and modifying such data structures according to the processes defined by the software. In addition or as an alternative, the computer system can provide functionality as a result of logic hardwired or otherwise embodied in a circuit (for example: accelerator 1244), which can operate in place of or together with software to execute particular processes or particular parts of particular processes described herein. Reference to software can encompass logic, and vice versa, where appropriate. Reference to a computer- readable media can encompass a circuit (such as an integrated circuit (IC)) storing software for execution, a circuit embodying logic for execution, or both, where appropriate. The present disclosure encompasses any suitable combination of hardware and software.

[139] While this disclosure has described several exemplary embodiments, there are alterations, permutations, and various substitute equivalents, which fall within the scope of the disclosure. It will thus be appreciated that those skilled in the art will be able to devise numerous systems and methods which, although not explicitly shown or described herein, embody the principles of the disclosure and are thus within the spirit and scope thereof.