Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
INTEGRATED CIRCUIT MEMORY AND FORMING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2022/062544
Kind Code:
A1
Abstract:
The present application provides an integrated circuit memory and a forming method therefor. The memory comprises: a substrate, multiple active regions arranged in an array being provided in the substate; a conductive line group formed in the substrate, the conductive line group comprising multiple conductive lines sequentially arranged in a first direction, each conductive line extending in a second direction and being connected to the corresponding active region, and the end portions of two adjacent conductive lines at the same side being staggered with each other in the second direction; and multiple contact pads formed on the substrate, a contact pad being connected to the end portion of a conductive line, and the two adjacent contact pads located at the same side being staggered with each other in the second direction. Thus, a limit lithography process window corresponding to the absence of an open circuit between the contact pads and the conductive lines is effectively enlarged, and a limit lithography process window corresponding to the absence of a short circuit between the adjacent conductive lines is enlarged, so that the risks of an open circuit between the contact pads and the conductive lines and a short circuit between the adjacent conductive lines can be significantly reduced.

Inventors:
LI YUKUN (CN)
Application Number:
PCT/CN2021/103717
Publication Date:
March 31, 2022
Filing Date:
June 30, 2021
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L27/108; G11C5/02
Foreign References:
US20110235386A12011-09-29
JPH0982710A1997-03-28
CN110391234A2019-10-29
CN110534517A2019-12-03
CN207938611U2018-10-02
Attorney, Agent or Firm:
LEADER PATENT & TRADEMARK FIRM (CN)
Download PDF: