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Patent Searching and Data


Title:
INTERFACE CIRCUIT, DATA TRANSMISSION CIRCUIT AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2022/042017
Kind Code:
A1
Abstract:
An interface circuit, a data transmission circuit and a memory, relating to the technical field of semiconductors. The interface circuit comprises a clock pad (102), data pads (101) and input buffer circuits (103), wherein the clock pad (102) and the data pads (101) are arranged in a first row, M data pads (101) are arranged on two sides of the clock pad (102), half of the M data pads (101) are arranged on each side, M input buffer circuits (103) are arranged in a second row, an axis (AA1) perpendicular to the first row is formed by taking the data pad (101) as a reference, the M input buffer circuits (103) are arranged on two sides of the axis (AA1), half of the M input buffer circuits (103) are arranged on each side, and the distance between each input buffer circuit (103) and the axis (AA1) is smaller than the distance between the data pad (101) corresponding to the input buffer circuit (103) and the axis (AA1).

Inventors:
LIN FENG (CN)
Application Number:
PCT/CN2021/103707
Publication Date:
March 03, 2022
Filing Date:
June 30, 2021
Export Citation:
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Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/4096
Foreign References:
CN111105826A2020-05-05
CN209087410U2019-07-09
CN102354519A2012-02-15
CN1641685A2005-07-20
CN104733050A2015-06-24
US20060109929A12006-05-25
Other References:
See also references of EP 4006905A4
Attorney, Agent or Firm:
SHANGHAI CHENHAO INTELLECTUAL PROPERTY LAW FIRM GENERAL PARTNERSHIP (CN)
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