Title:
INTERPOLATION FILTER SYSTEM IMPLEMENTED BY DIGITAL CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2021/056711
Kind Code:
A1
Abstract:
An interpolation filter system implemented by a digital circuit, comprising an interpolation filter operation controller, a cascade drive module, an intermediate result cache RAM, and a filter coefficient storage ROM; the interpolation filter operation controller comprises cascaded filter operation modules and master state machines; the intermediate result cache RAM is configured to store externally inputted data of the interpolation filter system and intermediate results outputted by the filter operation modules; the filter coefficient storage ROM is configured to store filter coefficients required for calculation by the filter operation modules; the interpolation filter operation controller is configured to control, under the drive of counting beats outputted by the cascade drive module, the master state machine to select data of the intermediate result cache RAM or externally directly inputted data to be sent to the cascaded filter operation modules for accumulation operation, and to select the filter coefficients of the filter coefficient storage ROM for multiplication operation, thereby achieving the purpose of interpolation filtering after the processing by the cascaded filter operation modules is performed.
Inventors:
WANG LILI (CN)
Application Number:
PCT/CN2019/116930
Publication Date:
April 01, 2021
Filing Date:
November 10, 2019
Export Citation:
Assignee:
AMICRO SEMICONDUCTOR CO LTD (CN)
International Classes:
H03H17/02
Foreign References:
| CN101820287A | 2010-09-01 | |||
| CN1992517A | 2007-07-04 | |||
| CN105048994A | 2015-11-11 | |||
| US20120068866A1 | 2012-03-22 |
Other References:
ZENG, PEIZHI: "Digital IF Filter Design and Implementation of FPGA", INFORMATION & TECHNOLOGY, CHINA MASTER'S THESES FULL-TEXT DATABASE, no. 6, 15 June 2015 (2015-06-15), pages 1 - 71, XP055793958, ISSN: 1674-0246
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