LARGE SCALE, SINGLE CHIP INTEGRATED CIRCUIT TELEVISION RECEIVER SUBSYSTEMS

CROSS REFERENCE TO RELATED APPLICATIONS 5

1. SC-80041 "Horizontal Oscillator"

2. SC-80044 "Horizontal phase Detector Gain Control"

3. SC-80977 "Horizontal Phase Lock Loop For Television"

4. SC-80978 "Variable Capacitance Circuit"

10 5. SC-80071 "Linear Full Wave Rectifier Circuit"

6. SC-80976 "Sync Separator"

7. SC-80980 "Integrator Circuit For Separating Vertical

Sync Pulses"

15 BACKGROUND OF THE INVENTION

Field of the Art:

The present invention relates to television circuits and, more particularly, to a partitioning scheme for a 20 television receiver for providing the video and signal processing circuits on a single large scale integrated circuit.

Description of the Prior Art:

25 Since the first television receiver was built comprising discrete circuitry and vacuum tubes television receivers have evolved to the present wherein the television receiver comprises a plurality of integrated circuits in combination with the tuner and high powered

30 portions of the circuit as well as the cathode ray tube (CRT) utilized to provide the television picture.

Generally, contemporary television receivers include a radio frequency (RF) tuner which is coupled to a tuned input of an intermediate frequency (IF) stage the output of

35 which is coupled to both a video processing stage and a signal processing stage wherein the video composite TV

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signal is processed to drive the cathode ray tube with the output of the signal processing stage being utilized to drive the horizontal and vertical deflection yokes of the television cathode ray tube so that the video information supplied from the video processor is converted to a recognizable picture on the CRT.

Typically, contemporary television receivers require a minimum of four integrated circuits to provide the functions of a basic black and white television receiver. For example, the television receiver can be partitioned in a manner wherein four integrated circuits may be utilized to provide (1) video IF amplifier and video detection (2) video signal processing (3) horizontal sync information processing and (4) vertical sync information processing. The aforedescribed combination of multiple integrated circuits .results in a problem that is related to all such television receivers which is caused by undesirous signal radiation that occurs to a_ greater or lesser extent because of the use of external coils in tuned circuits required for detection of the composite TV stereo operating in a high signal environment. For instance, this radiation usually emanates from a portion of the television receiver where the IF signal levels are at the highest: usually at the interface of the video detector stage of the television receiver where the external tuned circuits are utilized for video detection. Another problem with television receivers utilizing multiple integrated circuits is that exact DC signal bias levels must be maintained between each one of the multiple integrated circuits. It is quite difficult to achieve these bias levels and an attempt to so requires external biasing circuitry to be utilized. Still further, the use of multiple integrated circuits can be relatively expensive when compared to a television receiver that required only a single large scale integrated chip to provide the aforementioned functions.

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Hence, the present, invention is concerned with combining the basic functions of a television receiver, i.e., the IF amplifier/detector stage, video processing signal processing circuits into a single large scale integrated circuit having optimum partitioning. Such a single integrated circuit can eliminate radiation proble as aforedescribed with elimination of tuned circuits by use thereof as well as save costs by eliminating the nee for multiple integrated circuits.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present inventio to provide a large scale integrated circuit television subsystem.

There's another object of the present invention to provide a large scale integrated circuit incorporating th basic functions of a television receiver including the IF amplifier, video detecting and processing, horizontal and vertical processing circuits therefor.

A still further object of the present invention is t provide a large scale integrated circuit to be utilized i a television receiver having a horizontal and vertical processing circuit for producing vertical and horizontal sync pulses which are related to each other.

In accordance with the above and other objects there is provided a large scale integrated circuit having circu partitioning for providing basic functions of a black and white television receiver including an IF amplifier section, a video detector, a signal processor, a video signal processor, horizontal and vertical processors therein.

One feature of the present invention is that the vid detector circuit eliminates the use of tuned circuits suc that radiation problems which frequently occur in prior a

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television receivers are eliminated or at least greatly reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram illustrating a typical black and white television receiver;

Fig. 2 is a block diagram of the television receiver of the present invention; Fig. 3 is a block diagram of a vertical countdown circuitry of the present invention; and

Fig. 4 is a schematic diagram -of a latch circuit utilized in the vertical countdown circuitry of Fig. 3.

DETAILED DESCRIPTION OF THE INVENTION

Turning to Fig. 1, there is shown a typical black and white television receiver which is generally understood to those skilled in the art. Television receiver (10), as shown, comprises a RF tuner section 12 which is coupled to antenna 14 to recei-ve the television composite signal. RF tuner 12 includes a voltage controlled oscillator for converting the composite television signal to an IF frequency which is then applied via a tuned stage to the input of IF amplifier section 16. The output of IF amplifier section 16 is applied to video detector 18 wherein the video information, as well as the vertical and horizontal sync information are detected and separated from the sound information carrying signal. The sound signal is processed through sound processing circuit 20 to be reproduced as audio at speaker 22. The video information is processed through video processing circuit 24 to drive the cathode of cathode ray tube 26 to develop the television picture in conjunction with the vertical and horizontal deflection circuits V and H which surround tube 26. An output is also supplied from video detector 18 to

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signal processing cirucit 28, which as known provides several functional outputs, i.e., gated automatic gain control signals are provided for controlling the gains of the IF amplifier stage 16 and the RF tuner 12 via leads 30 5 and 32 respectively, also, the horizontal and vertical syn pulses are separated with RF noise spikes eliminated from the sync pulses. The respective pulses are supplied to horizontal and vertical processing circuits 34 and 36. Video processing circuit 24 is shown as receiving contrast 10 and brightness control signals as is understood to vary th signal drive to the cathode of cathode ray tube 26. Video processing circuit 24 also receives a blanking signal from vertical processing circuit 36 to blank the screen of the tube 26 during the vertical flyback period of the 15 television receiver.

Horizontal and vertical processing circuits 34 and 36 each typically include a free running oscillator which may be locked by the respective horizontal and vertical sync pulses supplied thereto for synching the horizontal and 20 vertical scanning to the__received video signal. Horizonta scanning information is sampled from the currents intro¬ duced through the horizontal deflection coils, H and V, which are positioned about tube 26 in order to maintain synchronization and linearity of drive. The outputs from 25 horizontal and vertical circuits 34 and 36 are supplied to horizontal and vertical output amplifiers 38 and 40 respectively to drive the aforementioned deflection coils.

It should be understood that although the foregoing description refers to a black and white television receiver 30 that those skilled in the art understand that a color receiver is also explained in that only a chroma demodulator and driver stages need be added to the television receiver in a known manner in conjunction with a color cathode ray tube. 35 Typically, contemporary television receiver 10 comprises a minimum of four integrated circuits (IC'ε) for

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providing the IF, video detection, horizontal sync and vertical sync processing. As an example, television receiver 10 can be realized using the following available ICs which are manufactured by Motorola Inc.:

TELEVISION CIRCUIT I

IF Amplifier 16 MC1349/1350

Video Dectector and video MC1330/1350

Processing Circuits 18 and 24 10 Sound Processing Circuit 20 TDA1190 Signal Processing Circuit 28 MC1344 Horizontal Processing Circuit _34 MC1391 Vertical Processing Circuit 36 MC1393 As mentioned previously, prior art television 15 receivers of the type described above suffer from several disadvantages, i.e. radiation problems and maintenance of accurate dc levels between individual integrated circuits. The present invention relates to specific partitioning of ^• the several individual stages described above into a large 20 scale integrated circuit to eliminate radiation. roblems generally arising in the video detector portion by eliminating the need for tuned circuits as well as eliminating the need for several dc biasing circuits for maintaining the dc levels between the individual integrated 25 circuits.

Turning now to Fig. 2, there is shown a large scale integrated television receiver subsystem circuit 50 of the preferred embodiment wherein partitioning of the IF and video processing circuity is accomplished on one single 30 integrated circuit to eliminate the aforementioned problems of the prior art. As illustrated single integrated circuit television receiver subsystem 50 includes video IF amplifier stage 52 to which is supplied the composite television signal at input terminals 52 and 54 from a RF 35 tuner section (not shown) . The output of the video IF section is coupled via coupling capacitors 56 and 58 to the

OM

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input of video detector 60. Coupling capacitors 58 and 56 are integrated on the integrated circuit whereby video detector 60 is ac coupled to video IF amplifier 52. The output at output terminal 62 from video detector is 5 supplied to the sound processor section of the television receiver which is not part of the integrated circuit subsystem 50. Copending patent application, Serial No. , entitled "Linear Full Wave Rectifier Circuit" which is incorporated herein by reference describes a 10 circuit that may be utilized for detecting the video television composite signal. The composite video information signal appearing at the ^* output of video detector 60 is supplied via lead 64 to video processor. circuit: 66 and is processed in like manner for prior art 15 processor circuits to provide the luma information to the cathode of the cathode ray tube at output 68 of subsystem circuit 50. It is to be understood that if a color television receiver is to utilize single subsystem circui 50 that chroma demodulator and detector circuits would be 20 coupled to output terminal 68 to provide chroma informatio to a color tube. The output of video processing circuit 66 is coupled to output 68 through a blank/buffer circuit 70 which receives a blanking input signal via lead 72 to provide the blanking function to the television tube during 25 vertical flyback. Still another output of detector 60 is taken via lead 74 and supplied to noise processing circuit 76 for eliminating noise spikes from the composite video signal appearing at output 74. Noise processing circuit 76 provides the aforementioned function in a known manner 30 wherein the noise spikes are inverted and then added back to the signal for 'example, to eliminate the same therefrom so that noise spikes will not affect the operation of the sync separator circuit 78. The output of noise processor circuit 76 as well as sync separator 78 and output 80 of 35 video detector 60 is supplied to automatic gain control (AGC) circuit 82. The horizontal flyback signal supplied

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at input terminal 84 via buffer circuit 86 is also supplied to an input of AGC circuit 82 to develop a gated gain control signal at the outputs of thereof in response to a gain control voltage being developed across an external capacitor 88 supplied to input terminal 90 of the tele¬ vision receiver subsystem 50. AGC circuit 82 operates in a known manner to first vary the gain of the video IF section 52 via lead 92 and then to vary the gain of the RF tuner via lead 94 which is connected at an output pin 96 of television receiver subsystem 50.

The output of noise processor circuit 76 is supplied to sync separator 78 to separate the horizontal and vertical sync pulses are separated from the video composite signal as is well known in the art. A possible circuit whcih may be utilized as sync separator 78 is described in detail in referenced patent application, Serial No. , entitled "Sync Separator" which is also incorporated herein by ref rence. The horizontal sync pulses from sync separator 78 and supplied to a horizontal processor circuit via lead 98 with the vertical sync pulse information being •-supplied to vertical sync circuit 100 via lead 102. Vertical sync circuit 100 may include an integrator circuit described in copending patent application, Serial No. , entitled "Integrator Circuit For Separating Vertical Sync Pulses", which is incorporated herein by reference.

As illustrated, the horizontal processor portion of television receiver subsystem circuit 50 operates to lock the horizontal flyback signal to the horizontal sync pulse which is in turn locked to the horizontal oscillator 104. An oscillator suitable for use as horizontal oscillator 104 is described in copending patent application, Serial No. , entitled "Horizontal Oscillator", and incorporated herein by reference operates at a frequency equal to twice the horizontal line frequency, i.e., 31.5 kHz. In the present embodiment, the horizontal processing circuit

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besides including horizontal oscillator 104, comprises a phase lock loop circuit comprising two loops. The first loop includes oscillator 104 which is a free running oscillator line the output thereof being provided to a εlicer and divide by two circuit 106. The output of εlice circuit 106 is provided to a first phase detector 108 whic is gated by the horizontal sync pulses provided from sync separator 78 via lead 98. The output of phase detector 108 is provided at an output 110 to a low pass filter (not shown) and is returned to the input of the horizontal oscillator 104 at an input pin 112. In this manner, the frequency of the horizontal oscillator 104 is varied such that the horizontal sync pulses are centered about the trailing edges of the output pulses of the horizontal oscillator 104. The second loop of the two-loop horizontal phase lock loop circuit includes oscillator 104, slicer/ divide by two circuit 106, and a second phase detector 114 which is gated by the flyback pulses from -the horizontal deflection circuit of the television receiver and supplied at input terminal 84 through flyback buffer 86. The output of phase detector 114 is supplied at an output 116 to a low pass filter which may be, as shown, capacitor 118 to bias a variable εlicer/divide by two circuit 120 which also receives the horizontal oscillator pulses via lead 122. In this manner, the horizontal flyback pulse is centered about a point on the output of the oscillator such that the horizontal flyback pulses are locked with respect to the horizontal sync pulses to the horizontal oscillator. A detailed description of a horizontal processor circuit that may be utilized in the present invention is provided in aforereferenced copending patent application, Serial No. , entitled "Horizontal Phase Lock Loop For

Television" which is incorporated herein by reference. The output of variable εlicer 120 εupplied through a horizontal buffer circuit 124 to output pin 126. As understood, the output from the horizontal processor circuit, at output pin

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126, is supplied to a horizontal driver amplifier to drive the horizontal deflection coils of the cathode ray tube of the television receiver. Phase detector 108 is shown as also receiving an input control signal via lead 128 from a window control circuit 130. As is fully explained in copending patent application. Serial No. , entitled

"Horizontal Phase Detector Gain Control", and incorporated herein by reference, the gain of the phase detector 108 is varied by thiε control signal supplied from window control circuit 130 in accordance with the television receiver being either in sync or not with the television composite signal. Hence, if the television receiver is in sync the gain of phase detector 108 is at a nominal value and is then increased if the television is not in sync to the incoming composite television signal, this increases the bandwidth of the phased locked loop to effect a faster pull-in of the horizontal sync pulses as is understood. An output of horizontal oscillator 104 is taken via lead 131 ^* and is supplied to a vertical countdown circuit 132. Vertical sync pulses are also supplied to the vertical processor circuit from vertical sync circuit 100. As will be fully explained hereinafter, the vertical sync pulses are utilized to reset vertical countdown circuit 132, a divide by 525 counter, such that in response to the input pulses supplied from the horizontal oscillator 104, a vertical flyback pulse is derived once each frame, as is required to sync the vertical picture scanning to the received video signal. Vertical countdown circuit 132 also supplies the aforementioned blanking signal via lead 72 to blanking buffer 70. The output of the vertical countdown circuit 132 is provided to vertical scan circuit 134. The output of vertical countdown circuit 132 is esεentially the vertical εync pulse which is then utilized to generate a ramp εignal acroεε the RC combination connected at pin 136 to derive the vertical flyback pulse via vertical preamplifier 138 to the vertical deflection coils of the

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tube at output 140. A feedback signal generated through the vertical deflection coils of the tube is supplied at input pin 142 to an input of vertical preamp 138 to insure tracking of the vertical flyback pulse. Turning to Figs. 3 and 4, the- combined operation of vertical countdown circuit 32 and window control circuit 130 can be explained. Window control circuit 130 is fully discussed in the aforereferenced application, Serial No. , entitled, "Horizontal phase Detector Gain Control" with respect to generating a gain control signal for varying the gain of phase detector 108 when the television receiver incorporating the present .invention is out of sync. The foregoing patent application is incorporated herein by reference. Briefly, the output pulses of horizontal oscillator 104 are supplied to the input of countdown circuit 132 to initiate vertical countdown. Vertical countdown circuit 132 comprises a ten stage counter 144 as understood. The horizontal oscillator clock pulses are divided by 525 by the counter to provide a . decode signal once each frame of the television picture to coincide with the vertical sync pulse supplied from vertical sync circuit 100. Vertical countdown circuit 132 includes a reset circuit 150 for among other things providing a reset pulse via lead 146 to reset counter 144 on the occurrence of a vertical sync pulse.

In normal operation, with the television receiver in sync, the vertical snyc pulse is supplied to a plurality of serially connected logic gate inverters 150a at the input of reset circuit 150. These gates may be enabled at the 514th count of counter 144 by gate 152 to allow the sync pulse to pasε to latch portion 150b of reεet circuit 150. The latch portion provides an output both at the input of reεet portion 150c of reset circuit 150 and to the input of vertical scan circuit 134 to initiate the vertical flyback period as previously discussed. The structure of the latch circuit is shown in Fig. 4 and includes a pair of

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integrated injection logic (I-^L) NAND gates as shown. At a predetermined level of the ramp signal generated at terminal 136 a εtop εignal is initiated from vertical scan circuit 134 via lead 154 to put latch portion 150b in its 5 latched state to thereby inhibit the input to vertical scan circuit 134 as well as to reset reset portion 150c. Therefore, in addition to initiating the vertical flyback period, the horizontal sync pulse produces a reset signal to reset counter 144. The reset portion of reset cirucit

10 150 may be a D-type flip flop circuit.

Between the 524th and 526th counts of the counter a narrow window pulse is produced via_ output lead 156 to the input of coincidence detector 148 of window control circuit 130. If coincidence occurs during this narrow window with

15 the reset signals applied via lead 158, coincidence detector 148 maintains the nominal gain of phase detector 108 and gate 152 is enabled to in turn enable the gates of circuit 150. Thus, a narrow window is established between counts 514 to 526 within which coincidence of the vertical

20 εync pulse must occur. If vertical sync iε loεt for one reaεon or another εuch that a vertical εync pulse does not occur during this narrow window pulse, counter 144 provides a decode signal at count 526 through "OR" gate 160 to produce a reset pulse to the counter. However, after eight

25 missing sync pulses window control circuit 130 defaults to a wide window mode to vary the gain of phase detector 108 as well as to open ^" the period that the gates of reset cirucit 150 are enabled. In th. = wide window mode, gate 152 is disabled by coincidence detector 148 which therefore

30 enables wide window latch 162 to enable the gates of reset counter 150 at the 86th count from counter 144. Simultaneously, gate 160 is enabled to provide a decode signal at the 546th count. Thus, a wide window pulse is initiated to occur between the 86th and 546th count. As

35 soon as a vertical sync pulse is acquired during the wide window mode, window control circuit 130 reverts back to the

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narrow window mode of operation. Hence, during normal operating conditions a narrow window mode of opeation is established in television subsystem 50 to inhibit noise interfering with vertical synchronization of the televisio receiver with a wide window mode being defaulted to when vertical sync pulses are lost for one reason or another to thereby allow fast acquisition thereof.

Thus, what has been described iε a single chip integrated circuit that will perform the electronic functions of a monochrome television receiver with the exception of the tuner, sound channel and power output stages. It iε to be understood that the aforedescribed single chip integrated circuit can be utilized in conjunction with a chroma demodulator detector stage to provide a color television receiver.