Title:
LEVEL CONVERSION CIRCUIT AND CHIP
Document Type and Number:
WIPO Patent Application WO/2023/035513
Kind Code:
A1
Abstract:
Provided in the present invention are a level conversion circuit and a chip. The level conversion circuit comprises first/second/third/fourth PMOS transistors, first/second/third/fourth NMOS transistors, and an inverter. The source electrode of the first PMOS transistor is connected to an I/O power supply, the drain electrode thereof is connected to a first node, and the gate electrode thereof is connected to a second node. The drain electrode of the first NMOS transistor is connected to the first node, the source electrode thereof is grounded, and the gate electrode thereof is connected to an input signal. The source electrode of the second PMOS transistor is connected to the I/O power supply, the drain electrode thereof is connected to the second node, and the gate electrode thereof is connected to the first node. The drain electrode of the second NMOS transistor is connected to the second node, the source electrode thereof is grounded, the gate electrode thereof is connected to an output terminal of the inverter, and an input terminal of the inverter is connected to the input signal.
Inventors:
YAN HUIJIE (CN)
WEN JIANXIN (CN)
JIANG YU (CN)
SHEN LING (CN)
ZENG XI (CN)
WEN JIANXIN (CN)
JIANG YU (CN)
SHEN LING (CN)
ZENG XI (CN)
Application Number:
PCT/CN2021/143850
Publication Date:
March 16, 2023
Filing Date:
December 31, 2021
Export Citation:
Assignee:
SHANGHAI IC R&D CT CO LTD (CN)
SHANGHAI ISHANGHAI INTEGRATED CIRCUIT EQUIPMENT & MAT INDUSTRY INNOVATION CENTER CO LTD (CN)
SHANGHAI ISHANGHAI INTEGRATED CIRCUIT EQUIPMENT & MAT INDUSTRY INNOVATION CENTER CO LTD (CN)
International Classes:
H03K19/0185
Attorney, Agent or Firm:
SHANGHAI IFUTURE INTELLECTUAL PROPERTY LAW FIRM (CN)
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