BACKGROUND

[0001] Radio frequency (RF) power amplifiers are used in modem digital telecommunications to amplify RF signals as needed for transmission to base stations and other devices. As communication bandwidth continues to come at a premium and more communication standards adopt RF power amplifier linearity requirements, it has become increasingly challenging to design RF power amplifiers that both maintain high linearity and leverage power saving techniques.

SUMMARY

[0002] The present disclosure relates to linearity -preserving amplifiers, including radio-frequency (RF) power amplifiers.

[0003] The subject matter described in this specification can be implemented in particular embodiments so as to realize one or more of the following advantages. For example, in some implementations, by leveraging one or more of the RF power amplifier configurations described herein, components and techniques conducive to minimizing power consumption and achieving other benefits may be employed without substantially sacrificing linearity. As described in further detail below, in some examples, one or more of the RF power amplifier configurations described herein feature a bias circuit that includes a boost circuit and an emitter follower circuit that operate in tandem to dynamically counteract nonlinear distortion and/or other effects introduced at least in part by such components and techniques.

[0004] In general, one innovative aspect of the subject matter described in this specification can be embodied in a radio frequency (RF) power amplifier including a driver amplifier circuit, a power amplifier circuit including multiple amplifier bipolar junction transistors (BJTs), an inter-stage impedance matching network connecting an output of the driver amplifier circuit to a first input of the power amplifier circuit, and a bias circuit connecting the output of the driver amplifier circuit to a second input of the power amplifier circuit. The bias circuit is configured to provide a bias voltage to the second input of the power amplifier circuit. The bias circuit includes an emitter follower circuit and a boost circuit. The emitter follower circuit includes a bias BJT and is configured to provide a first voltage. The boost circuit is configured to sample an RF signal from the output of the driver amplifier circuit and pass the sampled RF signal to the emitter follower circuit for rectification from which a second voltage is generated. The second voltage is proportional to a magnitude of a level of power exhibited by the RF signal. The bias voltage is a combination of the first voltage and the second voltage.

[0005] In some implementations, the boost circuit includes a capacitor. In at least some of these implementations, the boost circuit further includes a load element arranged in series with the capacitor.

[0006] In some examples, the power amplifier circuit includes a plurality of amplifier BJTs. In some such examples, the power amplifier circuit further includes a plurality of load elements that are each located between a base terminal of a respective amplifier BJT of the plurality of amplifier BJTs and the second input of the power amplifier circuit. [0007] In any one of these examples, the plurality of amplifier BJTs of the power amplifier circuit are arranged in an array, and the plurality of load elements operable to evenly distribute the bias voltage across the array. In any one of the aforementioned examples, the base terminal of each amplifier BJT is further coupled to the first input of the power amplifier circuit. In any one of the aforementioned examples, the power amplifier circuit further includes a plurality of capacitors that are each located between the base terminal of a respective amplifier BJT of the plurality of amplifier BJTs and the first input of the power amplifier circuit.

[0008] In any one of the aforementioned examples, a collector terminal of each amplifier BJT is connected to a common output of the power amplifier circuit. In any one of the aforementioned examples, the bias circuit and the power amplifier circuit are configured to cause each amplifier BJT to operate in a deep class-AB mode. In any one of the aforementioned examples, each amplifier BJT includes a heterojunction bipolar junction transistor (HBT).

[0009] In some implementations, the bias circuit includes a first bias load element located between an emitter terminal of the bias transistor of the emitter follower circuit and the second input of the power amplifier circuit. In some of these implementations, the bias circuit is configured to compensate for bias modulation introduced at least in part by the first bias load element. In some implementations, the boost circuit connects two points in the RF power amplifier including (i) a first point located between the output of the driver amplifier circuit and the first input of the power amplifier circuit and (ii) a second point located at the emitter terminal of the bias BJT. In some implementations, the first point in the RF power amplifier is located between the output of the driver amplifier circuit and an input of the inter-stage impedance matching network. In some implementations, the first point in the RF power amplifier is located between an input of the inter-stage impedance matching network and the first input of the power amplifier circuit.

[0010] In some examples, the RF power amplifier further includes an output impedance matching network connected to an output of the power amplifier circuit.

[0011] In some implementations, the bias circuit further includes multiple electronic components connected to a base terminal of the bias BJT of the emitter follower circuit. [0012] In some examples, at least one of a base terminal of the bias BJT of the emitter follower circuit and a collector terminal of the bias BJT of the emitter follower circuit is connected to a respective DC current source.

[0013] In some implementations, the inter-stage impedance matching network includes a load element and multiple additional components, the multiple additional components including one or more inductors, one or more capacitors, or a combination thereof.

[0014] In some implementations, the bias circuit includes: a power supply; a first BJT; and a second BJT, in which the power supply, the first BJT and the second BJT are coupled in series. In some implementations, a base of the first BJT is shorted to a collector of the first BJT, and a base of the second BJT is shorted to a collector of the second BJT. In some implementations, the bias circuit includes a bias capacitor coupled across the first BJT and the second BJT.

[0015] In some examples, an emitter terminal of the bias BJT of the emitter follower circuit is configured to provide the first voltage.

[0016] The foregoing and other embodiments can each optionally include one or more of the features described herein, alone or in combination. In particular, one embodiment includes all the following features in combination.

[0017] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below.

Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS [0018] FIG. 1 is a diagram of an example wireless communication system

[0019] FIG. 2 is a diagram of example details of a wireless device that may implement the methods and teachings according to this disclosure.

[0020] FIGS. 3A-3B are diagrams of an example RF power amplifier.

[0021] FIGS. 4A-4B are diagrams of an example linearity-preserving RF power amplifier.

[0022] FIG. 5 is a graph that reflects base bias voltage at an emitter follower circuit as a function of output power as exhibited by two example RF power amplifiers.

[0023] FIG. 6 is a graph that reflects base bias voltage at a power amplifier circuit as a function of output power as exhibited by two example RF power amplifiers.

DETAILED DESCRIPTION

[0024] FIG. 1 shows an example wireless communication system 100 including a wireless device 110 capable of communicating with one or more wireless communication networks. The one or more wireless communication networks with which the wireless device 110 is capable of communicating can include but is not limited to one or more cellular or wireless wide area networks (WWANs), one or more wireless local area networks (WLANs), one or more wireless personal area networks (WPANs), or a combination thereof.

[0025] In the example of FIG. 1, the wireless device 110 is communicating with at least one WWAN by way of at least one base station 120, at least one WLAN by way of at least one access point 130, and at least one personal area network (PAN) by at least one PAN device 140. The at least one base station 120 can support bi-directional communication with wireless devices that are within its corresponding area of coverage 122. Similarly, the at least one access point 130 can support bi-directional communication with wireless devices that are within its corresponding area of coverage 132.

[0026] In some implementations, the at least one WWAN with which the at least one base station 120 is associated can be a fifth generation (5G) network among other generations and ty pes of networks. In these implementations, the at least one base station 120 can be a 5G base station that employs orthogonal frequency-division multiplexing (OFDM) and/or non-OFDM and a transmission time interval (TTI) shorter than 1 ms (e.g. 100 or 200 microseconds), to communicate with wireless devices, such as wireless device 110. For example, the at least one base station 120 can take the form of one of several devices, such as a base transceiver station (BTS), aNode-B (NodeB), an evolved NodeB (eNB), a next (fifth) generation (5G) NodeB (gNB), a Home NodeB, a Home eNodeB, a site controller, an access point, or a wireless router, or a server, router, switch, or other processing entity with a wired or wireless network. In addition, and as shown in FIG. 1, wireless device 110 is configured to communicate with one or more personal area network (PAN) devices/systems 140 (e.g., Bluetooth® or radio frequency identification (RFID) systems and devices) over one or more WPANs.

[0027] System 100 can use multiple channel access functionality including for example schemes in which the at least one base station 120 and the wireless device 110 are configured to implement the Long Term Evolution wireless communication standard (LTE), LTE Advanced (LTE-A), and/or LTE Multimedia Broadcast Multicast Service (MBMS). In other implementations, the at least one base stations 120 and wireless device 110 are configured to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols can be utilized. In some examples, one or more such access schemes and wireless protocols can correspond to standards that impose RF power amplifier linearity requirements.

[0028] In order to communicate with one or both of the at least one base station 130 and the access point 130, the wireless device 110 can include singular or multiple transmitter and receiver components similar or equivalent to one or more of those described in further detail below with reference to FIG. 2 to support multiple communications with different types of access points, base stations and other wireless communication devices. The transmitter component of the wireless device 110 can include an RF power amplifier configured to amplify RF signals as needed for transmission to one or both of the at least one base station 120 and the access point 130. For instance, as the wireless device 110 moves toward an outer edge of the area of coverage 122 and further into the area of coverage 132, the transmitter component of the wireless device 110 can leverage its RF power amplifier to transmit RF signals destined for the at least one WWAN with increased amplification so as to increase the likelihood that such RF signals reach the at least one base station 120 with minimal degradation. Additionally or alternatively, in this same scenario, the transmitter component of the wireless device 110 can leverage its RF power amplifier to transmit RF signals destined for the at least one WLAN with reduced amplification so as to achieve power savings while sufficiently maintaining communication with the at least one access point 130. Examples of transmitter components and RF power amplifiers that can be employed in wireless device 110 and other similar devices are described in further detail below with reference to FIGS. 2-6. Although FIG. 1 illustrates one example of a communication system, various changes can be made to FIG. 1. For example, the communication system 100 could include any number of wireless devices, base stations, access points, networks, or other components in any suitable configuration.

[0029] FIG. 2 illustrates example details of the wireless device 110 that can implement the methods and teachings according to this disclosure. The wireless device 110 can, for example, be a mobile telephone, but can be other devices in further examples such as a desktop computer, laptop computer, tablet, hand-held computing device, automobile computing device and/or other computing devices. As shown in the figure, the wireless device 110 is shown as including at least one transmitter 210, at least one receiver 220, memory 230, at least one processor 240, and at least one input/output device 260. Here, only one transmitter and only one receiver are shown, but in many embodiments, multiple transmitters and receivers are included to support multiple communications of different types at the same time. Each transmitter may employ the innovations of the present disclosure.

[0030] The processor 240 can implement various processing operations of the wireless device 110. For example, the processor 240 can perform signal coding, data processing, power control, input/output processing, or any other functionality enabling the wireless device 110 to operate in the system 100 (FIG. 1). The processor 240 can include any suitable processing or computing device configured to perform one or more operations. For example, the processor 240 can include a microprocessor, microcontroller, digital signal processor, field programmable gate array, or application specific integrated circuit or a combination of these devices.

[0031] The transmitter 210 is configured to modulate data or other content for transmission by at least one antenna 250A. The transmitter 210 can also be configured to amplify, filter and upconvert baseband or intermediate frequency signals to radio frequency (RF) signals before such signals are provided to the a power amplifier and then to antenna 250A for transmission. The transmitter 210 can include any suitable stmcture for generating signals for wireless transmission. Additional aspects of the transmitter 210 are described in further detail below with reference to components 212-218 as depicted in FIG. 2.

[0032] The receiver 220 can be configured to demodulate data or other content received by at least one antenna 250B. The receiver 220 can also be configured to amplify, filter and frequency convert RF signals received via the antenna 250B. The receiver 220 can include any suitable structure for processing signals received wirelessly. [0033] Each of the antennas 250 A and 250B can include any suitable structure for transmitting and/or receiving wireless signals. In some implementations, the antennas 250A and 250B can be implemented by way of a single antenna that can be used for both transmitting and receiving RF signals.

[0034] It is appreciated that one or multiple transmitters 210 could be used in the wireless device 110, one or multiple receivers 220 could be used in the wireless device 110, and one or multiple antennas 250 could be used in the wireless device 110. Although shown as separate blocks or components, at least one transmitter 210 and at least one receiver 220 could be combined into a transceiver. Accordingly, rather than showing a separate block for the transmitter 210 and a separate block for the receiver 220 in FIG. 2, a single block for a transceiver could have been shown.

[0035] The wireless device 110 further includes one or more input/output devices 260. The input/output devices 260 facilitate interaction with a user. Each input/output device 260 includes any suitable structure for providing information to or receiving information from a user, such as a speaker, microphone, keypad, keyboard, display, or touch screen.

[0036] In addition, the wireless device 110 includes at least one memory 230. The memory 230 stores instructions and data used, generated, or collected by the wireless device 110. For example, the memory 230 could store software or firmware instructions executed by the processor(s) 240 and data used to reduce or eliminate interference in incoming signals. Each memory 230 includes any suitable volatile and/or non-volatile storage and retrieval device(s). Any suitable type of memory may be used, such as random access memory (RAM), read only memory (ROM), hard disk, optical disc, subscriber identify module (SIM) card, memory stick, secure digital (SD) memory card, and the like.

[0037] In some implementations, the transmitter 210 can include signal processing circuitry 212, modulation circuitry 214, a power amplifier 216, and at least one filter 218. The signal processing circuitry 212 may include one or more circuits that are configured to process signals received as input (e.g. from processor 240). For example, the signal processing circuitry 212 may include a digital-to-analog converter (D/A), which converts a digital input (e.g. from processor 240) into an analog signal which is then provided to a low pass filter, which filters the analog signal and provides the filtered analog signal to the modulation circuitry 214. The modulation circuitry 214, in addition to receiving the filtered analog signal from the signal processing circuitry 212, also receives a signal from a local oscillator 215 and modulates or adjusts the frequency of the RF signal, e.g. from a first frequency to a second frequency that is higher than the first frequency. For instance, the modulation circuitry 214 may include a mixer that frequency up-converts the filtered analog signal from a relatively low frequency (e.g. baseband frequency, or an intermediate frequency (IF) that is offset from the baseband frequency) to a relatively high frequency RF signal. Thus, a signal from the local oscillator 215 is used as a carrier signal in transmitter 210. Moreover, as shown in FIG. 2, transmitter 210 includes an RF front end 217, which includes amplification and filtering circuits that filter and amplify the RF signal before providing the RF signal to the power amplifier 216 [0038] The RF signal from the RF front end 217 is then amplified by the power amplifier 216 and filtered by the at least one filter 218 before being provided as output of the transmitter 210 to the at least one antenna 250A for wireless transmission. Although FIG. 2 shows the filter 218 as downstream from the power amplifier 216, in some implementations, the filter 218 can be upstream from the power amplifier 216 in which case the RF signal from the RF front end 217 is first filtered by the at least one filter 218 and then amplified by the power amplifier 216 before being provided as output of the transmitter 210 to the at least one antenna 250A for wireless transmission. In some examples, the transmitter 210 can further include a pre-power amplifier or other circuitry that connects the modulation circuitry 214 to the power amplifier 216. In some implementations, the power amplifier 216 corresponds to the RF power amplifier 300 or the RF power amplifier 400 as described in further detail below with reference to FIGS. 3A-3B and 4A-4B, respectively.

[0039] FIGS. 3A-3B are diagrams of an example RF power amplifier 300. In the example of FIGS. 3A-3B, the RF power amplifier 300 includes a driver amplifier circuit 310, an inter-stage impedance matching network 320, a bias circuit 330, a power amplifier circuit 340, and an output impedance matching network 350. The RF power amplifier 300 can be a multi-stage RF power amplifier, where the driver amplifier circuit 310 and the power amplifier circuit 340 represent two adjacent amplifier stages that are connected by way of the inter-stage impedance matching network 320. As mentioned above, in some implementations, the RF power amplifier 300 can correspond to the power amplifier 216 as described above with reference to FIG. 2, which may be implemented in wireless device 110 as described above with reference to FIG. 1 or another similar wireless device.

[0040] The driver amplifier circuit or “stage” 310 is configured to receive an RF signal from one or more upstream components (e.g., the modulation circuitry 214) through its input 311, amplify the received RF signal, and transmit the amplified RF signal through its output 312. As shown in FIG. 3B, in some examples, the driver amplifier circuit 310 includes a capacitor C4 and a resistor R2 that are connected to a base terminal of anNPN bipolar junction transistor Q9.

[0041] The inter-stage impedance matching network 320 connects the output 312 of the driver amplifier circuit 310 to a first input 341 A of the power amplifier circuit 340. More specifically, the output 312 of the driver amplifier circuit 310 is connected to an input 321 of the inter-stage impedance matching network 320, and an output 322 of the inter-stage impedance matching network 320 is connected to the first input 341 A of the power amplifier circuit 340. In general, the inter-stage impedance matching network 320 is configured to perform impedance matching to resolve a mismatch in impedance between the driver amplifier circuit or “stage” 310 and the power amplifier circuit or “stage” 340. The inter-stage impedance matching network 320 can include one or more circuits that include one or more resistors, one or more capacitors, one or more inductors, or a combination thereof. Other configurations are possible.

[0042] The power amplifier circuit or “stage” 340 is configured to receive the RF signal as amplified by the driver amplifier circuit 310 from the inter-stage impedance matching network 320 through its first input 341A, amplify the received RF signal, and transmit the amplified RF signal through its output 342. As shown in FIG. 3B, in some examples, the power amplifier circuit 340 includes an array of amplifier circuits, each of which includes a respective capacitor C4 and a respective resistor R2 that are connected to a base terminal of a respective NPN bipolar junction transistor (BJT) (Q4-Q8, also referred to herein as “amplifier BJTs”). In some implementations, the values of each capacitor C4 and each resistor R2 in the power amplifier circuit 340 can be similar or equivalent in value to those of capacitor C4 and resistor R2 in the driver amplifier circuit 310. In other implementations, the values of each capacitor C4 and each resistor R2 in the power amplifier circuit 340 can be different than those of capacitor C4 and resistor R2 in the driver amplifier circuit 310. In general, resistors R2 and other resistors described herein may represent examples of load elements. As such, resistors R2 and other resistors described herein are, in some instances, referred to as load elements.

[0043] Given that the relationship between input and output for a BJT is not linear across its full operating range, each amplifier circuit of the power amplifier circuit 340 approximates linear operation. In order to minimize distortion, each amplifier BJT of the power amplifier circuit 340 is biased so as to prevent each amplifier BJT from being driven into a region of extremely nonlinear operation. In some examples, the bias circuit 330 can be leveraged to provide such biasing functionality. Thus, by utilizing a plurality of amplifiers biased as described in an array, the power amplifier circuit 340, as a whole, produces a linear output to satisfy linearity requirements.

[0044] The bias circuit 330 is configured to provide a bias voltage through its output 332 to a second input 341B of the power amplifier circuit 340. In general, the bias voltage provided by the bias circuit 330 can bias the amplifier BJTs in the array of amplifier circuits of the power amplifier circuit 340 in a manner so that each amplifier BJT operates in a particular region of its respective transconductance curve. In some implementations, the bias circuit 330 includes an emitter follower circuit 334. More specifically, as shown in FIG. 3B, the emitter follower circuit 334 can include an NPN BJT Q1 (referred to herein as a “bias bipolar junction transistor”) that is connected to one or more components in an emitter follower or “common collector” configuration, such as a resistor R1. While the resistor R1 can represent an “emitter resistor” of the emitter follower circuit 334, it can additionally or alternatively represent a biasing resistor that serves to at least in part dictate the current and/or voltage with which the power amplifier circuit 340 is biased.

The bias circuit 330 also can include one or more DC current sources and one or more components that are coupled to the base and collector terminals of the NPN bias BJT Ql. In some implementations, one or more of the aforementioned amplifier BJTs of the RF power amplifier 300 are heterojunction bipolar transistors (HBTs).

[0045] The output impedance matching network 350 connects the output 342 of the power amplifier circuit 340 to one or more downstream components (e.g., the at least one filter 218, the at least one antenna 250A, etc.). More specifically, the output 342 of the power amplifier circuit 340 is connected to an input 351 of the output impedance matching network 350, and an output 352 of the output impedance matching network 350 is connected to one or more inputs of one or more components downstream from the RF power amplifier 300, such as one or more filters, one or more antennas, or a combination thereof. In general, the output impedance matching network 350 is configured to perform impedance matching to provide a desired load to the power amplifier circuit 340 from one or more downstream components. Much like the inter-stage impedance matching network 320, the output impedance matching network 350 can include one or more circuits that include one or more resistors, one or more capacitors, one or more inductors, or a combination thereof. Other configurations are possible.

[0046] Referring once again to the power amplifier circuit 340 and the bias circuit 330, in some applications, it may be particularly advantageous to employ resistors that have relatively high resistance values as resistors R1 and R2 in the bias circuit 330 and the power amplifier circuit 340. For instance, by employing resistors that have relatively high resistance values as resistors R2 in the power amplifier circuit 340, the resistors R2 evenly distribute the DC bias provided by the bias circuit 330 across the array of amplifier circuits in the power amplifier circuit 340 so as to more effectively prevent or reduce the likelihood of current or thermal runaway in the power amplifier circuit 340. In this way, the resistors R2 may effectively serve as ballasting resistors for the power amplifier circuit 340. In some examples, the value of each resistor R2 may be greater than a minimum value determined based on the specifications of one or more components in the power amplifier circuit 340, such as the amplifier BJTs. For example, each resistor R2 may have a resistance value of around 400 W. Furthermore, by employing a resistor that has a relatively high resistance value as resistor R1 in the bias circuit 330, the quiescent current (which is the current at the zero input condition of the transistor) of the BJTs in the power amplifier circuit 340 may be set to a relatively low value, such that the transistors consume less power during their off state. For example, employing such a resistor as resistor R1 in the bias circuit 330 can cause each BJT in the power amplifier circuit 340 to operate in a class-AB mode, such that the transistors are not operating at all times. In some examples, the class-AB mode may be relatively deep in nature such that the quiescent current of the BJTs in the power amplifier circuit 340 can be set to a value that is on the lower end of the range of quiescent currents associated with class-AB operation. Such a mode of operation is at times referred to herein as a “deep class-AB” mode of operation. This mode of operation can yield substantial power savings as a result of the conduction angle being between 180° to 270°, with greater efficiency obtainable closer towards 180°, where the device is on for only about half a cycle. For example, the resistor R1 may be employed with high resistance values in the hundreds of ohms in order to place the power amplifier circuit 340 into a deep class-AB mode of operation, while it might otherwise be employed with low resistance values in the tens of ohms in situations where deep class-AB mode of operation is not required. The resistance provided by resistors R2 in parallel can also serve to help place the amplifier BJTs of the power amplifier circuit 340 in such a mode.

[0047] Employing resistors that have relatively high resistance values as resistors R1 and R2 in the bias circuit 330 and the power amplifier circuit 340 also can, in some implementations, introduce significant bias modulation at the base terminal of each amplifier BJT in the power amplifier circuit 340 and thus cause significant nonlinear distortion. Examples of the types of adverse effects that might be produced in the RF power amplifier 300 include amplitude-to-amplitude modulation (AM/ AM) and amplitude-to-phase modulation (AM/PM). Moreover, as RF output power is increased during operation, the power amplifier circuit 340 may demand additional current, which may result in an undesired drooping of the DC bias voltage at the base terminal of each amplifier BJT in the power amplifier circuit 340, which may cause a collapse in gain or early compression. This early compression may significantly degrade the linear performance of the power amplifier circuit 340 and force the RF power amplifier 300 to operate with less current, which can be highly inefficient. One or more of the aforementioned effects of employing resistors that have relatively high resistance values are reflected in the function 610 as shown in FIG. 6 and described in further detail below. Given that linearity has bearing on communication bandwidth and must also meet certain requirements under many modem wireless communications protocols (e.g., WCDMA, LTE, 5G, WiFi, etc.), employing ballasting and biasing resistors that have relatively high resistance values may be difficult to achieve or yield poor performance in many RF power amplifier systems.

[0048] In some implementations, one or more of the RF power amplifier configurations described in further detail below can be leveraged to achieve the benefits that come with employing ballasting and biasing resistors that have relatively high resistance values without substantially sacrificing linearity. FIGS. 4A-4B are diagrams of an example linearity -preserving RF power amplifier 400. In the example of FIGS. 4A-4B, the RF power amplifier 400 includes a driver amplifier circuit 410, an inter-stage impedance matching network 420, a bias circuit 430, a power amplifier circuit 440, and an output impedance matching network 450. In some implementations, each of one or more of elements 410-430, 432, 434, and 440-452 as depicted in FIGS. 4A-4B is similar or equivalent to each of one or more of elements 310-330, 332, 334, and 340-352 as depicted in FIGS. 3A-3B, respectively. As mentioned above, in some implementations, the linearity-preserving RF power amplifier 400 can correspond to the power amplifier 216 as described above with reference to FIG. 2, which may be implemented in wireless device 110 as described above with reference to FIG. 1 or another similar wireless device. [0049] In the example of FIGS. 4A-4B, the bias circuit 430 includes a boost circuit 436. The boost circuit 436 is configured to sample the RF signal output by the driver amplifier circuit 410 and pass the sampled RF signal to the emitter follower circuit 434 of the bias circuit 430. More specifically, as shown in FIG. 4B, the boost circuit 436 connects two points in the RF power amplifier 400 including (i) a first point PI located between the output 412 of the driver amplifier circuit 410 and the first input 441 A of the power amplifier circuit 440, and (ii) a second point P2 located between the NPN bias BJT Q1 in the emitter follower circuit 434 and the resistor R1 of the bias circuit 430 (e.g., at the emitter terminal of the NPN bias BJT Ql). For example, the first point PI may be located between the output 412 of the driver amplifier circuit 410 and the input 421 of the inter-stage impedance matching network 420, or may be located between the input 421 of the inter-stage impedance matching network 420 and the output 422 of the inter-stage impedance matching network 420 (i.e., within the inter-stage impedance matching network 420).

[0050] As described in FIG. 4B, the bias circuit 430 is configured to provide a bias voltage through its output 432 to a second input 441B of the power amplifier output stage circuit 440. As shown in FIG. 4B, bias circuit 430 includes diode-collected bipolar transistors Q2 and Q3, and when a DC current is injected into Q2 and Q3, a voltage is formed at the collector of Q2. This voltage is reduced by the voltage from the NPN BJT Ql in the emitter follower circuit 434, resulting in the bias voltage at P2, which is provided via output 432 to the power amplifier output stage circuit.

[0051] By virtue of the emitter follower or “common collector” configuration of the NPN bias BJT Ql and other components in the bias circuit 430, once passed to the emitter follower circuit 434 of the bias circuit 430, the sampled RF signal is rectified to become an additional DC voltage with which the power amplifier circuit 440 is biased. That is, in this configuration, the PN junction between the base and emitter terminals of the bias BJT Q1 acts like a diode from which an additional DC voltage proportional to the magnitude of the power of the sampled RF signal is generated. The “boost” that is provided by this additional DC voltage may serve to effectively compensate for nonlinear distortion introduced at least in part by way of resistors R1 and R2. As such, the RF power amplifier 400 may employ resistors that have relatively high resistance values as resistors R1 and R2 in the bias circuit 430 and the power amplifier circuit 440 so as to combat current or thermal runaway in the power amplifier circuit 440 and achieve power savings by causing the amplifier BJTs (Q4-Q8) of the power amplifier circuit 440 to operate in a deep class- AB mode, and the boost circuit 436 may serve to preserve linearity in the power amplifier circuit 440, which might otherwise be threatened by the relatively high resistance values of resistors R1 and R2. For example, resistors R1 and R2 as implemented in the RF power amplifier 400 may have resistance values of 120 W and 400 W, respectively.

[0052] As shown in FIG. 4B, the boost circuit 436 can include a capacitor C7 arranged in series with a resistor R3. The values of capacitor C7 and resistor R3 can be selected based on a variety of different factors. For instance, in some implementations, the value of capacitor C7 is selected based at least in part on the frequency at which the RF signal is modulated upstream from the RF power amplifier 400. Within the context of FIG. 2, this might correspond to the frequency of the signal that is produced by the local oscillator 215. While the arrangement of capacitor C7 and resistor R3 in the boost circuit 436 represent one ty pe of passive filter, in some examples, the boost circuit 436 can include one or more components that form or otherwise represent another type of passive filter. In some implementations, the boost circuit 436 can include only capacitor C7 and not include resistor R3. Other configurations are possible.

[0053] FIG. 5 shows a graph that reflects base bias voltage at an emitter follower circuit as a function of output power as exhibited by two example RF power amplifiers. A first one of the two example RF power amplifiers represents an RF power amplifier similar or equivalent to that of the RF power amplifier 300, as described above with reference to FIGS. 3A-3B, as implemented with ballasting and/or biasing resistors (e.g., Rl, R2, etc.) with relatively high resistance values. The second of the two example RF power amplifiers represents an RF power amplifier similar or equivalent to that of the linearity-preserving RF power amplifier 400 as described above with reference to FIGS. 4A-4B. The y-axis of graph 500 is a DC voltage at the emitter terminal of a transistor in an emitter follower circuit in volts (V) referenced to ground or with respect to ground and the x-axis of graph 500 is the output power of one or more components of the example RF power amplifier to which the emitter follower circuit belongs in decibel-milliwatts (dBm).

[0054] Function 510, as depicted in FIG. 5, represents characteristics of the first one of the two example RF power amplifiers, which can be similar or equivalent to that of the RF power amplifier 300 as described above with reference to FIGS. 3A-3B. As such, function 510 represents a DC voltage as measured at the emitter terminal of a transistor in an emitter follower circuit with reference to ground as a function of output power, which may be similar or equivalent to a DC voltage as measured across the at the emitter terminal of the NPN bias BJT Q1 in the emitter follower circuit 334 with reference to ground as a function of the output power of the driver amplifier circuit 310. Function 520, as depicted in FIG. 5, represents characteristics of the second of the two example RF power amplifiers, which may be similar or equivalent to that of the linearity-preserving RF power amplifier 400 as described above with reference to FIGS. 4A-4B. As such, function 520 represents a DC voltage as measured at the emitter terminal of a transistor in an emitter follower circuit with reference to ground as a function of output power, which may be similar or equivalent to a DC voltage as measured at the emitter terminal of the NPN bias BJT Q1 in the emitter follower circuit 434 with reference to ground as a function of the output power of the driver amplifier circuit 410. As indicated by the differences in functions 510 and 520, the emitter follower circuit 434 and the boost circuit 436 are configured to cooperatively produce an additional DC voltage at the emitter terminal of NPN bias BJT Q1 that is proportional to the output power of the driver amplifier circuit 410.

[0055] FIG. 6 shows a graph that reflects base bias voltage at a power amplifier circuit as a function of output power as exhibited by two example RF power amplifiers. A first one of the two example RF power amplifiers represents an RF power amplifier similar or equivalent to that of the RF power amplifier 300, as described above with reference to FIGS. 3A-3B, as implemented with ballasting and/or biasing resistors (e.g., Rl, R2, etc.) with relatively high resistance values. The second of the two example RF power amplifiers represents an RF power amplifier similar or equivalent to that of the linearity-preserving RF power amplifier 400 as described above with reference to FIGS. 4A-4B. The y-axis of graph 600 represents a base bias voltage at a power amplifier circuit in volts (V) and the x-axis of graph 600 represents the output power of one or more components of the example RF power amplifier to which the power amplifier circuit belongs in decibel-milliwatts (dBm).

[0056] Function 610, as depicted in FIG. 6, represents characteristics of the first one of the two example RF power amplifiers, which may be similar or equivalent to that of the RF power amplifier 300 as described above with reference to FIGS. 3A-3B. As such, function 610 represents a voltage as measured across the base and emitter terminals of a transistor in a power amplifier circuit as a function of output power, which may be similar or equivalent to a voltage as measured across the base and emitter terminals of one of the NPN amplifier BJTs in the power amplifier circuit 340 as a function of the output power of the driver amplifier circuit 310 or a voltage as measured across the base and emitter terminals of a transistor that is representative of some or all of the NPN amplifier BJTs in the power amplifier circuit 340 as a function of the output power of the driver amplifier circuit 310. Function 620, as depicted in FIG. 6, represents characteristics of the second of the two example RF power amplifiers, which may be similar or equivalent to that of the linearity-preserving RF power amplifier 400 as described above with reference to FIGS. 4A-4B. As such, function 620 represents a voltage as measured across the base and emitter terminals of a transistor in a power amplifier circuit as a function of output power, which may be similar or equivalent to a voltage as measured across the base and emitter terminals of one of the NPN amplifier BJTs in the power amplifier circuit 440 as a function of the output power of the driver amplifier circuit 410 or a voltage as measured across the base and emitter terminals of a transistor that is representative of some or all of the NPN BJTs in the power amplifier circuit 440 as a function of the output power of the driver amplifier circuit 410. As indicated by the differences in functions 610 and 620, the emitter follower circuit 434 and the boost circuit 436 offer improved compensation for nonlinear distortion and DC bias voltage drooping introduced at least in part by ballasting and biasing resistors with relatively high resistance values (e.g., R1 and R2). Indeed, function 620 exhibits far less variance in base bias voltage than function 610 does, which indicates that linearity is preserved to a relatively great extent in the RF power amplifier associated with function 620. [0057] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially be claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0058] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0059] In addition, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of the present disclosure. Other items shown or discussed as coupled or directly coupled or communicating with each other may be indirectly coupled or communicating through some interface, device, or intermediate component whether electrically, mechanically, or otherwise. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and could be made without departing from the spirit and scope disclosed herein.

[0060] For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them.

[0061] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.