TECHNICAL FIELD

[0001] The present disclosure is generally related to SSD (Solid State Drive) controllers, and specifically to methods for saving NAND (Not-AND) flash memory on-die SRAM (Static Random Access Memory) write buffer storage under power loss conditions.

BACKGROUND

[0002] SSDs store data in solid state devices, rather than in a magnetic or optical medium. A typical SSD comprises a controller and solid state memory devices. A host device performs write and read operations on the SSD. In response, the SSD acknowledges receipt of the data, stores the data, and subsequently retrieves data.

[0003] Newly developed flash memory devices include SRAM and other circuits (collectively referred to as peripheral circuitry) as well as flash memory in the device. Such chips may be so- called three dimensional (3D) devices or four dimensional (4D) devices, depending on whether the peripheral circuitry is located, respectively, beside or beneath the flash memory of the device. In the process of storing data in the flash memory, the controller of the SSD first stores the data in a write buffer in the on-die SRAM of the flash memory, then instructs the flash memory device to write the data from the write buffer to flash memory.

SUMMARY

[0004] A first aspect relates to a power-loss backup method for a write buffer in Static Random Access Memory (SRAM) implemented by a controller of a flash memory device. The method includes obtaining a reduction factor («) for programming energy (Ep); obtaining a list of backup 1

SUBSTITUTE SHEET (RULE 26) storage cells in a single-level cell (SLC) memory region of the flash memory device; setting a programming power supply for the SLC memory region to produce reduced Ep programming write pulses based on a value of l/«; and writing individual bits of the write buffer into cells of the list of backup storage cells using the reduced Ep programming write pulses.

[0005] Optionally, in any of the preceding aspects, another implementation of the aspect provides further comprising: prior to writing the bits of the write buffer into cells of the list of backup storage cells, randomizing each SLC memory page of the write buffer using a key generated from address information of the SLC memory page.

[0006] A second aspect relates to a power-loss backup method for a write buffer in SRAM implemented by a controller of a flash memory device. The method includes obtaining a reduction factor (//) for programming energy (Ep); obtaining a list of backup storage cells in a single-level cell (SLC) memory region of the flash memory device; setting a programming power supply for the SLC memory region to produce reduced Ep programming write pulses based on a value of 1/M; derandomizing each multiple-level cell (Multiple-LC) memory page of the write buffer using a key generated from address information of the Multiple-LC memory page; randomizing each SLC memory page of the write buffer using a key generated from address information of the SLC memory page; adding error-correcting code (ECC) bits to each SLC memory page of the write buffer; and writing individual bits of the write buffer into cells of the list of backup storage cells using the reduced Ep programming write pulses.

[0007] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the flash memory device is a NAND flash memory device.

2

SUBSTITUTE SHEET (RULE 26) [0008] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the controller of the flash device in response to receipt of a power loss command from a device external to the flash device.

[0009] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the reduced Ep programming write pulses have an energy equal to 1/n times an energy of a programming write pulse (standard write pulse) produced by the programming power supply in power-on conditions.

[0010] Optionally, in any of the preceding aspects, another implementation of the aspect provides that: the list of backup storage cells has a size equal to a copies factor (k) times a number of bits in the write buffer, where k is an odd number; the reduced Ep programming write pulses have an energy equal to !k*n times the standard write pulse energy; and each of the bits of the write buffer is written into k backup storage cells.

[0011] Optionally, in any of the preceding aspects, another implementation of the aspect provides that each bit of the write buffer is written into a backup storage cell on a separate one of k SLC storage devices.

[0012] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the reduced Ep programming write pulses comprise at least one of a pulse time shorter than the standard write pulse and a voltage less than the standard write pulse.

[0013] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the bits of the write buffer written into the backup storage cells include Low Density Parity Check (LDPC) ECC bits.

3

SUBSTITUTE SHEET (RULE 26) [0014] Optionally, in any of the preceding aspects, another implementation of the aspect provides that obtaining the list of backup storage cells comprises reading the list from memory of the controller.

[0015] Optionally, in any of the preceding aspects, another implementation of the aspect provides further comprising: restoring the write buffer when power is restored to the flash memory device, wherein restoring the write buffer comprises: reading data from the cells of the list of backup storage cells; performing error correction on each SLC memory page of the data; adding ECC bits to each Multiple-LC memory page of the data; and writing the data to the Multiple-LC pages of the flash memory device.

[0016] Optionally, in any of the preceding aspects, another implementation of the aspect provides further comprising: prior to performing error correction on each SLC memory page of the data, de-randomizing each SLC memory page of the data using a key generated from address information of the SLC memory page; and prior to writing the data to the Multiple-LC pages of the flash memory device, randomizing each Multiple-LC memory page of the data using a key generated from address information of the Multiple-LC memory page.

[0017] Optionally, in any of the preceding aspects, another implementation of the aspect provides further comprising: restoring the write buffer when power is restored to the flash memory device, wherein restoring the write buffer comprises: reading data from the cells of the list of backup storage cells; performing error correction on each SLC memory page of the data; de-randomizing each SLC memory page of the data using a key generated from address information of the SLC memory page; randomizing each Multiple-LC memory page of the data using a key generated from address information of the Multiple-LC memory page; adding ECC

4

SUBSTITUTE SHEET (RULE 26) bits to each Multiple-LC memory page of the data; and writing the data to the Multiple-LC pages of the flash memory device.

[0018] Optionally, in any of the preceding aspects, another implementation of the aspect provides that reading data from the cells of the list of backup storage cells to generate a restored write buffer comprises: obtaining the copies factor (k), where k is an odd number representing a number of copies of the write buffer stored in the backup storage cells; and reading cell values of k backup storage cells and performing majority voting on the cell values of the k backup storage cells to determine a value for each bit of the restored write buffer.

[0019] Optionally, in any of the preceding aspects, another implementation of the aspect provides that obtaining the copies factor k comprises reading the copies factor k from memory of the controller.

[0020] Optionally, in any of the preceding aspects, another implementation of the aspect provides that one or more of the steps of performing error correction, adding ECC bits, derandomizing, and randomizing are performed in the peripheral circuit of the flash memory device. [0021] Optionally, in any of the preceding aspects, another implementation of the aspect provides that one or more of the steps of performing error correction, adding ECC bits, derandomizing, and randomizing are performed by one or more devices external to the flash memory device.

[0022] A third aspect relates to a backup storage cells selection method implemented by a controller of a flash memory device. The method includes obtaining a reduction factor (n) for programming energy (Ep); setting a programming power supply for a single-level cell (SLC) memory region to produce reduced Ep programming write pulses based on a value of 1/H; obtaining a desired size for the list of backup storage cells; obtaining a maximum number of cells in the SLC

5

SUBSTITUTE SHEET (RULE 26) memory region available for addition to the list of backup storage cells, where the desired number of cells is less than the maximum number of available cells; and implementing a loop in the method, the loop comprising: selecting a group of cells in the SLC memory region; writing a test pattern into the group of cells using the reduced Ep programming write pulses; reading data from the group of cells; performing error correction on the data read from the group of cells to determine whether the data is correct; adding the group of cells to the list of backup storage cells when the data is correct; storing the list of backup cells in a memory of the controller and terminating the loop successfully when a size of the list of backup storage cells is equal to the desired size for the list; and terminating the loop unsuccessfully when a number of cells equal to the maximum number of available cells have been tested and the size of the list of backup storage cells is less than the desired size for the list of backup storage cells.

[0023] Optionally, in any of the preceding aspects, another implementation of the aspect provides further comprising: storing the list of backup storage cells in memory of the controller after a predetermined number of times the flash memory device is powered up.

[0024] Optionally, in any of the preceding aspects, another implementation of the aspect provides that the group of cells is a page of cells.

[0025] Optionally, in any of the preceding aspects, another implementation of the aspect provides that error correction performed on the data read from the group of cells is LDPC error correction.

[0026] A fourth aspect relates to a backup storage cells selection method implemented by a controller of a flash memory device. The method comprises obtaining a reduction factor («) for programming energy (Ep); obtaining an initial value for a test copies factor ktest), where ktest is an odd number representing a number of copies of a test pattern to be stored to determine the backup

6

SUBSTITUTE SHEET (RULE 26) storage cells; obtaining a value for K _max , where K _max is a maximum allowable value for ktest, and implementing a loop in the method, the loop comprising: setting a programming power supply for a single-level cell (SLC) memory region to produce reduced Ep programming write pulses based on a value of l/(n*fe _s ?); writing the test pattern into a group of cells in the SLC memory region using the reduced Ep programming write pulses, where the group of cells has a size equal to ktest times a number of bits in a write buffer and each bit of the test pattern is written into each of k separate subgroups of the cells of the group of cells; generating a restored test pattern, where each bit of the restored test pattern comprises a majority voting result performed on cell values read from the ktest subgroups of cells of the group of cells; performing error correction on the restored test pattern to determine whether the restored test pattern is correct; when the restored test pattern is correct: storing the group of cells in a memory of the controller as the list of backup storage cells; storing the value of ktest in the memory of the controller as the copies factor (k), and terminating the loop successfully; and when the restored test pattern is not correct: incrementing the value of ktest by 2; and terminating the loop unsuccessfully when the incremented value of ktest is greater than K _max .

[0027] Optionally, in any of the preceding aspects, another implementation of the aspect provides that each of the k separate subgroups of the cells of the group of cells is located in a separate SLC memory device.

[0028] Optionally, in any of the preceding aspects, another implementation of the aspect provides further comprising: performing the backup storage cells selection method after the flash memory device is powered up a predetermined number of times.

7

SUBSTITUTE SHEET (RULE 26) [0029] Optionally, in any of the preceding aspects, another implementation of the aspect provides that error correction performed on the data read from the group of cells is Low Density Parity Check (LDPC) error correction.

[0030] For the purpose of clarity, any one of the foregoing embodiments may be combined with any one or more of the other foregoing embodiments to create a new embodiment within the scope of the present disclosure.

[0031] These and other features, and the advantages thereof, will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] For a more complete understanding of this disclosure, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts.

[0033] FIG. 1 is a schematic diagram of a flash memory SSD according to an embodiment of the present disclosure.

[0034] FIG. 2 is a schematic diagram of the NAND flash array of the SSD of FIG. 1.

[0035] FIG. 3 is a schematic diagram of one of the NAND flash devices of FIG. 2.

[0036] FIG. 4A is a first method for power loss backup of a write buffer according to an embodiment of the present disclosure.

[0037] FIG. 4B is a second method for power loss backup of a write buffer according to an embodiment of the present disclosure.

[0038] FIG. 5A is a first method for restoring the write buffer and writing the write buffer to flash memory on power up according to an embodiment of the present disclosure.

8

SUBSTITUTE SHEET (RULE 26) [0039] FIG. 5B is a second method for restoring the write buffer and writing the write buffer to flash memory on power up according to an embodiment of the present disclosure.

[0040] FIG. 6 is a first method of selecting SLC cells according to an embodiment of the present disclosure.

[0041] FIG. 7 is a second method of selecting SLC cells according to an embodiment of the present disclosure.

[0042] FIG. 8 is a schematic diagram illustrating a processor device according to an embodiment of the present disclosure.

[0043] FIG. 9 illustrates an apparatus configured to implement one or more of the methods for storing a write buffer of a flash memory device to SLC flash memory during a power loss event as described herein.

DETAILED DESCRIPTION

[0044] It should be understood at the outset that, although illustrative implementations of one or more embodiments are provided below, the disclosed systems and/or methods may be implemented using any number of techniques, whether currently known or in existence. The disclosure should in no way be limited to the illustrative implementations, drawings, and techniques illustrated below, including the exemplary designs and implementations illustrated and described herein, but may be modified within the scope of the appended claims along with their full scope of equivalents.

[0045] A flash memory device according to the disclosure stores its write buffer to single-level cell (SLC) flash memory during a power loss event. Such a device is able to save a larger write buffer, first, by storing the write buffer to SLC flash memory (which requires a lower programming energy and a quicker programming cycle than multi-level flash memory) and, second, by

9

SUBSTITUTE SHEET (RULE 26) preselecting SLC cells that can be written to at a preselected reduced programming energy while maintaining a bit error rate that can be corrected by error correction codes already present in the data stored in the write buffer. When power is next applied to the flash memory device, the data stored to the SLC cells can be reliably read to generate a restored write buffer that can be written to its original destinations in multi-level flash memory of the flash memory device.

[0046] FIG. 1 is a schematic diagram of a flash memory SSD 100 according to an embodiment of the present disclosure. While the SSD 100 comprises NAND flash memory, in other embodiments a device according to the disclosure may include NOR flash memory. The SSD 100 includes a main central processing unit (CPU) 102 and a NAND Flash Interface (NFI) CPU 108. The main CPU 102 includes a front-end CPU 104 and a back-end CPU 106. The front-end CPU 104 implements a handler for commands received from a host device 130 via a PCIe bus (Peripheral Component Interconnect Express), SAS bus (Serial Attached SCSI (Small Computer System Interface)), or other suitable interface. The front-end CPU 104 also implements a scheduler for Back End (BE) commands issued in response to received host commands. The back- end CPU 106 implements back end firmware (FW), performs Flash Translation Layer (FTL), mapping, and other back-end functions.

[0047] The NFI CPU 108 controls and manages channels 122. Each channel 122 communicates data and commands to a subset of NAND flash devices in a NAND flash array 150 (which is described in greater detail with reference to FIG. 2). In other SSDs, the main CPU 102 and/or NFI CPU 108 may be implemented with other numbers or types of CPUs and/or other distributions of functionality.

[0048] The SSD 100 further includes Dynamic Random Access Memory (DRAM) 112, Static Random Access Memory (SRAM) 114, Hardware (HW) Accelerators 116, and Other

10

SUBSTITUTE SHEET (RULE 26) Peripherals 118. The DRAM 112 is 32 Gigabytes (GB) in size, but may be larger or smaller in other SSDs. The SRAM 114 is 10 Megabytes (MB), but may be larger or smaller in other SSDs. [0049] The HW Accelerators 116 include an Exclusive-OR (XOR) engine, a buffer manager, a HW Garbage Collection (GC) engine, and may include other HW circuits designed to independently handle specific, limited functions for the main CPU 102 and the NFI CPU 108. The Other Peripherals 118 may include circuits such as a Serial Peripheral Interface (SPI) circuit, a General Purpose Input/Output (GPIO) circuit, an Inter-Integrated Circuit (I2C) bus interface, a Universal Asynchronous Receiver/Transmitter (UART) circuit, and other interface circuits.

[0050] The SSD 100 further includes flash subsystems 120, which may include a Low Density Parity Check (LDPC) or other error correction circuit, a randomizer circuit, a flash signal processing circuit, and may include other circuits that provide processing relating to writing and reading data to the NAND flash array 150. The main CPU 102, the NFI CPU 108, the DRAM 112, the SRAM 114, the HW Accelerators 116, the Other Peripherals 118, and the flash sub-systems 120 comprise a SSD controller 140 and are communicatively coupled to the host device 130 by an Interconnect Network (or bus) 110.

[0051] In embodiments according to the disclosure that comprises NOR flash memory, the SSD controller 140 may have a different complement of subsystems that provide control of the NOR flash devices and communication with the host device 130.

[0052] FIG. 2 is a schematic diagram of the NAND flash array 150 of the SSD 100 of FIG. 1. Each channel 122 communicates data and commands from the flash subsystems 120 to a subset of NAND flash devices 252 of the NAND flash array 150. Within each subset are sixteen NAND flash devices 252 (which may more generally be referred to as a flash memory device). Each NAND flash device 252 is coupled to a channel 122 and no NAND flash device 252 is coupled to

11

SUBSTITUTE SHEET (RULE 26) more than one channel 122. In other SSDs, fewer channels or more channels may be used. Similarly, in other SSDs, fewer or more NANO flash devices per channel may be provided.

[0053] As will be described in more detail with reference to FIG. 3, each NANO flash device 252 includes a multiple-level cell (Multiple-LC) flash memory 258, a single-level cell (Single-LC or SLC) flash memory 256, and peripheral circuitry that includes SRAM 254. Data to be written to the Multiple-LC flash memory 258 and/or the SLC flash memory 256 is written into the SRAM 254 via the channel 122. Control signals received by the NAND flash device 252 via the channel 122 cause the peripheral circuitry of the NAND flash device 252 to write the data from the SRAM 254 to its designated flash memory 256 or 258. When the SSD 100 experiences a power loss event, peripheral circuitry of the NAND flash device 252 receives a signal indicating such an event via the channel 122.

[0054] FIG. 3 is a schematic diagram of one of the flash memory devices of FIG. 2. As mentioned with reference to the SSD 100, while the flash memory device 252 is a NAND flash device, in other embodiments a flash memory device according to the disclosure may utilize NOR flash memory. The flash memory device 252 includes the Multiple-LC flash memory 258 and the SLC flash memory 256. The cells of the SLC flash memory 256 may also be referred to as “SLC cells.” The Multiple-LC flash memory 258 may comprise one or more of multi-level cell (MLC) memory that stores two bits of data per cell, triple level cell (TLC) memory that stores three bits of data per cell, quad level cell (QLC) memory that stores four bits of data per cell, or penta-level cell (PLC) memory that stores five bits of data per cell. Flash memory storing more than five bits of data per cell may be used in other embodiments according to the disclosure.

[0055] The flash memory device 252 further includes peripheral circuitry 310 that comprises a controller 302, the SRAM 254, and an Ep (programming energy) control circuit 308. A data

12

SUBSTITUTE SHEET (RULE 26) bus 304 and a control bus 306 interconnect the controller 302, the SRAM 254, the Multiple-LC flash memory 258, and the SLC flash memory 256. While the flash memory device 252 includes only a single data bus 304 and a single control bus 306, other flash devices according to the disclosure may utilize two or more data and/or control buses. The controller 302 is coupled to the flash subsystems 120 and other external devices by the channel 122.

[0056] The controller 302 is further coupled to and controls the Ep control circuit 308. The Ep control circuit 308 provides a selected programming write pulse to write data into the SLC flash memory 256. In normal powered operation, the programming write pulse has a standard pulse length and voltage that are selected by a designer of the flash memory device 252 to provide no more than a maximum bit error rate (BER) for data stored in the cells of the SLC flash memory 256. The standard pulse length and voltage provide what may be referred to as a standard Ep.

[0057] In embodiments according to the disclosure, the Ep control circuit 308, under control of the controller 302, provides a reduced Ep write pulse during power loss backup of the write buffer from the SRAM 254 to the SLC flash memory 256. The reduced Ep write pulse has an energy that is reduced relative to the energy of the standard Ep based on a reduction factor n. As will be described in more detail with reference to FIG. 6 and FIG. 7, in some embodiments the energy of the reduced Ep write pulse is \!n times the standard Ep, while in other embodiments the reduced Ep write pulse is l/(w*^) times the standard Ep (where k is a number of copies of the write buffer that are stored into the SLC flash memory 256).

[0058] The energy of the reduced Ep write pulse may be reduced by emitting a pulse that is shorter than the standard pulse length, has a voltage that is lower than the standard pulse voltage,

13

SUBSTITUTE SHEET (RULE 26) or that is both shorter and lower voltage than the standard pulse voltage. The value of the reduction factor n is selected by a designer of the SSD 100 and may be based on criteria that include, but are not limited to, an amount of energy stored in capacitors that provide power to the SSD 100 during a power loss event, a desired write buffer size in the flash memory devices 252 of the SSD 100, and a BER-to-Ep ratio of the SLC flash memories 256 of the flash memory devices 252 of the SSD 100.

[0059] Data stored to flash memory may be randomized for any or all of the following reasons: to improve reliability of the flash memory cells, to reduce memory cell noise, and to reduce bus noise during memory cell writes and reads. Each page of data is typically randomized using a key generated from an address of the page in memory. A page of flash memory cells is a group of flash memory cells (typically, the smallest group) that are written in a single write operation.

[0060] Data written to flash memory may also have error-correcting code (ECC) bits added to it, to enable errors in flash memory storage of the data to be detected and/or corrected (a process referred to as “performing error correction”). ECC bits are also typically added separately to each page of data.

[0061] In various embodiments of the disclosure, prior to writing a page of data to flash memory, randomization may be performed on the page before adding ECC bits, or ECC bits may be added to the page first and then the page data randomized. When the page of data is later read from flash memory, the steps of de-randomizing and performing error correction are performed in the inverse order appropriate to the order they were applied to the page before it was written to flash memory.

[0062] Write buffer data has typically already had randomization performed and ECC bits added before it is stored in the write buffer for subsequent programming into intended pages of the

14

SUBSTITUTE SHEET (RULE 26) Multiple-LC flash memory 258. As will be discussed in more detail with reference to FIGS. 4A- 4C and 5A-5C, such prior randomization and ECC bits may require additional steps in write buffer backup and restoration processes.

[0063] In some embodiments, in power loss backup methods of FIGS. 4A and 4B and write buffer restoration methods of FIGS. 5 A and 5B, steps of randomizing, de-randomizing, ECC correction, and ECC bit addition are performed by ECC and randomizer circuits in the peripheral circuits 310 of the flash memory device 252. In other embodiments, the controller 302 sends the write buffer and/or restored data to the flash subsystems 120 via the channel 122 for ECC and randomizer circuits in the flash subsystems 120 to perform the necessary steps and return the write buffer and/or restored data via the channel 122.

[0064] FIG. 4A is a first method 400 for power loss backup of a write buffer according to an embodiment of the present disclosure. The method 400 is initiated by the controller 302 upon sensing a power loss event or upon receiving a power loss event signal from the SSD controller 140. The power loss event interrupts the conventional writing of data from the write buffer into its intended locations in the Multiple-LC flash memory 258.

[0065] In step 402, the controller 302 obtains Ep reduction factors for the write buffer backup process. The Ep reduction factors include a reduction factor (//) and, in embodiments using a Majority Voting backup process (as described in more detail with reference to FIG. 7), the Ep reduction factors also include a copies factor k. In step 402, the controller 302 also obtains a list of backup cells in the SLC flash memory 256 in which to store the backup copy of the write buffer. The Ep reduction factors and the list of backup cells may be obtained from non-volatile memory of the controller 302, from the SSD controller 140 via the channel 122, or by another means. In embodiments using a Golden Cells backup process (as described in more detail with reference to

15

SUBSTITUTE SHEET (RULE 26) FIG. 6), the list of backup cells has a size equal to a size of the write buffer in the SRAM 254. In embodiments using the Majority Voting backup process, the list of backup cells has a size equal to k times the size of the write buffer.

[0066] In step 404, in embodiments using the Golden Cells backup process, the controller 302 sets the Ep control 308 to produce a reduced Ep write pulse of 1/n times the standard Ep. In embodiments using the Majority Voting backup process, the controller 302 sets the Ep control circuit 308 to produce a reduced Ep write pulse of l/(n*k) times the standard Ep.

[0067] In some embodiments, in step 406 the controller 302 randomizes each SLC memory page of the write buffer using a key generated from address information of the SLC memory page. In all embodiments, in step 408, the controller 302 writes each individual bit of the write buffer to a cell in the list of backup cells, in embodiments using the Golden Cells backup process. In embodiments using the Majority Voting backup process, the controller 302 writes each individual bit of the write buffer to k cells in the list of backup cells. Once all the bits of the write buffer have been written to cells in the list of backup cells, the method 400 is complete.

[0068] FIG. 4B is a second method 420 for power loss backup of a write buffer according to an embodiment of the present disclosure. In step 422, as described for step 402 of the method 400, the controller 302 obtains Ep reduction factors for the write buffer backup process, including a reduction factor (n) and, in embodiments using a Majority Voting backup process, a copies factor k. In step 422, the controller 302 also obtains a list of backup cells in the SLC flash memory 256. In embodiments using a Golden Cells backup process, the list of backup cells has a size equal to a size of the write buffer in the SRAM 254. In embodiments using the Majority Voting backup process, the list of backup cells has a size equal to k times the size of the write buffer.

16

SUBSTITUTE SHEET (RULE 26) [0069] In step 424, as described for step 404 of the method 400, in embodiments using the Golden Cells backup process, the controller 302 sets the Ep control 308 to produce a reduced Ep write pulse of 1/n times the standard Ep. In embodiments using the Majority Voting backup process, the controller 302 sets the Ep control circuit 308 to produce a reduced Ep write pulse of l/(n*k) times the standard Ep.

[0070] In step 426, the controller 302 derandomizes each Multiple-LC memory page of the write buffer using a key generated from address information of the Multiple-LC memory page. In step 428, the controller 302 randomizes each SLC memory page of the write buffer using a key generated from address information of the SLC memory page. In step 430, the controller 302 adds ECC bits to each SLC memory page of the write buffer. In step 432, the controller 302 writes each individual bit of the write buffer to a cell in the list of backup cells, in embodiments using the Golden Cells backup process. In embodiments using the Majority Voting backup process, the controller 302 writes each individual bit of the write buffer to k cells in the list of backup cells. Once all the bits of the write buffer have been written to cells in the list of backup cells, the method 420 is complete.

[0071] FIG. 5A is a first method 500 for restoring the write buffer and writing the write buffer to flash memory on power up according to an embodiment of the present disclosure. The method 500 is used to restore write buffer data that was stored using the method 400 of FIG. 4A.

[0072] In step 502, the controller 302 reads data (“read data”) from cells of the list of backup cells. In embodiments using the Majority Voting backup process, in step 502, the controller 302 also obtains the copies factor k and performs majority voting on the cell values of k cells of the list of backup cells to determine a value for each bit of the read data. The copies factor k may be

17

SUBSTITUTE SHEET (RULE 26) obtained from non-volatile memory of the controller 302, from the SSD controller 140 via the channel 122, or by another means.

[0073] In embodiments where step 406 of the method 400 was performed to randomize the write buffer data prior to being written into the list of backup cells, in step 504 the controller 302 de-randomizes each SLC memory page of the read data using a key generated from address information of the SLC memory page.

[0074] In all embodiments of the method 500, in step 506 the controller 302 performs error correction on each SLC memory page of the read data and, in step 508, the controller 302 adds ECC bits to each Multiple-LC memory page of the read data.

[0075] Further, in embodiments where step 406 of the method 400 was performed to randomize the write buffer data prior to being written into the list of backup cells, in step 510 the controller 302 randomizes each Multiple-LC memory page of the read data using a key generated from address information of the Multiple-LC memory page.

[0076] Finally, in all embodiments, in step 512 the controller 302 writes the read data (now restored write buffer data) to its originally intended locations in the Multiple-LC flash memory 258, completing the conventional write buffer writing process that was interrupted by the power loss event that caused the write buffer to be backed up to the SLC flash memory 256.

[0077] FIG. 5B is a second method 520 for restoring the write buffer and writing the write buffer to flash memory on power up according to an embodiment of the present disclosure. The method 520 is used to restore write buffer data that was stored using the method 420 of FIG. 4B.

[0078] In step 522, the controller 302 reads data (“read data”) from cells of the list of backup cells to create a restored buffer. As described for step 502 of the method 500, in embodiments using the Majority Voting backup process, the controller 302 also obtains the copies factor k and

18

SUBSTITUTE SHEET (RULE 26) performs majority voting on the cell values of k cells of the list of backup cells to determine a value for each bit of the read data.

[0079] In step 524, the controller 302 performs error correction on each SLC memory page of the read data. In step 526, the controller 302 de-randomizes each SLC memory page of the read data using a key generated from address information of the SLC memory. In step 528, the controller 302 randomizes each Multiple-LC memory page of the read data using a key generated from address information of the Multiple-LC memory page. In step 530, the controller 302 adds ECC bits to each Multiple-LC memory page of the read data.

[0080] In step 532, the controller 302 writes the read data (now restored write buffer data) to its originally intended locations in the Multiple-LC flash memory 258, completing the conventional write buffer writing process that was interrupted by the power loss event that caused the write buffer to be backed up to the SLC flash memory 256.

[0081] FIG. 6 is a first method 600 of selecting SLC cells according to an embodiment of the present disclosure. The method 600 chooses one or more groups of SLC cells that, together, have a size equal to the size of a write buffer to be backed up on capacitor power during a power loss event. The groups of SLC cells chosen by the method 600 are ones that can successfully be programmed using the reduced Ep write pulse of 1/n times the standard Ep (which may also be referred to as a ‘noisy SLC write energy’). The cells chosen by the method 600 are stored as a list of backup cells, and may be referred to as “Golden Cells” and the method 600 as a “Golden Cells selection” method. The controller then reserves the list of backup cells from use during normal, powered up operation so that they will be available to back up the SRAM write buffer during a power loss event.

19

SUBSTITUTE SHEET (RULE 26) [0082] In step 602, the controller 302 obtains a value for n, the Ep reduction factor. The value of n may be obtained from non-volatile memory of the controller 302, from the SSD controller 140 via the channel 122, or by another means. The controller 302 then sets the Ep control circuit 308 to produce the reduced Ep write pulse of 1/n times the standard Ep. In step 602, the controller 302 also obtains a size of the SRAM write buffer, as a target for the number of SLC cells to find, and sets a value for M _max , which represents a maximum amount of the SLC flash memory 256 that may be considered for use for storing write buffer backup in a power loss event. When the method 600 tests M _max number of SLC cells and has not found enough cells that store data successfully at the noisy SLC write energy to backup the SRAM write buffer, the method 600 terminates unsuccessfully.

[0083] In step 604, the controller 302 selects m, a candidate group of SLC cells from the SLC flash memory 256. In some embodiments, m is a single page of SLC cells. In other embodiments, m may be two or more pages, a partial page, or some other size group of SLC cells. Where m is two or more pages, the pages may not be contiguous to each other.

[0084] In step 606, the controller 302 stores a test pattern into m, using the noisy SLC write energy. The test pattern may be randomly created or may be a consistent pattern. In either case, it is a pattern that includes Error Correction Code (ECC) bits. In some embodiments, because the write buffer being backed up may include pages that have already had Low Density Parity Check (LDPC) ECC bits added, the test pattern will include LDPC ECC bits, in order to test the cells of m under the conditions that will be encountered during a write buffer backup process. Each bit of the test pattern is written to a separate cell of m.

[0085] In step 608, the controller 302 reads individual bit data from the cells of m, generates a read test pattern from the read bits, and performs LDPC ECC on the read test pattern. In step 610,

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SUBSTITUTE SHEET (RULE 26) the controller 302 determines from the ECC results whether the read test data is correct. When the read test data is correct, in step 612 the group m of SLC cells is added to the list of cells selected for use as backup cells for storage of the SRAM write buffer contents during a power loss event. The group m may be contiguous or discontiguous with other SLC cells of the list. In step 612, the controller 302 also removes the size of m from M _max or adds the size of m to a variable that accumulates the number of SLC cells that have been tested for inclusion in a list of cells selected for use as backup cells for storage of the SRAM write buffer contents during a power loss event.

[0086] In step 614, the number of cells in the list of cells selected for use as backup cells is compared to a size of the SRAM write buffer, to determine whether enough SLC cells have been tested to enable a complete backup of the SRAM write buffer. When enough SLC cells have been tested to enable a complete backup of the SRAM write buffer, the method 600 terminates successfully at step 616. The controller 302 stores the list of cells as a list of backup cells for subsequent use in a backup of the SRAM write buffer during a power loss event.

[0087] When enough SLC cells have not been tested (at step 614) or the read test data is not correct (at step 610), in step 618 the controller 302 determines whether the value for M _max has been reached. Consistent with step 612, the test may be whether the value of M _max has been decremented to zero or whether the variable accumulating the number of tested SLC cells has reached M _max . ^\\QnM _max has not been reached, the method 600 continues at step 604, selecting another group m of candidate SLC cells.

[0088] When M _max has been reached, in step 620, the list selection fails and the method 600 terminates unsuccessfully. Upon unsuccessful termination, the controller 302 signals the failure to the SSD controller 140. In some embodiments, the SSD controller 140 reduces the size of the

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SUBSTITUTE SHEET (RULE 26) write buffer in the SRAM 254 and/or decreases the value for n, the Ep reduction factor, to increase the possibility that another invocation of the method 600 will terminate successfully.

[0089] FIG. 7 is a second method 700 of selecting SLC cells according to an embodiment of the present disclosure. Where a large number of SLC backup cells is available, the designer may choose to write each bit of the write buffer to an odd-numbered plurality of SLC cells at an even further reduced noisy SLC write energy, then perform a majority voting process on the bits read from the plurality of SLC cells during a write buffer recovery process. The cells selected by the method 700 are stored as a list of backup cells, and may be referred to a “Majority Voting cells” and the method 700 as a “Majority Voting selection” method.

[0090] The choice of Majority Voting over Golden Cells may be a tradeoff by a designer of the flash memory device 252 between reduced Ep and BER. The use of Golden Cells may require a lower BER than Majority Voting. As such Majority Voting may be preferred in an embodiment where the technology of the SLC cells of the flash memory device 252 has a BER that is less sensitive to Ep reduction. In other embodiments, Majority Voting may be preferred to allow the controller 302 to write each of the k copies into a separate SLC memory device, to improve the chance of the write buffer backup surviving the failure of a complete SLC memory device.

[0091] In step 702, the controller 302 obtains a value for n, the Ep reduction factor. In step 702, the controller 302 also obtains an initial value for ktest, a candidate value for an odd number of copies of each write buffer bit that will be written to SLC cells during power loss backup. In step 702, the controller 302 further obtains a value for K _max , a maximum acceptable value for ktest- The values of n, ktest, and K _max may be obtained from non-volatile memory of the controller 302, from the SSD controller 140 via the channel 122, or by another means.

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SUBSTITUTE SHEET (RULE 26) [0092] In step 704, the controller 302 selects a candidate group of SLC cells from the SLC flash memory 256, where the candidate group has a size equal to ktest times a size of the write buffer in the SRAM 254. In some embodiments, the candidate group is a contiguous group of pages of SLC cells. In other embodiments, the candidate group is a discontiguous group of pages of SLC cells. In still other embodiments, the candidate group includes partial pages of SLC cells.

[0093] In step 706, the controller 302 sets the Ep control circuit 308 to produce a reduced Ep write pulse of l(n*kt _es i) times the standard Ep (which, may also be referred to as a “Majority Voting noisy SLC write energy”). The controller 302 then stores a test pattern into the candidate group, using the Majority Voting noisy SLC write energy. The test pattern may be randomly created or may be a consistent pattern. In either case, it is a pattern that includes Error Correction Code (ECC) bits. In some embodiments, because the write buffer being backed up may include pages that have already had Low Density Parity Check (LDPC) ECC bits added, the test pattern will include LDPC ECC bits, in order to test the cells of the candidate group under the conditions that will be encountered during a write buffer backup process. Each bit of the test pattern is written to each of ktest separate subgroups of the cells of the candidate group.

[0094] In step 708, the controller 302 reads individual bit data from the ktest subgroups of cells and generates read test data from the read bits using majority voting. Since the value of ktest is an odd number, even when some of the bits of read data for a subgroup have a value different from other bits of read data, there will always be more bits (or a majority of bits) in the subgroup of read data with one value than with the other. This majority value is the value assigned to the associated bit of the read test data.

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SUBSTITUTE SHEET (RULE 26) [0095] In step 710, the controller 302 performs LDPC ECC on the read test data and, in step 712, determines from the ECC results whether the read test data is correct. When the read test data is correct, in step 714 the method 700 terminates successfully. The controller 302 stores the successful final value of ktest as a copies factor k and stores the candidate group as the list of backup cells, for subsequent use in Majority Voting backup of the SRAM write buffer during a power loss event.

[0096] When it is determined in step 712 that the read test data is not correct, the method 700 continues with step 716, where the controller 302 increments the value of ktest by 2 (so that ktest remains an odd number). In step 718, the controller 302 determines whether the new value of ktest exceeds the limit value of K _max . When ktest does not exceed K _max , the method 700 loops back to step 704 to test a larger candidate group of SLC cells.

[0097] When ktest does exceed K _max , in step 720 the method 700 terminates unsuccessfully. Upon unsuccessful termination, the controller 302 signals the failure to the SSD controller 140. In some embodiments, the SSD controller 140 reduces the size of the write buffer in the SRAM 254 and/or decreases the value for M, the Ep reduction factor, to increase the possibility that another invocation of the method 700 will terminate successfully.

[0098] Programming characteristics of the SLC cells of the SLC flash memory 256 can change over time and with use. Based on this characteristic of the SLC cells, the designer of the flash memory device 252 may choose to perform the method 600 or 700 only once (upon the initial power up of the flash memory device 252 after fabrication), after a predetermined number of times the flash memory device 252 is powered up, or every time the flash memory device 252 is powered up.

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SUBSTITUTE SHEET (RULE 26) [0099] The methods 600 and 700 are performed separately by the controller 302 of each NAND flash device 252. In some embodiments, by designer choice, the controller 302 may implement only one of the methods 600 or 700. Such a choice may be made, for example, as a tradeoff between the amount of SLC cell space available and the amount of energy available for the write buffer backup process. In other embodiments, the controller 302 may implement both of the methods 600 and 700, with the method that is used selected by the SSD controller 140 using a signal sent via the channel 122. In such embodiments, a tradeoff between available SLC cell space, available backup energy, write buffer size, and flash memory size (or number of flash memory devices) may be made as part of the design of SSD 100, and the designer configure each flash memory device to use one or the other of the methods 600 and 700. In other embodiments, the designer may use Golden Cell backup for one portion of the write buffer and Majority Voting backup for the remainder of the write buffer.

[00100] FIG. 8 is a schematic diagram illustrating a processor device 800 according to an embodiment of the present disclosure. The processor device 800 is suitable for implementing the disclosed embodiments as described herein. The processor device 800 comprises a processor, logic unit, or other suitable processing circuit 830 to process data; a bus transceiver (XCVR) 840 and bus port 850 for sending and receiving the data via a bus such as the channel 122; and a memory 860 for storing the data. The processor device 800 is suitable for implementing the functions described herein performed by the controller 302.

[00101] The processor 830 is implemented by hardware and software. The processor 830 may be implemented as one or more CPU chips, cores (e.g., as a multi-core processor), field- programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and digital signal processors (DSPs). The processor 830 is in communication with bus transceiver 840, bus

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SUBSTITUTE SHEET (RULE 26) port 850, and memory 860. The processor 830 comprises a power loss backup module (PLBM) 870, The PLBM 870 implements the disclosed embodiments described above. For instance, the PLBM 870 can include instructions for implementing the power loss backup and restoration methods described in FIGS. 4-7. The inclusion of the SSD control module 870 therefore provides a substantial improvement to the functionality of the processor device 800 and effects a transformation of the processor device 800 to a different state. For example, the inclusion of the PLBM 870 improves the functionality of the processor device 800 by enabling a flash memory device according to the disclosure to reliably store its full write buffer to flash memory during a power loss event.

[00102] The memory 860 may be used as an over-flow data storage device, to store programs when such programs are selected for execution, and to store instructions and data that are read during program execution. The memory 860 may be volatile and/or non-volatile and may be readonly memory (ROM), random-access memory (RAM), ternary content-addressable memory (TCAM), and static random-access memory (SRAM).

[00103] FIG. 9 illustrates an apparatus 900 configured to implement one or more of the methods for storing a write buffer of a flash memory device to SLC flash memory during a power loss event as described herein. For example, the apparatus 900 is configured to implement the methods 400, 420, 500, 520, 600, and 700 of FIGS. 4A-4B, 5A-5B, 6, and 7, respectively. The apparatus 900 may be implemented in the processor device 800. The apparatus 900 comprises means 902 for performing power loss backup of a write buffer, as described with reference to the method 400; means 904 for restoring the write buffer and writing the write buffer to flash memory on power up, as described with reference to the method 500; means 906 for choosing Golden Cells to be written to during a power loss event, as described with reference to the method 600; and means

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SUBSTITUTE SHEET (RULE 26) 908 for choosing Majority Voting cells to be written to during a power loss event, as described with reference to the method 700.

[00104] While several embodiments have been provided in the present disclosure, it may be understood that the disclosed systems and methods might be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The present examples are to be considered as illustrative and not restrictive, and the disclosure is not to be limited to the details given herein. For example, the various elements or components may be combined or integrated in another system or certain features may be omitted, or not implemented.

[00105] In addition, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods without departing from the scope of the present disclosure. Other items shown or discussed as coupled or directly coupled or communicating with each other may be indirectly coupled or communicating through some interface, device, or intermediate component whether electrically, mechanically, or otherwise. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and may be made without departing from the spirit and scope disclosed herein.

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SUBSTITUTE SHEET (RULE 26)