Title:
LOW-LEAKAGE MEMORY ARRAY
Document Type and Number:
WIPO Patent Application WO/2021/212393
Kind Code:
A1
Abstract:
A low-leakage memory array (310). The memory array (310) comprises: a read bit line (RBL), a read bit line switch (M0) connecting the ground (VSS) and the read bit line (RBL), and a plurality of memory circuits, wherein each memory circuit comprises a memory cell (420) for storing data, and a read circuit (410) for reading the data in the memory cell (420). A data input end of the read circuit (410) is connected to a data output end of the memory cell (420) to read data in the memory circuits, and a data output end of the read circuit (410) is connected to the read bit line (RBL) to output the read data to the read bit line (RBL). At least one PMOS transistor is provided in a leakage path, which is from a power supply (VDD) to the read bit line (RBL), in the read circuit (410) in order to suppress a leakage current in the read circuit (410) and reduce data reading errors caused by leakage of the memory array (310).
Inventors:
CAI JIANGZHENG (CN)
BU MINGEN (CN)
JIN YUZHENG (CN)
ZHANG YUQING (CN)
BU MINGEN (CN)
JIN YUZHENG (CN)
ZHANG YUQING (CN)
Application Number:
PCT/CN2020/086280
Publication Date:
October 28, 2021
Filing Date:
April 23, 2020
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
G11C11/413; G11C11/417; G11C11/419
Foreign References:
| CN103700395A | 2014-04-02 | |||
| US5420813A | 1995-05-30 | |||
| CN109887535A | 2019-06-14 | |||
| CN106328190A | 2017-01-11 | |||
| CN103531229A | 2014-01-22 | |||
| CN109935260A | 2019-06-25 |
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