MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE

Title:

MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE

Document Type and Number:

WIPO Patent Application WO/2022/160629

Kind Code:

A1

Abstract:

Provided in embodiments of the present application are a method for manufacturing a semiconductor structure and the semiconductor structure. The manufacturing method comprises: providing a substrate, which is provided with a peripheral area and an array area; forming an insulating layer on the substrate; forming a first mask layer having a first mask pattern on the insulating layer; etching the insulating layer with the first mask layer serving as a mask to form a contact hole running through the insulating layer in the array area; forming a first electrode layer, which at least covers the surface of the first mask layer and the surface of the contact hole of the array area; forming a second mask layer having a second mask pattern, the second mask layer being arranged on the first electrode layer, and the graphics of the first mask pattern and the graphics of the second mask pattern being complementary to each other; etching the first electrode layer and the first mask layer with the second mask layer serving as a mask until the insulating layer of the array area is exposed, the remaining first electrode layer serving as a lower electrode layer. The embodiments of the present application favor an increase in the electrical properties of the semiconductor structure.

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Inventors:

XIA JUN (CN)
WAN QIANG (CN)
XU PENGHUI (CN)
LI SEN (CN)
ZHAN KANGSHU (CN)
LIU TAO (CN)

Application Number:

PCT/CN2021/108761

Publication Date:

August 04, 2022

Filing Date:

July 27, 2021

Export Citation:

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Assignee:

CHANGXIN MEMORY TECH INC (CN)

International Classes:

H01L27/108; H01L21/8242

Foreign References:

US20020127854A1	2002-09-12
CN102339797A	2012-02-01
US20070063247A1	2007-03-22

Attorney, Agent or Firm:

CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)

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