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Title:
MEMORY CELL ARRAY UNIT
Document Type and Number:
WIPO Patent Application WO/2022/085470
Kind Code:
A1
Abstract:
This memory cell array unit according to one embodiment comprises a micro-controller which, on the basis of read/write control from a memory controller, performs reading/writing on a memory cell array by using n-bit allocated memory cells. When the micro-controller has discovered a defect in one of the n-bit allocated memory cells, the micro-controller writes write data of n-1 bits, such data excluding data of the least significant bit among the n-bit write data, to n-1 bit allocated memory cells, such memory cells excluding the defective allocated memory cell among the n-bit allocated memory cells.

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Inventors:
SAKAI LUI (JP)
KANDA YASUO (JP)
Application Number:
PCT/JP2021/037180
Publication Date:
April 28, 2022
Filing Date:
October 07, 2021
Export Citation:
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Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L45/00; G06F11/10; G11C29/00; H01L21/8239; H01L27/105; H01L49/00
Foreign References:
US7230600B12007-06-12
JP2001351398A2001-12-21
JP2019168749A2019-10-03
JP2017033170A2017-02-09
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
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