MEMORY DEVICE WITH A DATA HOLD LATCH - FREESCALE SEMICONDUCTOR INC

Title:

MEMORY DEVICE WITH A DATA HOLD LATCH

Document Type and Number:

WIPO Patent Application WO2006001910

Kind Code:

A3

Abstract:

A memory device includes a plurality of pairs of complimentary bit lines (200, 202) and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells (31, 37). Each latch circuit has an input coupled to a data line and a first output and a second output to provide complementary latched values dependent upon a value of the data line. For each latch of the plurality of latches, the first output is coupled to a first bit line of a pair of the plurality such that a value of the first bit line is continuously determined by the first output during memory device operation and the second output is coupled to a second bit line of the pair such that a value of the second bit line is continuously determined by the second output during memory device operation.

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Inventors:

RAMARAJU RAVINDRARAJ (US)
HOEKSTRA GEORGE P (US)
KENKARE PRASHANT U (US)

Application Number:

PCT/US2005/015858

Publication Date:

September 14, 2006

Filing Date:

May 05, 2005

Export Citation:

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Assignee:

FREESCALE SEMICONDUCTOR INC (US)
RAMARAJU RAVINDRARAJ (US)
HOEKSTRA GEORGE P (US)
KENKARE PRASHANT U (US)

International Classes:

E06C7/10; G11C7/00; G11C7/10

Foreign References:

US6859400B2	2005-02-22
US6470467B2	2002-10-22
US5517461A	1996-05-14

Other References: