Title:
MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME
Document Type and Number:
WIPO Patent Application WO/2023/028847
Kind Code:
A1
Abstract:
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells, and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with a plurality of sides of the semiconductor body. One end of the semiconductor body coupled to the storage unit is flush with the gate structure. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the bonding interface.
Inventors:
ZHU HONGBIN (CN)
LIU WEI (CN)
WANG YANHONG (CN)
LIU WEI (CN)
WANG YANHONG (CN)
Application Number:
PCT/CN2021/115704
Publication Date:
March 09, 2023
Filing Date:
August 31, 2021
Export Citation:
Assignee:
YANGTZE MEMORY TECH CO LTD (CN)
International Classes:
H01L27/108; H01L21/8242
Foreign References:
| US20180061835A1 | 2018-03-01 | |||
| US20180061834A1 | 2018-03-01 | |||
| CN109411473A | 2019-03-01 | |||
| CN110192269A | 2019-08-30 | |||
| US20210028174A1 | 2021-01-28 | |||
| US20050280061A1 | 2005-12-22 |
Attorney, Agent or Firm:
NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD. (CN)
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