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Patent Searching and Data


Title:
MEMORY HAVING VARIABLE REFRESH CONTROL AND METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO2004075257
Kind Code:
A3
Abstract:
A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit (16) controls refresh operations. The refresh counter (22) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit (16) to control a refresh rate of the memory array (12). A programmable fuse circuit (26) is provided to program the refresh rate using the counter (22). The programmable fuse circuit (26) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit (24) may be included to facilitate testing.

Inventors:
PELLEY PERRY H (US)
BURGAN JOHN M (US)
Application Number:
PCT/US2004/003494
Publication Date:
January 13, 2005
Filing Date:
February 06, 2004
Export Citation:
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Assignee:
FREESCALE SEMICONDUCTOR INC (US)
PELLEY PERRY H (US)
BURGAN JOHN M (US)
International Classes:
G11C7/10; G11C8/18; G11C11/406; G11C29/00; G11C29/02; (IPC1-7): G11C7/00
Foreign References:
US5475646A1995-12-12
US5619468A1997-04-08
US5933381A1999-08-03
US6426909B12002-07-30
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