Title:
METHOD AND APPARATUS FOR DETECTING AND CORRECTING ERRORS IN A PARALLEL TO SERIAL CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2010/088016
Kind Code:
A3
Abstract:
A circuit (301 ) has first portion (302) that receives data at a first rate; a second portion (305) that outputs data at a second rate synchronized to and different from the first rate; a third portion (350) that transfers data from the first portion (302) to the second portion (305); and a fourth portion (361 ) that generates an error detected signal in response to a disruption in the synchronism between the first and second rates. A different aspect involves a method that includes: receiving data at a first rate in a first portion (302); transferring data from the first portion (302) to a second portion (305); outputting data at a second rate from the second portion (305), the second rate being synchronized to and different from the first rate; and generating an error detected signal in response to detection of a disruption in the synchronism between the first and second rates.
Inventors:
PATRA MADEN M (US)
SASAKI PAUL T (US)
SASAKI PAUL T (US)
Application Number:
PCT/US2010/020560
Publication Date:
March 10, 2011
Filing Date:
January 08, 2010
Export Citation:
Assignee:
XILINX INC (US)
International Classes:
H03K5/19; H03L7/095; H03M9/00; G01R31/317; G06F11/07
Domestic Patent References:
| WO2004038994A1 | 2004-05-06 |
Foreign References:
| EP1249936A2 | 2002-10-16 | |||
| JPH10322200A | 1998-12-04 | |||
| US7091890B1 | 2006-08-15 |
Attorney, Agent or Firm:
LIU, Justin et al. (Inc.2100 Logic Driv, San Jose CA, US)
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