METHOD AND APPARATUS FOR DETERMINING FAILED-BIT REPAIR SCHEME

WIPO Patent Application WO/2022/037197

A1

Provided are a method and apparatus for determining a failed-bit repair scheme, which relate to the technical field of integrated circuits and which can be applied to a scenario of repairing a failed bit in a chip. The method for determining the failed-bit repair scheme comprises: determining an area to be repaired of a chip to be repaired; the area to be repaired comprises a plurality of target repair areas (S110); using a backup circuit to perform initial repair processing on the failed bits in each target repair area; a backup circuit comprises a backup word line and a bit line (S120); if the number of remaining spare word lines is greater than zero and the number of remaining spare bit lines is greater than zero, then determining a candidate repair sub-scheme for each target repair area, and determining a candidate repair cost corresponding to each candidate repair sub-scheme (S140); according to each candidate repair sub-scheme and candidate repair cost, determining a target repair scheme of the area to be repaired; the comprehensive repair cost corresponding to the target repair scheme is the smallest (S150). The present method can be used in limited RWL and RBL situations to determine the best dispatch solution.

CHEN YUI-LANG (CN)

PCT/CN2021/099146

February 24, 2022

June 09, 2021

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CHANGXIN MEMORY TECH INC (CN)

G11C29/44

CN110797072A	2020-02-14
CN1366308A	2002-08-28
CN109753374A	2019-05-14
CN101329918A	2008-12-24
US20060098503A1	2006-05-11

BEIJING INTELLEGAL INTELLECTUAL PROPERTY AGENT LTD. (CN)

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