Title:
METHOD AND APPARATUS FOR SCHEDULING OF INSTRUCTIONS IN A MULTISTRAND OUT-OF-ORDER PROCESSOR
Document Type and Number:
WIPO Patent Application WO/2013/006566
Kind Code:
A3
Abstract:
In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for scheduling instructions in a multi-strand out-of-order processor. For example, an apparatus for scheduling instructions in a multi-strand out-of-order processor includes an out-of-order instruction fetch unit to retrieve a plurality of interdependent instructions for execution from a multi-strand representation of a sequential program listing; an instruction scheduling unit to schedule the execution of the plurality of interdependent instructions based at least in part on operand synchronization bits encoded within each of the plurality of interdependent instructions; and a plurality of execution units to execute at least a subset of the plurality of interdependent instructions in parallel.
Inventors:
BABAYAN BORIS A (RU)
PENTKOVSKI VLADIMIR M (US)
BUTUZOV ALEXANDER V (RU)
SHISHLOV SERGEY Y (RU)
SIVTSOV ALEXEY Y (RU)
KOSAREV NIKOLAY E (RU)
PENTKOVSKI VLADIMIR M (US)
BUTUZOV ALEXANDER V (RU)
SHISHLOV SERGEY Y (RU)
SIVTSOV ALEXEY Y (RU)
KOSAREV NIKOLAY E (RU)
Application Number:
PCT/US2012/045286
Publication Date:
March 07, 2013
Filing Date:
July 02, 2012
Export Citation:
Assignee:
INTEL CORP (US)
BABAYAN BORIS A (RU)
PENTKOVSKI VLADIMIR M (US)
BUTUZOV ALEXANDER V (RU)
SHISHLOV SERGEY Y (RU)
SIVTSOV ALEXEY Y (RU)
KOSAREV NIKOLAY E (RU)
BABAYAN BORIS A (RU)
PENTKOVSKI VLADIMIR M (US)
BUTUZOV ALEXANDER V (RU)
SHISHLOV SERGEY Y (RU)
SIVTSOV ALEXEY Y (RU)
KOSAREV NIKOLAY E (RU)
International Classes:
G06F9/46; G06F9/30; G06F9/38
Foreign References:
| US20100274972A1 | 2010-10-28 | |||
| US20040162972A1 | 2004-08-19 | |||
| US20090217020A1 | 2009-08-27 | |||
| US7080234B2 | 2006-07-18 |
Attorney, Agent or Firm:
VINCENT, Lester J. et al. (1279 Oakmead ParkwaySunnyvale, California, US)
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