LOWER SUPPLY VOLTAGES

TECHNICAL FIELD

[0001] The disclosure generally relates to a mixed signal integrated circuit (IC) chip having an analog circuitry portion and a digital circuitry portion.

BACKGROUND

[0002] An integrated circuit (IC) chip generally incorporates one or more pins to receive input voltages for powering the IC chip.

SUMMARY

[0003] In one aspect, some implementations provide a mixed-signal integrated circuit that includes: one or more pins to receive an input voltage; a digital circuitry portion including transistors configured to be driven by the input voltage; and an analog circuitry portion including analog components configured to be driven by a regulated boosted voltage that is higher than the input voltage, the analog circuitry portion comprising a voltage booster that includes: one or more charge pump devices configured to receive the input voltage, an oscillator signal, and a control signal, wherein the one or more charge pump devices comprise a network of capacitors switchable to provide a charged pumped in response to the control signal, and wherein the one or more charge pump devices, using the charged pumped, generate a boosted voltage based on the input voltage and at least a portion of an amplitude of the oscillator signal, a voltage regulator coupled to the one or more charge pump devices and configured to receive the boosted voltage and generate a regulated boosted voltage based on the boosted voltage, and a control and monitoring engine configured to provide the control signal based on, at least in part, the input voltage, the oscillator signal, and the regulated boosted voltage.

[0004] Implementations may include one or more of the following features.

[0005] The mixed-signal integrated circuit may further include a ring oscillator configured to: receive the input voltage and the control signal; and provide the oscillator signal. A frequency of the oscillator signal may be adjustable based on, at least in part, the control signal. The boosted voltage may be increased when the frequency of the oscillator signal is increased. The boosted voltage may be decreased when the frequency of the oscillator signal is decreased.

[0006] The network of capacitors may be adjustable to affect the charge pumped such that the boosted voltage is altered. The boosted voltage may be increased when a capacitance of at least one capacitor from the network of capacitors is increased. The boosted voltage may be decreased when a capacitance of at least one capacitor from the network of capacitors is decreased.

[0007] The mixed-signal integrated circuit may include an analog-to-digital converter

(ADC) to sense the boosted voltage. The ADC may include a single clocked comparator, wherein the oscillator signal drives the single clocked comparator. The single clocked comparator may be coupled to receive the input voltage, and a reference voltage. The single clocked comparator may be configured to measure the input voltage with respect to the reference voltage.

[0008] The mixed-signal integrated circuit may include a resistive ladder to divide the boosted voltage to generate the reference voltage. The mixed-signal integrated circuit may additionally include multiplexor to select the reference voltage and provide the reference voltage to the single clocked comparator. The single clocked comparator may be configured to generate a first measurement of the input voltage with respect to the reference voltage at a first time point, and generate a second measurement of the input voltage with respect to the reference voltage at a second time point. The first time point may precede the second time point. The mixed-signal integrated circuit may further include a multiplexer configured to select a first instance of the oscillator signal at the first time point, and a second instance of the oscillator signal at the second time point. The first instance of the oscillator signal may precede, in phase, the first instance of the oscillator signal. The control and monitor engine may be configured to: generate the control signal based on the first measurement at the first time point, and the second measurement at the second time point. The mixed-signal integrated circuit may further include: a bandgap reference generator configured to generate the reference voltage.

[0009] The voltage regulator may be configured to regulate the boosted voltage by reducing voltage ripples from the boosted voltage. The input voltage may be about 0.7V to 0.75V and the regulated boosted voltage is up to about multiples of the input voltage. The mixed-signal integrated circuit may be configured to drive an analog load with a load current. The frequency of the oscillator signal may be adaptively controlled based upon the load current. [0010] The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other aspects, features, and advantages will become apparent from the description, the drawings, and the claims.

DESCRIPTION OF DRAWINGS

[0011] Fig. 1 illustrates an example of an IC circuit with a fully integrated a high voltage generator according to some implementations of the present disclosure.

[0012] Figs. 2A to 2C show an example of charge pump voltage booster (CPVB) to further illustrate the operation of the high voltage power supply (HVPS) ripple control mechanism according to some implementations of the present disclosure.

[0013] Fig. 3 illustrates the use of an ADC to monitor the voltage levels at HVPS according to some implementations of the present disclosure.

[0014] Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0015] Two trends are concurrently driving the current design of analog and mixed- signal circuits. The first trend is a decrease in voltage of the power supply for an integrated circuit (IC) chip. For example, there is a continuing reduction of power supply in current deep sub-nanometer FinFET processes. In other words, this trend corresponds to a reduction in the voltage provided to power an IC chip. At the same time, the second trend is that more and more chip components are demanding differing driving voltages for improved performance. However, for consumer and Internet of Things (IOT) applications, due to cost considerations, a single lower operational power supply is preferred. Supplying a single IC chip with various higher supply voltages increases the cost of the system. For this reason, it is advantageous to have an efficient localized high voltage generator integrated with the analog circuit, which localized high voltage generator can generate the desired higher voltage from the available lower operational voltage.

[0016] The present disclosure describes various implementations that incorporate a charge pump configuration on the same IC chip as the various analog components demanding varying voltages higher than an input voltage to the IC chip. The charge pump configuration is capable of providing an adjustable voltage (that is higher than the input voltage provided to power the chip) to the various analog components on the same IC chip. The charge pump configuration therefore serves as a voltage booster. Examples of the charge pump configuration includes a PLL voltage boosting charge pump driven by a control signal and an oscillator signal. The control signal may be derived based on an output of the PLL voltage boosting charge pump, an output of a voltage reference generator, and an output of a voltage regulator. The oscillator signal may come from a ring oscillator on the same chip, or can be provided as an input clock signal to the chip. The output of the PLL voltage boosting charge pump can be adjusted by varying, for example, the oscillator signal, the capacitor on the charge pump, or the number of booster stages.

[0017] Fig. 1 shows an example of an IC circuit 100 with fully integrated a high voltage generator. The IC circuit 100 can operate off a 0.75 V supply. The high voltage generator can boost the input voltage supply internally to a 1.2V supply. The IC circuit 100 may include both low voltage and high voltage transistors, each operating on respective voltages. In particular, the IC circuit 100 can operate under a local supply voltage VOUT 122, where VOUT can be higher than VIN 120, receive from a pin of the IC circuit 100.

[0018] As illustrated in Fig. 1, a charge pump based voltage booster (CPVB) 101 receives a low voltage power supply (LVPS) or VIN 120. The IC chip on which CPVB resides may include one or more pins to receive VIN 120. However, the IC chip may not receive additional input power supplies. In other words, the IC chip may receive one input power supply. CPVB 100 can receive another input, namely, a clock (CLK) 127, which in some cases has a swing equal to the amplitude of the LVPS. This swing can refer to half of the rail-to-rail amplitude. CPVB 101 provides a high voltage power supply (HVPS) 121 as its output. In a situation where loss can be ignored, CPVB 101 accepts input voltage VIN at its input and produces a high voltage, for example, equal to the value of low voltage VIN plus amplitude of clock) at its output. If the amplitude of clock is equal to the value of low voltage, the high voltage produced can double the value of low voltage. In this example, if the LVPS and the CLK 127 are each 0.75 V in amplitude, then the HVPS can be up to 1.5 V. If a voltage higher than the double is desired, a multi-stage voltage booster can be used to generate three times or four times the supply voltage. The output current capability of the CPVB is dependent on the frequency of CLK 127. For example, the higher the clock frequency, the larger the current drive at output. The CPVB 101 may accept yet other inputs 129, which can be used to configure the structure of the CPVB 101, such as, for example, selecting the number of boosting stages, sizes of capacitors, sizes of active switchers.

[0019] A ring oscillator (RO) 102 can operates at the lower voltage LVPS and supply clock signal CLK 127 to the CPVB 101 and analog-digital converter (ADC) 103. The RO 102 may be at a fixed frequency (or a variable frequency that can be controlled). For example, the RO 102 can include a chain of N inverters where N is an odd number. If all N inverters are connected in a loop, RO 102 will produce a frequency of / = 1 /(TV X 2 X t _d ) where td is the delay from input to output of each cell. If N-2 inverters are connected in series, the frequency is increased to / = 1 /((TV — 2) X 2 X t _d ) and so on. Alternatively, the frequency could be controlled by a bias current or other analog control, which may itself may be generated and controlled by analog or digital means.

[0020] A bandgap reference generator (BG) 104 can connect to the HVPS 121. The BG

104 can produce an accurate reference voltage (VREF) 123 of, for example, 1.2V and provide the voltage as reference to the low dropout voltage regulator (LDO) 106. The BG may also provide other reference voltages 124, 125 to the droop sensor 103 and control & monitoring engine CME 105.

[0021] A low dropout voltage regulator (LDO) 106 receives, as inputs, HVPS 121 and

VREF 123 and produces a further regulated voltage at its output VOUT 122. In this example, VOUT 122 can be 1.2V. The LDO 106 may further remove ripples from the further regulated voltage at VOUT 122. As illustrated, VOUT 122 drives analog circuit 107 as a load.

[0022] A control and monitoring engine (CME) 105 may receive the various sensed values from the ADC 103, HVPS 121, LVPS 120, bandgap reference 125, and VOUT 122, and generates a control signal 129, which can appropriately configure the CPVB 101 and RO 102. In one illustration, ADC 103 senses HVPS 121 and generates a sensed signal on line 126 to feed CME 105. For example, if droop is in excess of a defined value VdroopH, CME 105 can send control signal 129 to RO 102 to increase the frequency of clock signal 127 and hence reduce the voltage droop. Alternatively, if the droop is below a defined value VdroopL, then CME 105 can send control signal 129 to RO 102 to reduce the frequency of clock signal 127. In some cases, to maintain the power consumed by this system at a desired level, the system can perform at lower frequencies (hence lower power consumption) at lower output current loads and vice versa. [0023] The CME 105 can have an indicator output signal 128, with various functions.

For example, the CME 105 can monitor the bandgap reference and indicate a signal BGG _OOC I=1 when the CME 105 senses VREF is in the appropriate range. The CME 105 can monitor LVPS 120 with respect to VREF and indicate a signal LVGood=l when LVPS 120 is within appropriate range. The CME 105 can monitor HVPS 121 with respect to VREF and indicate a signal HV Good ⁼ 1 when HVPS 121 is within appropriate range. The CME 105 can monitors VOUT 122 and indicates a signal VouT_Good=l when VOUT 122 is within appropriate range. In some cases, the indicator output signal 128 can have multiple bits, each representing the abovementioned monitoring outputs.

[0024] Further referring to Figs. 2A to 2C, an example of a charge pump voltage booster

(CPVB) 200A is shown to further illustrate the operation of the HVPS ripple control mechanism. Fig. 2A particularly shows a schematic of CPVB 200A, as an example of CPVB 101 in Fig. 1. Here, a core voltage or LVPS 221 is applied to the source nodes of N channel transistors of inverters 204 and 205, as indicated by Vss. As illustrated, inverters IA 204 and IA 205 are connected in series back to back. Inverter 204 generates an inverted output at terminal 226. Inverter 205 generates an inverted output at terminal 227. A high voltage power supply (HVPS) 223 is connected to the source nodes of P channel transistors of inverters IA 204 and IA 205, as indicated by VDD. Complementary clocks CLKA 224 and CLKB 225 may be derived from input clock CLK 222. As illustrated, CLKA 224 and CLKB 225 are respectively capacitively coupled to the gates of inverters 204 and 205 through capacitors 202 and 203. Load capacitor CL 206 is connected to HVPS 223 to smooth the ripple at HVPS 223. ADC 207 is driven by clock SCLK 228. This configuration allows a voltage build-up at HVPS 223. As illustrated, at each rising edge of CLKA or CLKB, electrical charges are injected into CL 206. At steady state, the maximum value of HVPS 223 is about double the value of LVPS 221, when the amplitude of clock signals 224 and 225 are the same as the voltage of LVPS 221. [0025] Fig. 2B illustrates an example 200B for generating phase varied edges of CLKA and CLKB to produce SCLK. As illustrated, CLK 222 drives a series of inventors. Here,

CLKA EARLY 224E is a phase advanced version of CLKA 224. For example, CLKA EARLY 224E is ahead in phase of CLKA 224 by a suitable value, as determined by the phase delay of each inverter between CLKA EARLY 224E and CLKA 224. CLKB LATE 225L is a phase delayed version of CLKB. For example, CLKB LATE 225L is delayed in phase of CLKB by a suitable value as determined by the phase delay of each inverter between CLKB 225 and CLKB LATE 225L.

[0026] Fig. 2C shows an example of a diagram 200C illustrating how CLKB LATE 225L samples the value of HVPS 223 at its rising edge by using an analog to digital comparator ADC 207 or other suitable method. This value is called VSi, and represents the highest value of HVPS 223, i.e. VMAX(HVPS). CLKA EARLY 224E samples the value of HVPS 223 at its rising edge. This value is called VS2 and represents the lowest value of HVPS 223, i.e. VMIN(HVPS). The difference between VSi and VS2 is known as droop of HVPS 223 voltage.

[0027] At steady state operation, if VSi is less than a pre-defmed value of, for example,

1.9 x LVPS, additional capacitance can be added to CA 202 and CB 203, or alternatively additional transistors can be added to the inverters IA 204 and IB 205 to increase VMAX(HVPS). Conversely, if VSi is higher than a pre-defmed value of, for example, 1.95 ^c LVPS, some capacitance can be deducted from CA 202 and CB 203 or alternatively some transistors can be deducted from the inverters IA 204 and IB 205 to decrease VMAX(HVPS). In other words, depending on the sensed VSi, capacitance coupled to IA 204 and IB 205 can be adjusted to induce more or less charge build-up so that the sensed VSi becomes closer to the pre-defmed value. For example, more capacitors can be switchably included in or excluded from the coupling to IA 204 and IB 205.

[0028] At steady state of operation, if VS2 is less than a pre-defmed value of, for example, 1.8 ^c LVPS, the frequency of CLK 222 can be increased. If VS2 is more than a pre- defmed value of, for example, 1.85 ^c LVPS, the frequency of CLK 222 can be decreased. This frequency adjustment can also be done to control the value of VSi. The frequency of CLK 222 can be adjusted by, for example, adjusting the configuration of RO 102. In some instances, inter inverter delay can be adjusted. In some cases, the number of active inverters in the ring can be adjusted. [0029] The above mentioned pre-defmed values may be controlled externally or alternatively by feedback from the application. In these cases, a register file may be present on, for example, CME 105. In many cases, the droop/ripple in HVPS is periodic in nature. As such, the sampling need not be done at successive edges of clock signal CLK 222. If VSi is sampled at the rising edge of CLKB LATE, VS2 can be sampled after a few cycles of CLK A EARLY. A slower speed of sampling can allow lower speed operation of ADC or other suitable comparison circuitry, thereby reducing power consumed.

[0030] Referring further to Fig. 3, an example 300 illustrates the use of a single clocked comparator (in lieu of a conventional multi-bit ADC) to monitor the voltage levels at HVPS. In this example, control and monitoring Engine (CME) 302 controls a single clocked comparator CC 301. The use of a single comparator can greatly reduce power consumed by the monitoring circuitry. Boosted voltage HVPS 303 is resistively divided down using a resistive ladder including resistors 304, 305, 306, 307, 308, 309, and 310 and multiple taps 311, 312, 313, and 314. A set of pre-defmed voltages equivalent to, for example, 1.95 ^c LVPS, 1.9 * LVPS, 1.85 ^c LVPS and 1.8 ^c LVPS can respectively feed into an analog multiplexer (MUX) 315. The output 316 of the analog mux 315 is provided to the positive (+) terminal of clocked comparator 301. LVPS 317 is fed into the negative (-) terminal of the same clocked comparator. A second mux 318 has, as its inputs, multiple clocks, for example CLKA EARLY 319 and CLKB LATE 320. Both mux 315 and mux 318 are controlled by the CME 302.

[0031] To determine if the highest value of HVPS, i.e. VSi is within a desired range of

1.9 to 1.95 of LVPS, the CME 302 can control mux 318 such that CLKB LATE is connected to the CLK node 322 of CC 301. In this configuration, two measurements can be made, namely, one measurement when node 311 is connected to 316 denoted M195 and the other measurement when node 312 is connected to 316, denoted M19. The results of the two measurements can be interpreted according to the following table 1.

[0032]

Table 1 [0033] To determine whether the lowest value of HVPS, i.e. VS2 is within desired range of 1.8 to 1.85 of LVPS, the CME 302 can control mux 318 such that CLKA EARLY is connected to the CLK node 322 of CC 301. In this configuration, two measurements can be made, namely, one measurement when node 313 is connected to 316 denoted Ml 85 and another measurement when node 314 is connected to 316, denoted Ml 8. The results of these two measurements can be interpreted based on the following table 2.

[0034]

Table 2

[0035] By continuously monitoring and taking appropriate action, as described, the boosted voltage HVPS can be set to the desired level and droop of HVPS can be controlled to desired level at optimum efficiency.

[0036] What has been described is a method and apparatus which can be employed on a mixed signal integrated circuit (IC) chip to, for example, provide an increased voltage supply on board the chip based on an off-chip low-voltage power supply. In other words, a mixed-signal IC can be constructed out of low voltage and high voltage transistors using a fully integrated high voltage generator. Such a mixed-signal IC can operate on a single low voltage supply, as opposed to operating on dual low voltage and high voltage supplies. Based on the single low input voltage, the mixed signal IC can generate a precise higher voltage for sustaining the operations of the on-chip high-voltage transistors. The mixed signal IC can provide additional optional control bits for selecting between a range of desired output voltages for powering the on-chip high-voltage transistors. The voltage booster feature is self-contained. The examples illustrated within utilize a charge pump voltage booster (CPVB) device as a voltage booster on the mixed-signal IC chip. The clocking frequency of the CPVB can be adaptively controlled based upon the load current. Although the example of PLL circuit is advantageously employed as an on-chip component, the advantages of the application may be exploited, for example, in conjunction with microcontroller chips having very high operational frequencies. Indeed, a number of implementations have been described. For example, implementations can include a precise reference voltage generator such as a Bandgap reference (BG) to generate a precise reference voltage, using internal feedback/control mechanisms. The output(s) of the precise reference generator can be used for power supply monitoring, e.g., providing accurate output signals indicating the input voltage, the output voltage, or other values are within acceptable range(s). Nevertheless, it will be understood that various modifications can be made without departing from the spirit and scope of the subject innovation. In addition, the logic flows depicted in the figures do not require the particular order shown, or sequential order, to achieve desirable results. In addition, other steps may be provided, or steps may be eliminated, from the described flows, and other components may be added to, or removed from, the described systems. Accordingly, other implementations are within the scope of the following claims.