The present disclosure relates to a method of controlling a Direct Current (DC) to Alternating Current (AC) Modular Multilevel Converter (MMC).

BACKGROUND

An MMC is a power converter of the type Voltage Source Converter (VSC), also called Voltage Source Inverter, comprising series-connected cells (also known as modules or submodules), forming a converter branch (also known as arm). These branches can be configured in several manners leading to dedicated converter topologies. Depending on the output voltage

requirements of these branches to provide only positive or also negative voltage, the cells of a branch can be implemented by means of only half bridge (HB, also called unipolar or unidirectional) cells, or full-bridge (FB, also called bipolar, bidirectional or H-bridge) cells or a combination of HB and FB cells, respectively. A DC-to-three-phase AC MMC inverter structure in double-star configuration may be used for interconnection of a three-phase grid, e.g., 50 or 60 Hz, with a DC grid, e.g. a High-Voltage DC (HVDC) grid.

An HVDC connected MMC inverter is prone to high cell overvoltage during internal AC faults, an internal AC fault being a fault between the MMC, specifically the cells/valves thereof, and the secondary side, also called valve side i.e. the side facing the MMC and facing away from the AC grid, of a transformer interface with the AC grid.

WO 2017/080597 discloses an MMC for handling AC side faults. The MMC comprises a control unit configured to enter a first protective control mode upon the detection of an operational disturbance of the converter, the first protective control mode comprising controlling all the bipolar voltage contribution cells to operate as unipolar voltage contribution cells, and if the operational disturbance is identified as a fault on a phase of a connected AC link, to block the cells of the phase leg connected to the phase for the remainder of the first protective control mode and control the cells of the phase legs connected to the healthy phases of the AC link to handle effects of the fault. This solution is mainly applicable to MMC arms with only FB cells, while situations with arms having a mixture of FB and HB cells may be more challenging to handle.

SUMMARY

It is an objective of the present invention to provide novel way of detecting and handling internal AC faults in inverter arrangements comprising at least one MMC, especially when said inverter arrangement comprises a plurality of series connected MMCs. Some embodiments of the invention may be particularly useful for an MMC with arms having a mixture of FB and HB cells. Also, some embodiments of the invention may be especially useful for an MMC connected in series with at least one other MMC.

According to an aspect of the present invention, there is provided a method of controlling an inverter arrangement between a DC network and a three-phase AC network. The inverter arrangement comprises a plurality of series connected converter arrangements, each comprising a controller and an MMC having a topology with one positive arm and one negative arm per phase. Each of the arms comprises a plurality of series-connected converter cells, each of which cells comprising an energy storage and a plurality of valves. At least 50% of the plurality of series-connected converter cells of each arm are full-bridge cells. The method comprises, in each of the plurality of converter arrangements, by means of the controller in the converter arrangement: sensing at least one property of the MMC; based on the sensed property, detecting that an internal AC fault has occurred in one of the plurality of converter arrangements; and, in response to the detecting of the fault, controlling the MMC in the converter arrangement by blocking its negative arms while keeping deblocked its positive arms and controlling the current magnitude of each phase toward zero.

According to another aspect of the present invention, there is provided a computer program product comprising computer-executable components for causing a controller to perform an embodiment of the method of the present disclosure when the computer-executable components are run on processing circuitry comprised in the controller.

According to another aspect of the present invention, there is provided an inverter arrangement configured for being between a DC network and a three-phase AC network. The inverter arrangement comprises a plurality of series connected converter arrangements, each comprising a controller and an MMC having a topology with one positive arm and one negative arm per phase. Each of the arms comprises a plurality of series-connected converter cells, each of which cells comprising an energy storage and a plurality of valves, at least 50% of said plurality of series-connected converter cells of each arm being full-bridge cells. In each of the plurality of series connected converter arrangements, the controller comprises processing circuitry, and data storage storing instructions executable by said processing circuitry whereby said controller is operative to: sense at least one property of the MMC in the converter arrangement; based on the sensed property, detect that an internal AC fault has occurred in one of the plurality of converter arrangements; and, in response to the detecting of the fault, control the MMC in the converter arrangement by blocking its negative arms while keeping deblocked its positive arms and controlling the current magnitude of each phase toward zero.

By means of the way of detecting an internal AC fault outlined herein, the MMC can itself detect an internal AC fault in another MMC with which it is series connected, without the need for time consuming inter-MMC

communication which may delay efficient handling of the fault. Regardless of whether the internal AC fault is at its own MMC or at an other, series connected, MMC, the controller may control the MMC in the same way, by blocking all the negative arm cells while the positive arms keep unblocking and controlling the current of each phase to zero, in accordance with the present disclosure.

It is to be noted that any feature of any of the aspects may be applied to any other aspect, wherever appropriate. Likewise, any advantage of any of the aspects may apply to any of the other aspects. Other objectives, features and advantages of the enclosed embodiments will be apparent from the following detailed disclosure, from the attached dependent claims as well as from the drawings.

Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to "a/an/the element, apparatus, component, means, step, etc." are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated. The use of “first”,“second” etc. for different features/components of the present disclosure are only intended to distinguish the features/components from other similar features/components and not to impart any order or hierarchy to the features/components.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be described, by way of example, with reference to the accompanying drawings, in which:

Fig l is a schematic circuit diagram of an embodiment of a HVDC system, in accordance the present invention.

Fig 2 is a schematic circuit diagram of an embodiment of a DC-to-AC converter arrangement, in accordance the present invention.

Fig 3 is a schematic circuit diagram of an embodiment of a converter arm of an MMC, comprising both HB and FB converter cells, in accordance the present invention.

Fig 4 is a schematic functional block diagram illustrating embodiments of a control method for communication less internal AC fault detection in accordance with the present invention. Fig 5 is a schematic diagram of an embodiment of a sensing arrangement of a converter arrangement, in accordance with the present invention.

Fig 6 is a schematic block diagram of an embodiment of a controller of an inverter arrangement, in accordance with the present invention.

Fig 7 is a schematic flow chart of an embodiment of a control method for internal AC fault handling in accordance with the present invention.

Fig 8 is a schematic flow chart, in more detail, of an embodiment of the method step of detecting of an internal AC fault, in accordance with the present invention.

DETAILED DESCRIPTION

Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments are shown.

However, other embodiments in many different forms are possible within the scope of the present disclosure. Rather, the following embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout the description.

Figure l illustrates a system l, especially a HVDC system, with a DC network 2 connected to an AC network 5 via an inverter arrangement 4. The inverter arrangement 4 comprises at least one VSC in the form of an MMC 7, e.g. at least two MMC 7 in series as in the figure. On the rectifier side, on the other hand, the rectifier arrangement 3 may comprise at least one Line

Commutated Converter (LCC), e.g. at least two LCC in series as in the figure. However, the present disclosure is focused on the inverter arrangement 4.

The inverter arrangement 4 comprises at least one converter arrangement 6 and a controller 10 (see figure 6). Each converter arrangement 6 comprises an MMC and a converter transformer 8 interfacing the MMC with the AC network 5. It may be convenient to series connect MMCs 7, and thus converter arrangements 6, especially for high-voltage application, e.g. HVDC, in view of the voltage rating of each MMC. For instance, as exemplified in the figure, if the nominal voltage of the HVDC network 2 is 8oo kV and the available MMC has a voltage rating of 400 kV, two series connected MMC 7 are needed in the inverter arrangement 4. In the figure, these MMC 7 comprise an upper MMC 7a in an upper converter arrangement 6a, which also comprises an upper transformer 8a, with a positive terminal p at 800 kV (the voltage of the HVDC network 2) and a negative terminal n at 400 kV.

The series connected MMC 7 also comprises a lower MMC 7b in a lower converter arrangement 6b, which also comprises a lower transformer 8b, with a positive terminal p at 400 kV (the same as for the negative terminal voltage of the upper MMC 7a) and a negative terminal n at o kV (connected to ground). Each MMC has two DC terminals: one positive DC terminal p connecting the positive arms 2ip together and one negative DC terminal n connecting the negative arms 21h together. Typically, positive current flows into the MMC at the positive terminal and out of the MMC at the negative terminal.

The first MMC, as discussed herein, can (in the system of figure 1) be either of the upper and lower MMCs, the second MMC being the other one. It should be noted that in other embodiments, the inverter arrangement 4 may include more than two converter arrangements 6 with respective MMCs 7 in series connection.

Figure 2 illustrates a converter arrangement 6, comprising an MMC and a transformer 8, as discussed above with reference to figure 1. Since the AC network 5 is a three-phase AC network, the MMC 7 comprises three phases 20, here denoted 20a, 20b and 20c, respectively, each connected to a respective one of the three phases of the AC network. Each phase 20 comprises two arms 21, a negative arm 21h connected to the negative terminal n, and a positive arm 2ip connected to the positive terminal p. Thus, the MMC 7 has a modular multilevel topology with one positive arm 2ip and one negative arm 21h per phase 20, wherein each of said arms 21 comprises a plurality of series-connected converter cells. In some embodiments of the present invention, the MMC has a double-star topology (also called double- wye, or double-Y, topology), as in figure 2.

In the figure, the valves V of the different arms 21 of the MMC j are

collectively referenced as: Vap for the positive arm 2ip of phase 20a, Van for the negative arm 2in of phase 20a, Vbp for the positive arm 2ip of phase 20b, Vbn for the negative arm 2in of phase 20b, Vcp for the positive arm 2ip of phase 20c, and Vcn for the negative arm 2in of phase 20c.

An internal AC fault 22 is illustrated schematically in figure 2. As discussed herein, an internal AC fault is a fault that occurs in a converter arrangement 6 between the valve side of the transformer 8 and the MMC 7, typically defined as the valves of the MMC.

Figure 3 illustrates an arm 21 of an MMC 7, e.g. any of the positive or negative arms in figure 2. The arm 21 comprises a plurality of series- connected converter cells 31, and (optionally) at lest one series connected reactor 34. Each of the cells comprises an energy storage 33 and a plurality of valves 35. In the example of figure 3, the arm comprises both full-bridge (FB) cells 31F and half-bridge (HB) cells 31H, here in a 1:1 ratio of 50% each.

Typically, at least 50% FB cells 31F are needed, thus with at most 50% HB cells. Thus, in accordance with the embodiments of the present disclosure, each arm 21 has between 50-100% FB cells. However, as further discussed below, embodiments of the present invention may be especially useful when each arm 21 comprises at least one HB cell, e.g. up to 50% HB cells.

Each valve 35 comprises a semiconductor switch S, here conventionally denoted Si, S2, S3 & S4 in an FB cell 31F and Si & S2 in an HB cell 31H. In the figure, each of the semiconductor switches S comprises a Bi-Mode

Insulated Gate Transistors (BIGT), which may be suitable in some

embodiments. However, another type of semiconductor switch may be suitable in some other embodiments, e.g. Insulated-Gate Bipolar Transistor (IGBT), Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), Forced-Commutated Thyristor or any other forced-commutated switch. Each valve 35 typically also comprises an anti-parallel one directional

semiconductor device 36, e.g. comprising a diode such as a free-wheeling diode. To avoid cluttering of the figure, the reference numerals for the valves

35 and anti-parallel one directional semiconductor devices 36 are only given in the top cell of the figure.

The energy storage 33 may comprise a capacitor arrangement comprising at least one capacitor. The energy storage 33, and thus its cell 31, may be charged and discharged during operation while its cell 31 is inserted, not bypassed, in its arm 21. A cell 31 can only be charged or discharged when inserted. Also, charging or discharging of cells depends on current direction. Therefore, due to the different structure of FB cells 31F compared to HB cells 31H, the charging and discharging of cells might be different for FB and HB cells in the same arm 21. For example, when negative arms 21h are blocked, for a current flowing from ground through the negative arms, the HB cells will be bypassed via the anti-parallel one directional semiconductor devices

36 (and therefore not charged), while FB cells will be inserted via the anti parallel one directional semiconductor device 36 (therefore charged and resulting in increased voltage). Thus, reverse voltage can be made by FB cells in the negative arms which can limit the cell charging currents resulting from an internal AC fault 22, herein also called fault current, in the inverter arrangement 4. It follows that the fault current is more effectively limited if all cells in each arm is an FB cell. However, embodiments of the present invention are useful with up to 50% HB cells in each arm.

Another factor to consider is the time period from occurrence of the fault 22 and the detection thereof, the detection delay. The smaller detection delay, the more effective the limiting of the fault current. To effectively limit the fault current when HB cells are in the arms may, in conformity with the discussion above, be especially important. Thus, in accordance with the present invention, a communication less detection of an internal AC fault in a series connected converter arrangement 6, i.e. a detection in a first converter arrangement, comprising a first MMC, typically by a converter arrangement sub-controller of the controller 10, of an internal AC fault in a series connected second converter arrangement, comprising a second MMC, without the need for signalling information from the second converter arrangement to the first converter arrangement for informing the first converter arrangement of the fault in the second converter arrangement.

Figure 4 illustrates example embodiments of the process of communication less detection in a first converter arrangement 6a or 6b of an internal AC fault in a second converter arrangement 6b or 6a, e.g. performed by a converter arrangement controller 10 of the first converter arrangement.

Input to the process of the embodiment of figure 4 are (herein indicated as per unit, pu):

- The DC current Idc which is followed over time e.g. continuously or periodically sampled, e.g. as measured at the positive terminal p and/or the negative terminal n of the MMC. The direction of the DC current measurement at the positive terminal p is positive in the direction of entering the MMC 7 (a current towards the valves of the MMC is positive), while the direction of the DC current measurement at the negative terminal n is positive in the direction of exiting the MMC 7 (a current in the direction away from the valves of the MMC is positive). The sum of currents flowing in the valve positive arms 2ip (Vap, Vbp, and Vcp) is equal to the DC current Idcp, and similarly the sum of currents flowing in the valve negative arms 21h (Van, Vbn, and Vcn) is equal to the DC current Idcn. Thus, the sum of arm currents in 2ip/2in can also be used instead of the DC current.

o Based on the DC current Idc, the pre-fault DC current (Idcpreflt), as measured e.g. at positive p and/or negative n terminals of the MMC before the fault 22 may be compared with the DC current during the fault 22.

- The DC voltage (Udc) of the MMC which is followed over time e.g. continuously or periodically sampled.

o The sensing of the DC voltage allows the determining the

voltage difference AUdc over a predetermined number of control cycles. In an embodiment, the number of control cycles may be 3, i.e. AUdc is calculated as the difference between the measured Udc of the present control cycle minus the measured Udc of the control cycle three cycles ago. Typically, the number of control cycles is an integer within the range of 1 to 10, or 2 to 5, preferably 3 according to experimental results. Typical examples of the control cycle duration are in the range of from 100 to 200 ps.

- Optionally, the DC voltage rating of the MMC may in some

embodiments be used as the predetermined threshold voltage value Umi.

- Based on the sensed voltage and current Udc and Idc, the pre-fault power of the first MMC may optionally be obtained, which may be used to determine whether the converter is in inverter operation before the fault (during steady state operation). This may be optional e.g. since it may already be known whether the MMC is operating as an inverter or rectifier.

The process steps for communication less fault detection in a first MMC 7 in series connection with other MMC(s) may then be: a) During fault 22, if DC current Idc in the converter changes its direction from positive to negative with more than the predetermined second threshold current value, e.g. in the range of -1.2 to -2.0 pu, e.g. -1.5 pu, where the minus sign indicates that the current has changed its direction, an internal AC fault has occurred in an upper converter arrangement 6a (the first MMC being part of a lower converter arrangement 6b in relation to the upper converter arrangement in which the fault has occurred). Note that both DC currents at pole and neutral in lower converter may typically change in the same direction with the same level. Also note that the converter arrangement controller 10 may not know beforehand whether its converter arrangement with the first MMC is connected as an upper or lower converter arrangement in the inverter arrangement 4. b) During fault 22, if the DC current Idc increases in the same direction (implying no minus sign since the current does not change direction) with more than the predetermined first threshold current value Imi, e.g. in the range of 0.2 to 1.0, e.g. 0.5 pu, an internal AC fault has occurred in a lower converter arrangement 6b (the fist MMC being part of an upper converter arrangement 6a in relation to the lower converter arrangement 6b in which the fault has occurred). Note that Both DC currents at pole and neutral in upper converter may typically increase in the same direction with the same level. Again, note that the converter arrangement controller 10 may not know beforehand whether its converter arrangement with the first MMC is connected as an upper or lower converter arrangement in the inverter arrangement 4, why both steps a) and b) may be performed for the first MMC and the OR function illustrated in figure 4 indicates that if either of what is discussed in a) and b) occurs, an internal AC fault may have occurred. c) Optionally, during fault 22, the DC voltage difference (AUdc) within e.g. three control cycles may fulfil the requirements of being above the

predetermined threshold voltage value Umi and/or below the negative of said predetermined threshold voltage value -Umi. The predetermined threshold voltage value Umi may be within the range of 0.5 to 1.0 pu, e.g. corresponding to the voltage rating of the MMC. In some embodiments, the difference in the sensed DC voltage difference (AUdc) is both above the predetermined threshold voltage value Umi and below the negative of said predetermined threshold voltage value -Umi during a predefined time window e.g. of a few milliseconds, such as five or three milliseconds or a quarter of fundamental frequency cycle of the AC network 5. This condition of step c) together with above mentioned conditions of steps a) and b) may distinguish an internal AC fault from other types of fault (for example DC faults).

An OFF-Delay may be applied when either criterion a) or b), or criterion c) has occurred, which implies that when a signal goes high and then again goes low, it remains high for a set time as specified by the OFF-delay time. Since voltage and current transients due to the fault 22 can occur at slightly different times in the MMC, the OFF-delay may be used after determining fulfilment of either of condition a) or b) or condition c) to see if the other condition [ c) or a)/b) ] is also fulfilled. Typical examples of the OFF-delay duration may be within the range of from 10 to 20 ms. The Output in figure 4 refers to the output from communication less fault detection algorithm.

Note that a communication less fault detection approach for series converters is faster than using direct communication, which always include some communication delays. The reason is that a communication less approach detects a fault 22 in an initial stage of the fault and does not wait on the faulty second converter arrangement to first detect the fault and then to

communicate the fault to the first converter arrangement.

If the internal AC fault 22 instead occurs in the first converter arrangement, the fault is detected, by the converter arrangement sub-controller of the controller 10, directly by conventional means, e.g. using differential protection.

Regardless of whether the fault 22 has been detected, by the first converter arrangement, in the first converter arrangement directly or in the second converter arrangement by communication less detection, the same process steps for controlling the first MMC are taken, i.e.:

- The positive arms 2ip of the first MMC should stay in operation, i.e. keep deblocking, controlling the phase currents toward zero, e.g. to zero or near zero as it converges towards zero by means of the controlling of the positive arms, e.g. controlling the phase current until the magnitude of the phase current near zero.

- The negative arms 21h of the first MMC should block, causing FB cells 31F in the arms 21h to build reverse voltage on the negative arms.

A consequences of this control approach is that the reverse voltage that can be produced by the FB cells on the negative arms is enough to limit the cell charging currents due to the internal AC fault 22. Figure 5 illustrates a sensing arrangement 51 in a converter arrangement 6 at each terminal of the MMC 7 in said converter arrangement, at which terminals the forward current (the current flowing in positive direction from the DC grid 2 towards ground) flows into and out of the valve arrangement of the MMC, respectively. The sensing arrangement can be used for the sensing of DC current Idc and DC voltage Udc as discussed herein. The sensing arrangement (51) includes a current sensor (52) and a voltage sensor (53).

The current sensor is arranged to sense a DC current locally within the converter arrangement 6, e.g. without the need for a separate communication channel. Similarly, the voltage sensor is arranged to sense a DC voltage locally within the converter arrangement. The converter arrangement further includes a controller (54) which receives the sensed DC current and DC voltage from the current and voltage sensors respectively. Said controller 54 may be a part or sub-controller of the controller 10 of the converter arrangement 6 as discussed herein.

Figure 6 schematically illustrates an embodiment of a controller 10 of the inverter arrangement 4 of the present disclosure. The controller may e.g. be centralized or distributed, and the controller may e.g. comprise sub controllers for each of the MMCs 7, in each of the converter arrangements 6, in the inverter arrangement 4 and/or each of the cells 31 and/or valves 35 of said MMCs. Typically, each converter arrangement 6 comprises a controller 10, which may or may not communicate with other controllers in the inverter arrangement. The controller may be arranged for controlling the MMC(s) of the inverter arrangement 4 by using references and controlling the

conducting and non-conducting states of the valve switches S of said MMC(s) based on said references. The controller 10 comprises processing circuitry 11 e.g. a central processing unit (CPU). The processing circuitry 11 may comprise one or a plurality of processing units in the form of microprocessor(s).

However, other suitable devices with computing capabilities could be comprised in the processing circuitry 301, e.g. an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or a complex programmable logic device (CPLD). The processing circuitry 11 is configured to run one or several computer program(s) or software (SW) 13 stored in a data storage 12 of one or several storage unit(s) e.g. a memory.

The storage unit is regarded as a computer readable means as discussed herein and may e.g. be in the form of a Random Access Memory (RAM), a Flash memory or other solid state memory, or a hard disk, or be a

combination thereof. The processing circuitry 11 may also be configured to store data in the storage 12, as needed.

Figure 7 illustrates some embodiments of the method of the present disclosure. The method comprises sensing Ml properties of the MMC, e.g. a DC current Idc and a DC voltage Udc of the MMC. The method also comprises, based on the sensed Mi properties, detecting M2 that an internal AC fault 22 has occurred in one of the plurality of converter arrangements. For instance, said detecting M2 comprises, in some embodiments, detecting that the internal AC fault has occurred in its own converter arrangement or, in some other embodiments, detecting that the internal AC fault has occurred in another of the plurality of converter arrangements.

As discussed herein, the detecting M2 may be by means of a communication less detection process, especially when the fault 22 is detected in a series connected converter arrangement 6 other than the converter arrangement doing the detecting M2. With reference to figure 8, the communication less detection M2 then comprises determining pre-fault 22 DC current, Idcpreflt, e.g. at positive terminal p and/or negative terminal n of the MMC. Further, the detection M2 may comprise determining Mil that the difference between the sensed DC current Idc and a pre-fault DC current Idcpreflt either is above a predetermined first threshold current value Imi or is below a

predetermined second threshold current value Im2. In some embodiments, the predetermined first threshold current value Imi is within the range of from 0.2 to 1.0 pu. In some embodiments, the predetermined second threshold current value Im2 is within the range of from -1.2 to -2.0 pu.

Further, the detection M2 may comprise determining M12 that the absolute value of a difference in the sensed Mi DC voltage AUdc over a number of control cycles during the fault 22 is above a predetermined threshold voltage value Umi. In some embodiments, the predetermined threshold voltage value Umi is within the range of from 0.5 to 1.0 pu. In some embodiments, the difference in the sensed Mi DC voltage AUdc is both above the

predetermined threshold voltage value Umi and below the negative of said predetermined threshold voltage value -Umi during a predefined time window.

However, in some embodiments, wherein the detecting M2 comprises detecting that the internal AC fault has occurred in its own converter arrangement, the detection M2 comprises using differential protection, rather than the so called communication less detection described herein and with reference to figure 8. Then, in some embodiments, the method comprises signalling information about the detected M2 internal AC fault to the respective controller(s) 10 of the other converter arrangements of the plurality of converter arrangements in the inverter arrangement.

The detection Mi also comprises determining Mil that, e.g. at the positive terminal p and/or at the negative terminal n of the MMC, the DC current Idc during the fault 22 changes its direction with at least 1.5 pu compared with the pre-fault DC current, e.g. according to Idc - Idcpreflt < -1.5 pu, or increases with at least 0.5 pu compared with the pre-fault DC current, e.g. according to Idc - Idcpreflt > 0.5 pu. The detection Mi also comprises determining that difference in DC current during the fault at the positive terminal p, Idcp, and at the negative terminal n, Idcn, is at most 0.1 pu, according to | Idcp-Idcn | < 0.1 pu. The detection Ml also comprises determining M14 that difference in DC voltage, AUdc, over n control cycles during the fault 22 is both above the positive voltage rating, +Udc_rate, and below the negative voltage rating, -Udc_rate, of the MMC times a predefined factor“a” between o and 1 during a predefined time window.

In some embodiments of the present invention, the DC current Idc and DC voltage Udc are sensed Mi at one or both of positive and negative terminals p and/or n of the MMC 7. In some embodiments, DC current Idc is sensed as the DC current flowing into the positive DC terminal p of the MMC, the DC i6 current flowing out from the negative terminal n of the MMC or the current of the (e.g. six) arms 21 of the MMC. In some embodiments, the DC voltage Udc is sensed as the voltage between positive DC terminal p and ground, the voltage between the negative DC terminal n and ground or the voltage across the two DC terminals p and n.

With reference to figure 8, in some embodiments of the present invention, the detecting M2 that the internal AC fault has occurred in another of the plurality of converter arrangements comprises determining Mil that the sensed DC current Idc, during the fault 22, changes equal to or larger than a predetermined first threshold value compared with the pre-fault DC current Idc-preflt, and determining M12 that a difference in the sensed Ml DC voltage AUdc over a number of control cycles during the fault 22 is equal to or larger than a predetermined second threshold value. In some

embodiments, the number of control cycles is an integer within the range of 1 to 10, or 2 to 5, preferably 3.

In some embodiments, that the sensed DC current changes equal to or larger than a predetermined first threshold value corresponds to the sensed Mi DC current Idc changing its direction with at least 1.5 pu compared with a pre fault DC current Idcpreflt, e.g. according to Idc - Idcpreflt < -1.5 pu where Idc may be as sensed at the positive terminal p, i.e. Idcp, or at the negative terminal n, i.e. Idcn, of the MMC 7.

In some other embodiments, that the sensed DC current changes equal to or larger than a predetermined first threshold value corresponds to the sensed Mi DC current Idc increasing with at least 0.5 pu compared with a pre-fault DC current Idcpreflt.

Thus, in some embodiments, the absolute value of the first threshold value is at least 0.5 pu, i.e. the first threshold value is -0.5 pu or +0.5 pu.

In some embodiments of the present invention, the absolute value of the second threshold value is at least the DC voltage rating Udc_rate of the MMC, i.e. the second threshold value is +Udc rate or -Udc rate. In some embodiments, that the difference in the sensed Mi DC voltage AUdc over a number of control cycles during the fault 22 is equal to or larger than a predetermined second threshold value corresponds to that the difference in DC voltage AUdc is both above the positive DC voltage rating +Udc_rate, and below the negative DC voltage rating -Udc_rate, of the MMC during a predefined time window. In some embodiments of the present invention, the predefined time window in the determining step M14 is less than 5 ms, e.g. a quarter of a fundamental frequency cycle of the AC network 5.

In some embodiments of the present invention, at least one, and up to 50%, of the plurality of series-connected converter cells 31 of each arm 21 is a half bridge cell 31H, i.e. each arm comprises both FB and HB cells.

In some embodiments of the present invention, the MMC has a double-star topology.

In at least one of the converter arrangements 6, the detecting M2 comprises detecting the internal AC fault between an other MMC 7b or 7a and a valve side of a transformer 8b or 8a via which the other MMC is connected to the AC network 5, wherein the other MMC is comprised in an external converter arrangement 6 with which the at least one converter arrangement 6 is series connected.

Additionally, in at least one other of the converter arrangements 6, the detecting M2 comprises detecting the internal AC fault internally in said converter arrangement, between its MMC 7a or 7b and a valve side of its transformer 8a or 8b via which its MMC is connected to the AC network 5, i.e. the converter arrangement 6 may detect the fault 22 within itself, by conventional detection processes e.g. differential protection.

Each of the plurality of series connected converter arrangements 6, in response to the detecting of said fault, regardless of whether the fault 22 is detected in its own converter arrangement or externally, controls its MMC by blocking each of the cells 31 in the negative arms 21h while the positive arms 2ip remain in operation and controlling the current of each phase 20 to zero. i8

Embodiments of the method of the present invention may be performed by the controller to, e.g. including a converter controller 51 of each converter arrangement 6, comprised in the inverter arrangement 4, which controller 10 comprises processing circuitry 11 associated with data storage 12. The processing circuitry may be equipped with one or more processing units CPU in the form of microprocessor(s) executing appropriate software stored in associated memory for procuring required functionality. However, other suitable devices with computing capabilities could be comprised in the processor, e.g. an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), etc., in order to control the valves of the respective MMCs 7 in the inverter arrangement 4 and perform embodiments of the method of the present disclosure, while executing appropriate software 13, e.g. stored in a suitable data storage 12, such as a RAM, a Flash memory or a hard disk, or in the processing circuitry itself (as e.g. in case of an FPGA).

Embodiments of the present invention may be conveniently implemented using one or more conventional general purpose or specialized digital computer, computing device, machine, or microprocessor, including one or more processors, memory and/or computer readable storage media programmed according to the teachings of the present disclosure.

Appropriate software coding can readily be prepared by skilled programmers based on the teachings of the present disclosure, as will be apparent to those skilled in the software art.

In some embodiments, the present invention includes a computer program product 12 which is a non-transitory storage medium or computer readable medium (media) having instructions 13 stored thereon/in, in the form of computer-executable components or software (SW), which can be used to program a computer to perform any of the methods/processes of the present invention. Examples of the storage medium can include, but is not limited to, any type of disk including floppy disks, optical discs, DVD, CD-ROMs, microdrive, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), or any type of media or device suitable for storing instructions and/or data.

In a more general embodiment of the present invention, there is provided a method of controlling an MMC 7 in an inverter arrangement 4 between a DC network 2 and a three-phase AC network 5, wherein the method comprises detecting Ml an internal AC fault 22 in the inverter arrangement, and controlling M2 the MMC by blocking each of the cells 31 in the negative arms 21h while the positive arms 2ip remain in operation and controlling the current of each phase 20 to zero. The present disclosure has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the present disclosure, as defined by the appended claims.