CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to international patent application PCT/IB2019/057909 filed on September 19th, 2019, the entire contents thereof being here with incorporated by reference.

FIELD OF THE INVENTION

The present disclosure relates to a method for flattening a substrate or layer. In particular, the present disclosure relates to a method for flattening a substrate or layer using surface profiling, 3D lithography and etching.

BACKGROUND

Diamond material, for example, single crystal diamond is an extremely hard material, available in small substrate sizes. This makes polishing difficult, leading to substrate quality that is worse than for other established materials, such as silica or silicon.

Single crystal diamond is a very interesting material for many applications, for example, in optics, where substrate flatness and parallelism is highly important. Commerically available substrates and polishing services are however limited as to the degree of achievable flatness. Additionally, standard polishing quality is also influenced by substrate thickness as thin substrates are less rigid, and therefore more difficult to polish flat.

Principle factors which govern the quality of the realizable micro-optical structures are surface roughness, absorption, flatness and parallelism (especially for transmission-type devices). Absorption is primarily determined by substrate growth quality, while sidewall roughness is a product of the etching process and used material stack. Surface roughness, flatness and parallelism are primarily determined by the polishing regime employed. However, polishing can introduce defects in the top surface, such as polishing pits and create dislocations that extend below the surface due to the extreme mechanical stress. Figure 9(a) shows a schematic of a top surface of diamond plate or substrate along with the possible defects that may be present or encountered resulting from known polishing methods.

The strict requirements for producing high optical quality components show the need for high-quality substrates and in particularthe need for high-quality diamond substrates. When as-received substrates don’t meet requirements for the application envisaged, additional processing is required to be carried to improve the surface quality to a level that produces a high optical quality component. Figure 8 shows a list of different available diamond samples/substrates. The Inventors characterized the surface properties of these samples/substrates. While substrates/plates are typically smooth enough between defect pits, some samples exhibit large defect density (resulting in a large mean roughness). Pits decrease bonded area and reduce fabrication yield, which is especially problematic when large area photonic circuits need to be fabricated. Unfortunately, as can be seen from the data in Figure 8, flatness is not a common requirement of diamond plates, and is typically not guaranteed by suppliers. As mentioned above, flatness is an important requirement for high optical quality components.

Achieving highly flat surface is, however, a challenge. Moreover, from the table of Figure 8, it is also apparent that it is difficult to obtain substrates that are both flat and smooth.

SUMMARY OF THE INVENTION

It is thus a goal of the present disclosure to address the above-mentioned limitations of current substrate processing methods.

The present invention addresses the above-mentioned limitations by providing a layer or substrate flattening method according to claim 1 .

The method of the present disclosure advantageously provides a substrate or material flatness compatible with the requirements of high optical quality components.

The method for flattening substrates uses surface profiling, 3D lithography and etching, for example, proportional dry etching. The as-received substrate is profiled to measure the deviation from ideal flat surface, the profile data is processed, for example, into a 3D photoresist profile, that is written onto the substrate. The resist and substrate are etched using, for example, a directional plasma, transferring the resist profile into the substrate. The resist profile is chosen so that during etching the original deviation is cancelled out, leaving a flat surface.

This method can, for example, be repeated on the second surface of a substrate to have two flat surfaces, or the sample can profiled in transmission to eliminate a wedge error/improve the parallelism of the substrate.

While the examples provided in the present disclosure concern processing single crystal diamond, a substrate difficult to flatten/parallelise due to its hardness, it should be noted that the method could be adapted to other difficult to polish materials, such as but not limited to silicon carbide. While the method of the present disclosure is particularly advantageous with hard materials, it can equally be used for flattening other materials and is not limited to hard materials. Furthermore, the low selectivity of the etch process advantageously decreases the stepwise nature of the patterning, improving the result. The etch process also advantegously imparts smoothening to the substrate.

The etch for etching diamond substrate has sufficiently low selectivity. 3D printing or writing was carried out using, for example, voxel overlapping to increase the z resolution of the writing.

The method allows to achieve a sub-10 nm height control in the resulting surface.

Correction for the substrate tilt and accurate realisation of the resist profile can be achieved through customized pattern generation by a conversion computer program.

The process has been developed for, for example, diamond flattening, with reliable results. Final tuning can be performed to determine achievable flatness and quality. Field overlapping is assures etching of a continous surface.

The method of the present disclosure can, for example, advantageously assure an improved optical substrate fabrication, provides improved substrates for bonding or optical reference flats, provides extremely flat substrates that can be used as mounts for polishers or flat surface / parallel diamond plates that can be integrated into devices such as lasers, quantum sensors, integrated photonics, biosensors, etc.

The method of the present disclosure also advantageously allows flattening to be obtained over large surfaces via multiple field stitching.

The above and other objects, features and advantages of the present invention and the manner of realizing them will become more apparent, and the invention itself will best be understood from a study of the following description with reference to the attached drawings showing some preferred embodiments of the invention.

A BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Figure 1 schematically shows an exemplary flattening method according to the present disclosure. The specific details mentioned thereon are exemplary and non-limiting details.

Figure 2 also schematically shows an exemplary flattening method according to the present disclosure. A process flow for 3D printing-based flattening is for example shown. I, substrate cleaning, for example, Diamond substrate cleaning and attaching to a carrier wafer. II, Initial surfaces is optically profiled. Ill, Height data is converted into complementary surface. IV, a photoresist, for example, IP-S photoresist is dispensed and exposed in, for example, a 3D lithography system, for example, a NanoScribe system using, for example, a 25x objective. V, Resist development in for example PGMEA and IPA. VI, etching, for example, a Ch-based ICP proportional etch. VII, Optical profiling of the flattened surface. VIII, Evaluation of the flattening performance.

Figure 3(a) shows an improved writing performance of the method of the present disclosure in which the resolution in the Z direction is increased by overlapping voxels, making the effective resolution the overlap distance DZ.

Figure 3(b) shows the effect of tilt compensation. The top image shows the written patterns for a tilted substrate, while the bottom image shows the resulting resist structures with respect to the surface, highlighting the advantage of performing both global and local correction to arrive at a flatter surface.

Figure 3(c) shows resist profiles of three adjacent fields, with different amount of overlap (negative overlap meaning separation). Arrows mark the location of the overlap, where a protrusion can be observed for overlapping fields, while zero overlap and separation result in a hole. Profiles have been offset for easier comparison.

Figure 4(a) shows a schematic for determining the resist height to be written based on the measured height ( h _pre ). The writing of the resist happens relative to a plane, with voxels written inside material lost, therefore the written height has to account for the original topography to arrive at a resist profile ( ) that is correctly scaled with a selectivity S of the etch. Difference in the reference height (dashed line) only results in a constant offset and therefore not a concern for the process.

Figure 4(b) shows a surface evolution for a theoretical etch process which has a selectivity (S) of 1 to aid in the understanding of the method. In this case, the written height needs to be a constant value, to produce a flat surface result.

Figure 5(a) shows a surface profile before and Figure 5(b) shows a surface profile after application of the flattening process of the present disclosure, measured via interferometry. On the central area, where the process and patterning were carried out, the peak to valley flatness is better than 100 nm, corresponding to about a 4-fold improvement or reduction in topography over the same central area.

Figures 6(a) and 6(b) shows a surface profile resulting from the flattening process of the present disclosure in which multiple field stitching has been performed, the surface profile shows the absence of gaps between individual fields and about a 100 nm flatness is achieved over almost the entire 3 mm x 3 mm chip surface (2.8 mm x 2.8 mm).

Figure 7(a) is an AFM measurement of a surface of the flattened area after etching showing that the surface roughness is unchanged with respect to the original surface or original polishing. The vertical grooves are a byproduct of scaife polishing process carried out on the provided sample/substrate that underwent the flattening method of the present disclosure and do not result from the method of the present disclosure.

Figure 7(b) is an AFM measurement of a resist step transferred into diamond. The dashed line shows where the solid line profile was extracted. As expected, a ~10nm step is observed, which equals the DZ multiplied with the selectivity (1 :15).

Figure 8 shows a table listing diamond samples/substrates tested to characterize surface properties.

Figure 9(a) shows an overview of defects in diamond plates - 1 , Surface contamination: slurry particles, organics. 2, Polishing pits (up to hundreds of nm depth). 3, Polishing tracks, shallow. 4, Surface dislocations caused by contact polishing, extend few pm into the bulk. 5, Bulk dislocations, caused by crystal growth. 6, Surface roughness, set by polishing. 7, Surface flatness / parallelism, set by polishing.

Figures 9(b) is a SEM and 9(c) an AFM showing a surface profile of an as-received sample, showcasing the previously mentioned surface defects 1 to 3.

Herein , identical reference numerals are used, where possible, to designate identical elements that are common to the Figures.

DETAILED DESCRIPTION OF SEVERAL EMBODIMENTS

Figures 1 and 2 schematically show an exemplary layer or substrate flattening method according to the present disclosure.

The flattening of the substrate or layer 1 is based on measuring a deviation from an ideal or target substrate flatness (substrate surface flatness) of the current surface, and correcting this deviation by etching the substrate 1 and etching the difference between the measured profile and ideal flat profile.

The layer or substrate flattening method comprises providing a layer or substrate 1 to be flattened. A topography of at least one area 3 (or multiple areas 3) of the layer or substrate 1 to be flattened is then measured. At least one etch layer or etch material 5A is provided on the at least one area 3 of the layer or substrate 1 to be flattened. A topography 7 of the etch layer 5 is defined. This topography 7 allows to correct the deviation from a target substrate flatness across the area 3 as the defined topography 7 assures that the difference or deviation between the measured profile and target flat profile is removed. The at least one etch layer 5 having the defined topography 7 and the at least one area 3 of the layer or substrate 5 to be flattened is then etched. This results in a flattened surface in the at least one area 3 of the layer or substrate 1. The topography 7 defines a surface configuration of the etch layer 5 and an outersurface configuration that is to be exposed to etching.

Etching is carried out up until to a plane PL defined inside the layer or substrate 1 to be flattened. The defined topography 7 of the etch layer is transferred inside the area 3 of the layer or substrate 1 by the etching to produce a flat surface on the area 3 of the layer or substrate 1.

The defined topography 7 of the etch layer is transferred into the topography or surface profile of the layer or substrate 1 to be flattened to produce a flat surface on the area 3 of the layer or substrate 1.

A characterization method or step records the surface profile of the substrate 1 (or of the at least one area 3 of the substrate 1), a patterning method or step creates a profile removal layer 5B (from etch layer 5A) having topography 7 that governs the amount of etching carried out on each point or location across the substrate 1 (or each point or location across the at least one area 3 of the substrate 1) and an etching method or step transfers the pattern or patterns of the profile removal layer 5B into the substrate 1 (or the at least one area 3) to produce a flatter or flattened substrate surface 9 (across the at least one area 3).

Patterning is carried out across the etch layer 5A in X, Y directions but also in a depth direction Z to provide a 3D pattern or the topography 7 across the etch layer 5. This results in the profile removal layer 5B (produced from etch layer 5A) having a pattern or topography 7 across the layer or substrate 1. The profile removal layer 5B permits the measured or current (non-flat) profile of the substrate 1 to be removed when etching the layer 5B and substrate 1 . The pattern or topography 7 is transferred into the substrate 1 to remove the deviation of the substrate surface profile from a target substrate flatness to produce a substrate surface having the target flatness at a (predetermined) depth or level inside the substrate 1.

The flattening method can be repeated on multiple areas 3 of the layer or substrate 1 to flatten a larger surface area of the substrate or layer 1 .

A plurality of areas 3 of the layer or substrate 1 can be flattened across the layer or substrate 1 , or on opposite sides of the layer or substrate 1 to improve parallelism of the surfaces of the layer or substrate 1. A plurality of areas 3 of the layer or substrate 1 can be flattened across the layer or substrate 1 to flatten the full layer or substrate.

The etching is carried out up until to a plane PL (or target plane PL) defined inside the layer or substrate 1 to be flattened. The plane PL extends across the layer orsubstrate 1 in a X-Y direction. The plane PL defines or comprises the flattened surface 9. The layer or substrate 1 to be flattened may, for example, optionally be provided on a carrier substrate or wafer 11 (see, for example, part I of Figure 2). The layer or substrate 1 to be flattened may be attached to the carrier substrate or wafer 11 prior to the surface profile of the substrate 1 being measured and prior to the substrate 1 being etched. In a non-limiting example, the carrier substrate or wafer 11 may comprise or consist of Silicon. The substrate 1 may be attached, for example, using an adhesive that allows later removal of the substrate 1 from the carrier substrate or wafer 11. The adhesive may for example be a wax. The substrate 1 may optionally, for example, be placed inside a depression or recession formed inside the carrier substrate or wafer 11.

The layer or substrate 1 to be flattened may for example comprise or consist of a hard material. The layer or substrate 1 may, for example, comprise or consist of diamond, single crystal diamond or silicon carbide. The layer or substrate 1 may, for example, comprise or consist of a single or mono crystal or crystalline diamond substrates or layers 1.

The single crystalline diamond substrate or layer 1 may for example be non-natural or synthetic single crystalline diamond, for example, chemical vapor deposition CVD single crystalline diamond or synthetic diamond by HPHT (high pressure high temperature) synthesis.

The measured surface profile ortopography ofthe area 3 of the layer or substrate 1 to be flattened can, for example, be determined using optical profilometry or using mechanical profilometry (see, for example, part II of Figure 2). The substrate 1 can, for example, be cleaned prior to the surface profile measurements. Cleaning for example may be carried out by soaking in acetone / IPA (5m), followed by Piranha (1 :4 H ₂ 0 ₂ :H ₂ S0 ₄ , 100°C, 20mins), followed by HF (49%, 20mins).

The method can, for example, use tools such as metrology tools (optical/mechanical profiler), 3D lithography system, and a dry etcher.

Optical profilometry is a fast, non-contact method to measure the topography of a surface or substrate. Vertical scanning interferometry (VSI) or White Light Interferometry (WLI) uses fringe contrast to find surface height. The sample 1 is scanned vertically through the whole height range, and the Z position corresponding to the maximum fringe contrast is recorded for each pixel. These maxima are assembled into a topography image of the area 3 or substrate 1. The size of the image is determined by the magnification ofthe objective used, but multiple images can be taken and stitched to create a composite image spanning multiple field-of-views. For optical profiling, the Inventors used, for example, a Sensofar Neox S system with the Nikon 10X Dl objective in VSI mode. 3-by-3 fields are taken and stitched together to form the topography image.

In the exemplary flattening method carried out by the inventors, a carrier substrate 11 (Si substrate) was used to hold the substrate 1 to be flattened. An image was also taken ofthe topography of a carrier substrate 11 to measure the tilt of the sample 1 with respect to the carrier 11 , because extending the scan range to coverthe carrier 11 degrades stitching accuracy and the stitched image has visible error.

The exemplary flattening method carried out by the inventors presented in the present disclosure was performed on single crystal diamond, it should be noted that the flattening method is not limited to diamond and can equally be used for flattening other materials, hard materials and non-hard materials.

To accommodate the preparation of the topography 7 of the etch layer 5 that subsequently undergoes etching, since the objectives used in such preparation have a working distance of about 300 pm, the substrate 1 was sunk with respect to the carrier substrate 11 to prevent accidentally crashing into substrate 1 during movement. This was achieved using standard lithography and Bosch-process silicon etching, etching square recessions of about 230 pm depth. The substrate 1 was mounted in the recession using an adhesive, for example, QuickStick 135. Part I of Figure 2 shows the substrate 1 mounted on the carrier substrate 11.

The etch layer or etch material 5A,5B provided on the at least one area 3 of the layer or substrate 1 to be flattened may, for example, comprises or consists of a photoresist layer. The etch layer or material may, for example, comprise or consist of a negative photoresist, for example, an IP-S photoresist or an IP-DIP photoresist.

Lithography is performed on the etch layer or etch material 5A to define the topography 7 of the etch layer or etch material that will subsequently be exposed to etching. Lithography can be performed for example to carry out volumetric exposures or voxel exposures of the etch layer or etch material 5A and across the etch layer or etch material 5A to define a desired topography, pattern or profile 7.

The volumetric or voxel exposures are carried out using 3D printing, additive 3D printing, or 3D optical exposure such as grayscale lithography, or subtractive 3D patterning such as scanning probe lithography or nanoimprint lithography.

In an exemplary embodiment, to provide an etch layer having the desired topography, pattern or profile 7, to carryout 3D lithography the inventors used an exemplary 3D lithography system that is a NanoScribe Photonic Professional GT system as a tool for additive manufacturing using two photon polymerization. It should, however, be noted that the present disclosure is not limited to such a specific system and other 3D lithography systems can be used. 780 nm femtosecond laser light is focused to crosslink a volume of photoresist, with the required energy for crosslinking gained only when two photon are absorbed simultaneously. A single point of exposure forms a volumetric exposure in the photoresist or volumetric pixel, or voxel. The size of the voxel depends on the laser power and the used objective. Exposing complex patterns or topographies are done by moving an illuminated spot in X, Y and Z, forming a 3D structure of exposed photoresist. The substrates 1 were placed in a depression of a carrier substrate 11 to simply prevent accidental crashing into substrate 1 during movement.

The plate or substrate 1 was mounted in the recession using the exemplary adhesive QuickStick 135. The carrier wafer 11 was mounted into a holderwhich is loaded onto the Nanoscribe stage. The system is designed so that holder is flat, and the holder being mounted onto the stage so that the tilt of the holder (and by extension, the carrier substrate 11) is zero with respect to the X-Y axes of the stage. The precision required in Z displacement of the writing requires the use of a piezo for moving the write head, and the large area writing requires the use of the galvo-scanner. In this writing mode employed by the Inventors, a galvo-scanner deflects the beam to provide scanning over the field of view of the objective, while the Z displacement is controlled by a piezo translating the stage. The writing proceeds in the X-Y plane line by line, then the Z coordinate is stepped (layer-by-layer writing).

To exploit the NanoScribe Photonic Professional GT system tool of this exemplary embodiment, once the surface height profile of the area 3 or substrate 1 is obtained via the profilometry step, it is converted into an exposure task that can be applied by the NanoScribe tool, applying corrections if necessary so that exposed surface matches the designed surface precisely.

The raw height data can be processed using an SPM data treatment software (see, for example, Necas, David, and Petr Klapetek. “Gwyddion: An Open-Source Software forSPM Data Analysis.” Open Physics 10, no. 1 (January 1 , 2012). https://doi.org/10.2478/s11534-011-0096-2). 2x2 binning can optionally applied to the height images to reduce processing requirements. The tilt of the substrate image is extracted as reference. The profile of the substrate 1 is rotated to align the edges of the substrate 1 with the x-y axes, then the image can be cropped to discard a small region along the edges where the profile data may be unreliable. Next, the tilt is extracted and removed from the profile.

To prevent measurement errors and/or point-like defects influencing the writing/printing process in the etch layer, the image can be low-pass filtered (2D FFT filter). The image is inverted and shifted, so that the range of image is [0,°°). The maximum height value is recorded and the image is exported as a 16- bit TIFF image. For additional correction of the written data, the source image can be further processed using image processing software (for example, ImageMagick, LLC, ImageMagick Studio. ‘‘ImageMagick.” ImageMagick. https://imagemagick.org ).

The resolution of the written pattern in the etch layer 5 depends on the volumetric or voxel exposure size, which in turn primarily depends on the used objective. A large X-Y voxel size decreases writing time (low X-Y resolution), and a high Z resolution provides smooth written features in the etch layer 5. To increase vertical resolution, voxels are overlapped (see Figure 3a), leading to structures and patterns with high Z resolution and that can be written quickly, which can be produced using, for example, a 25x objective. In the exemplary embodiment, a resolution DZ of 150nm was used by the Inventors to expose the structures in the etch layer 5. The voxel exposures in the direction of the height or thickness of the etch layer are highly (>50%) overlapped for increased resolution. The voxel size can, for example, be larger in the Z direction than in the XY-direction.

The topography 7 ofthe etch layer 5 is determined based on (i) the measured topography or profile of the area 3 ofthe layer or substrate 1 to be flattened, (ii) a selectivity S of an etch rate ofthe etching with respect to the etch layer 5 and the area 3 of the layer or substrate 1 to be flattened and (iii) a location of a target plane/zone PL defined or located inside the layer or substrate 1 to be flattened.

The topography 7 ofthe etch layer 5 can, for example, be determined based on the following Equation 1.1 (see Figure 4(a)):

(1-1) where hwnte is a height of the etch layer 5 at a position on the etch layer 5 with respect to a plane PL (the target plane/zone) defined inside the layer or substrate 1 to be flattened, h _pre is a measured height of the area 3 of the layer or substrate 1 to be flattened with respect to that plane and at that same position, and C is a constant.

The topography 7 of the etch layer 5 is determined by determining values for hwnte at a plurality of positions across the etch layer above and corresponding to the area 3. The plurality of values of define the topography 7 or profile of the etch layer 5 that will subsequently be etched.

A height hresist ofthe etch layer 5 with respect to the surface of the area 3 ofthe layer or substrate 1 to be flattened at a position on the etch layer is given by where h _pre is the measured height of the area 3 of the layer or substrate 1 to be flattened with respect to the target plane/zone PL defined inside the layer or substrate 1 to be flattened at that position, C is a constant and, as previously mentioned, S is the selectivity of the etch rate ofthe etching with respect to the etch layer 5 and the area 3 of the layer or substrate 1 to be flattened.

The selectivity S is defined as ERsutstmte/ERetch layer , where ERsutstmte is the etch rate of the layer or substrate 1 to be flattened, and ERetch layer is the etch rate of the etch layer 5. The constant C has a value C>0.

The topography 7 of the etch layer 5 is defined or produced by carrying out a plurality of the volumetric or voxel exposures in and across the etch layer 5A (see, for example, part IV of Figure 2). The etch layer material is configured to strengthen or harden (for example, polymerize or cross-link) where exposure has occurred. The unexposed material of the etch layer is removed to provide etch layer or etch structure 5B to be exposed to etching (see, for example, part V of Figure 2).. Removal of the unexposed material can be carried out using, for example, a solvent or developer. When photoresist is used as the etch layer material 5, the unexposed material can, for example, be removed via photoresist development in Propylene glycol methyl ether acetate (PGMEA) and/or Isopropyl alcohol (IPA) leaving behind the exposed structure having topography 7.

As mentioned above, the resulting etch layer or etch structure 5B defines a profile removal layer 5B having the topography 7 that governs the amount of etching carried out on each point or location across the substrate 1 (or each point or location across the at least one area 3 of the substrate 1) and the subsequent etching transfers the pattern ortopography of this profile removal layer 5B into the substrate 1 (or the at least one area 3) to produce a flatter or flattened substrate surface 9 (across the at least one area 3).

The etch layer (for example, photoresist) image is transferred into the substrate 1 using etching (for example, a proportional etch) forwhich selectivity S, as mentioned above, is defined as ERsubstmte/ERetch tayer, which is typically smaller than 1 for, for example, most plasma etches.

To account for this selectivity S, the source image is scaled by 1/S -1 , yielding a etch layer surface described by Equation (1.1) above, of which the etch layerthickness is given by relating it to the original surface and given by Equation (1.2), which corresponds to scaling the resist by the selectivity and an offset (see Figure 4).

A constant height C is added to ensure the writing/printing in the etch layer is always above the substrate surface. A constant height offset only changes the etch time required to completely etch the resist, but not the shape of the resulting profile. During the etch, the etch layer profile will be proportional to the substrate surface by S, leading to a final profile obeying Equation (1.3) below, a constant (flat) surface. An example surface evolution overtime t is shown on Figure 4(b) with selectivity S = 1 to elucidate the validity of the above equations and calculations.

The etching can, for example, be carried out using a low selectivity etch. The selectivity S is between 1 :1 and 1 :100, for example, 1 :15.

The etching may, for example, comprise or consist of proportional etching or proportional dry etching. The etching, may for example, comprise or consist of plasma etching, deep reactive ion etching or ion beam etching. The etching may, for example, comprise or consist of a chlorine-based deep reactive ion etching. The etching may, for example, comprise or consist of a chlorine-based ICP proportional etch (see for example, Figure 2 part VI).

Proportional etching transfers the 3D profile defined in the photoresist 5 in a proportional or analogue manner into the substrate 1. If one considers an etch process with the material to pattern (bulk) and a masking material, and if one denotes the etch rate of bulk as v1 and the etch rate of the mask as v2, one can derive the selectivity of the process as v1/v2. Any morphological feature in the mask layer gets transferred into the bulk material via the etch process, but the features are scaled by the selectivity.

In the exemplary embodiment in which the inventors used a NanoScribe Photonic Professional GT system, the image is split up into square fields based on the field of view of the objective (a < 300 pm, chosen size is 200 pm). No overlap between the fields results in a trench developing between fields, due to the shrinkage of the resist used as the etch layer or material 5 (Figure 3(c)), while overlap results in a protrusion with a height related to the numberof layers in the overlap area, due to increased ambient dose. The structures are exposed without overlap to prevent protrusions, since protrusions are detrimental for bonding surfaces.

The tool uses an autofocusing system based on Zeiss Definite Focus II, but it is not reliable when multiple optical interfaces are present (such as resist-diamond-resist/air/QuickStick/silicon), resulting in either the system not focusing, unpredictable shifts of focus versus the etch layer - substrate interface or focusing on the carrier surface. The accuracy of the focusing is limited about 1pm, which is not feasible when the exact height is required to be written. Since profile data is available of the height, a manual focusing and tilt correction scheme can be used.

The piezo can address coordinates between [0, 300] pm, thus the focusing is performed by resetting the piezo, then moving to the lowest corner of the diamond 1 and moving the objective to focus (setting the lowest corner).

For subsequent fields, to prevent structures to be written either inside the substrate 11 or above it due to substrate tilt, the written data is offset in Z by the piezo (global tilt correction) based on the measured tilt of the plate 1 (calculated via subtracting the plate 1/substrate 11 tilt from the carrier 11 tilt). Additional compensation of the pattern is applied forthe tilt of the substrate 11 . Since the aspect ratio is very small, the projection of the written pattern to the actual surface is approximated as a plane offset - shear is thus neglected. The tilt of the substrate 11 is extracted as a plane given by a _x , a _y , a _xy ( P = a _x x + a _y y + a _xy x y) and a gradient is generated with a matching slope and added to each field (local correction).

Then each field is offset based on the global position, to match the bottom of the field to the diamond surface (global correction). Figure 3(b) shows the effect of correction: uncorrected structures waste time writing inside the substrate 11 and produce an error proportional to the tilt. Global correction reduces wasted time and the error is reduced, but the profile is discontinuous. Applying local correction in addition to global correction results in a continuous, flat profile.

Correcting for a tilt of the layer or substrate 1 to be flattened on the carrier substrate or wafer 11 thus assures improved flattening. Tilt compensation can be carried out globally and/or locally as mentioned above.

The written height in the exemplary embodiment has a non-1 :1 relationship with the programmed height, likely due to using a high overlap during writing, which causes exposure of the resist outside of the voxel. Since an offset in the resulting structure height does not influence the flattening process, only the linear scaling factor is identified, which is about 0.75 for 150 nm DZ. This linear scaling is not an error of the piezo translation, therefore the manual focusing and tilt correction offsets were not be corrected with this factor. It is expected that the choice of DZ influences the value of this scaling factor.

The data for writing with the NanoScribe Photonic Professional GT system was generated from each pre-distorted image, converted via the Describe commandline mode. The height data is discretized into equidistant levels that are constant across fields to prevent steps and assembled into a field-by-field writing program.

In the exemplary embodiment, a photoresist, for example, IP-S photoresist was dispensed onto the diamond plate 1 and the wafer 11 was loaded into the machine for exposure. Manual focusing is performed as described previously. Once the exposure is completed, the resist 5 was developed in PGMEA for 17 minutes and in IPA for 5 minutes. The resist layer 5 profile or topography 7 was measured to ascertain exposure fidelity via mechanical profiling (as optical profiling can be unreliable due to multiple reflections occurring at the air-resist and resist 5 - substrate 1 interfaces and due to the possibility of discontinuities/high angles surfaces in the resist).

Transfer of the resist pattern into substrate 1 was performed by deep reactive ion etching. A chlorine- based recipe is used (STS Multiplex ICP, 800W coil power, 300W platen power, 5mTorr chamber pressure, 40 seem CI2 and 25 seem Ar, etch rate 64.5 nm min ¹ ), which provides low selectivity (S = 1 : 15) and a smooth surface. 150 nm DZ steps are transferred as 10nm steps in the resulting surface. The etching time is not critical and is chosen to ensure that all resist 5 was etched away. Optical profiling and AFM is used to characterize the resulting surface and the resulting flattened surface is shown in Figure 5(b).

A better than 4-fold reduction of peak-to-valley topography has been achieved via the 3D printing-based flattening of the present disclosure, resulting in a P-V flatness betterthan 100 nm on a 1 4mm x 1 4mm area.

Figures 6(a) and 6(b) shows another surface profile resulting from the flattening process of the present disclosure in which multiple field stitching has been performed. The surface profile shows the absence of gaps between individual fields and about a 100 nm flatness is achieved over almost the entire 3 mm x 3 mm chip surface (2.8 mm x 2.8 mm).

The processed diamond surface may have added roughness compared to the unprocessed one: the noise of the piezo drive is superimposed upon the resulting surface, multiplied by the selectivity (S), along with a stepwise discontinuity arising from the layer-by-layer writing process. In practice, the smoothing property of the etch significantly reduces this effect, and the low selectivity transforms steps into slopes (Figure 7(b)). The piezo could be driven directly with tilt compensation signal, instead of discretising, which would eliminate the stepwise discontinuity. Further reduction of DZ might be feasible to reduce discontinuities, but non-contact polishing techniques, such as IBE polishing can also improve the final roughness.

Figure 7(b) is an AFM measurement of a resist step transferred into diamond. The dashed line shows where the solid line profile was extracted. As expected, a ~10nm step is observed, which equals the DZ multiplied with the selectivity (1 :15).

According to another aspect, the present disclosure also concerns the flattened layer or substrate obtained using the method of the present disclosure.

While the invention has been disclosed with reference to certain preferred embodiments, numerous modifications, alterations, and changes to the described embodiments, and equivalents thereof, are possible without departing from the sphere and scope of the invention. Accordingly, it is intended that the invention not be limited to the described embodiments and be given the broadest reasonable interpretation in accordance with the language of the appended claims. Features of one of the above described embodiments may be included in any other embodiment described herein.