Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2020/066819
Kind Code:
A1
Abstract:
This method for manufacturing a semiconductor device includes a first layering step, a second layering step, a third layering step, a first annealing step, and a fourth layering step. In the first layering step, a first electrode film is layered on a substrate. In the second layering step, a capacitive insulator is layered on the first electrode film. In the third layering step, a metal oxide is layered on the capacitive insulator. In the first annealing step, the first electrode film, the capacitive insulator, and the metal oxide, which are layered on the substrate, are annealed. In the fourth layering step, a second electrode film is layered on the annealed metal oxide. The capacitive insulator is an oxide that includes zirconium and/or hafnium, and the metal oxide is an oxide that includes at least one of tungsten, molybdenum, and vanadium.
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Inventors:
KAWANO YUMIKO (JP)
NAKAMURA GENJI (JP)
GAUBERT PHILIPPE (JP)
NAKABAYASHI HAJIME (JP)
NAKAMURA GENJI (JP)
GAUBERT PHILIPPE (JP)
NAKABAYASHI HAJIME (JP)
Application Number:
PCT/JP2019/036690
Publication Date:
April 02, 2020
Filing Date:
September 19, 2019
Export Citation:
Assignee:
TOKYO ELECTRON LTD (JP)
International Classes:
H01L21/316; C23C14/06; C23C16/34; C23C16/40; C23C16/56; H01L21/768; H01L21/8242; H01L23/532; H01L27/108
Domestic Patent References:
| WO2013035561A1 | 2013-03-14 |
Foreign References:
| JP2014135387A | 2014-07-24 | |||
| JP2013120825A | 2013-06-17 | |||
| JP2013069982A | 2013-04-18 | |||
| JPH06338599A | 1994-12-06 |
Attorney, Agent or Firm:
SAKAI INTERNATIONAL PATENT OFFICE (JP)
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