Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER
Document Type and Number:
WIPO Patent Application WO/2022/219955
Kind Code:
A1
Abstract:
The present invention pertains to a method for manufacturing a semiconductor wafer, the method being characterized by comprising, at least, a chamfering step for polishing the circumferential edge of a wafer and forming a chamfered part which includes a wafer edge portion and a wafer notch portion, a double-side polishing step, a mirror chamfering step, and a mirror polishing processing step. This method is also characterized in that the mirror chamfering step comprises a first mirror chamfering process for polishing, prior to the double-side polishing step, the wafer notch portion in the chamfered part, and a second mirror chamfering process for polishing, after the double-side polishing step, the wafer notch portion and the wafer edge portion, and that the polishing rate for the wafer notch portion in the second mirror chamfering process is set less than the polishing rate for the wafer notch portion in the first mirror chamfering process. Accordingly, it is possible to provide a semiconductor wafer manufacturing method that enables minimizing aggravation of surface roughness in a wafer notch portion, which arises from the polishing rate for the wafer notch portion in a mirror chamfering step during production of a semiconductor wafer.
Inventors:
HASEGAWA RYO (JP)
Application Number:
PCT/JP2022/009007
Publication Date:
October 20, 2022
Filing Date:
March 03, 2022
Export Citation:
Assignee:
SHINETSU HANDOTAI KK (JP)
International Classes:
B24B9/00; B24B37/07; H01L21/304
Foreign References:
| JP2017157796A | 2017-09-07 | |||
| JP2020104210A | 2020-07-09 | |||
| JP2010040876A | 2010-02-18 |
Attorney, Agent or Firm:
YOSHIMIYA Mikio et al. (JP)
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