Title:
Method for placement of clock buffers in a clock distribution system
Document Type and Number:
WIPO Patent Application WO1997039414
Kind Code:
A3
Abstract:
A method for routing clock signals in an integrated circuit provides a hierarchical routing scheme in which the lowest level clock buffers are first placed row by row in preallocated locations and routed to the input pins of standard cells receiving the output clock signals of these clock buffers. Under the method, the number of clock buffers to be placed in each row is computed according to estimates of their load capacitances and expected wiring lengths within a window. The output buffers of the same clock signal are gridded or strapped together to minimize clock skew. A second level of clock buffers are then assigned to drive the lowest level buffers. The hierarchy can be extended to any number of higher levels, until clock signals are routed for the entire integrated circuit. The higher level clock signals can also be strapped or gridded to minimize clock skew.
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Inventors:
SCHERER ALISA M (US)
WEBER FREDERICK (US)
WEBER FREDERICK (US)
Application Number:
PCT/US1997/005422
Publication Date:
March 12, 1998
Filing Date:
April 15, 1997
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INC (US)
International Classes:
G06F17/50; (IPC1-7): G06F17/50; G06F1/10
Foreign References:
| EP0646854A2 | 1995-04-05 | |||
| US5430397A | 1995-07-04 | |||
| US5410491A | 1995-04-25 | |||
| US5012427A | 1991-04-30 |
Other References:
BLAIR G M: "SKEW-FREE CLOCK DISTRIBUTION FOR STANDARD-CELL VLSI DESIGNS", IEE PROCEEDINGS G. ELECTRONIC CIRCUITS & SYSTEMS, vol. 139, no. 2, 1 April 1992 (1992-04-01), pages 265 - 267, XP000300862
MONTUNO D Y ET AL: "A LAYOUT METHODOLOGY FOR THE SYNTHESIS OF HIGH SPEED GLOBAL CLOCK NETS", PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE, BOSTON, MAY 3 - 6, 1992, no. CONF. 14, 3 May 1992 (1992-05-03), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 28.4.1 - 28.4.4, XP000340976
CHO J -D ET AL: "A BUFFER DISTRIBUTION ALGORITHM FOR HIGH-PERFORMANCE CLOCK NET OPTIMIZATION", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 3, no. 1, 1 March 1995 (1995-03-01), pages 84 - 98, XP000500304
MONTUNO D Y ET AL: "A LAYOUT METHODOLOGY FOR THE SYNTHESIS OF HIGH SPEED GLOBAL CLOCK NETS", PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE, BOSTON, MAY 3 - 6, 1992, no. CONF. 14, 3 May 1992 (1992-05-03), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 28.4.1 - 28.4.4, XP000340976
CHO J -D ET AL: "A BUFFER DISTRIBUTION ALGORITHM FOR HIGH-PERFORMANCE CLOCK NET OPTIMIZATION", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 3, no. 1, 1 March 1995 (1995-03-01), pages 84 - 98, XP000500304
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