MATRIX

TECHNICAL FIELD

[0001] The present disclosure is directed generally to methods and apparatus for systematic encoding of data in a communication system, more specifically, to systematic encoding of data using triangular factorization of generator matrix.

BACKGROUND

[0002] In modem digital data transmission (wireless telephony, wireless data transmission, optical disk transmission to a player, music players receiving music data, and so on), a channel encoder can receive a source data block (SDB) and add redundancy to it (by passing the SDB through a transformation) to produce a transmitted code block (TCB) that is better protected against noise in a transmission channel than the SDB from which it is derived. A receiver at the other end of the transmission channel receives a received code block (RCB), which is a version of the TCB corrupted by channel noise and/or distortion, and uses a channel decoder to produce from the RCB a decoded source data block (DSDB). The DSDB is then forwarded to a destination, e.g., a music player, which plays the decoded data as audio, or a storage device, which stores the decoded data as a file.

[0003] A frame error is said to occur if the DSDB is not an identical copy of the SDB. A generally accepted design goal for channel coding is to reduce the frame error rate (FER) to acceptable levels. A second measure of performance for channel coding is the symbol error rate (SER), which is the average number of symbols (coordinates) in which the DSDB differs from the SDB. If the data symbols are binary, the term bit error rate (BER) is used instead of SER. Channel codes that reduce the FER/SER at the cost of too much computation are of little practical use. In prior art, there exist many classes of channel encoders, such as linear block encoders, that are able to achieve an acceptable tradeoff between the FER/SER and complexity of implementation. [0004] One type of encoder for a linear block code is a non-systematic encoder, which encodes the SDB into the TCB by multiplying the SDB by a generator matrix. In non-systematic encoding the SDB is not guaranteed to appear transparently as part of the TCB. An alternative method of encoding is systematic encoding, in which the SDB is guaranteed to appear transparently as part of the TCB. [0005] Systematic encoding provides several advantages over non-systematic encoding. First, having the SDB appear transparently as part of the TCB may be a system requirement, rather than on option. Second, systematic encoding typically improves the SER/BER performance, without causing a degradation in the FER performance. Third, systematic encoding makes it possible to bypass the decoding function when “hard-decisions” on the RCB yield a valid TCB

(where the validity may be verified by checking if certain parity-checks are satisfied). Bypassing the decoder saves energy, which is important in battery operated devices. Fourth, systematic encoding is a necessity in some coding schemes, such as turbo coding [BER1996], where iterative decoding methods are employed that rely on systematic encoding for their operation.

[0006] The present disclosure provides systematic encoding methods for triangular factorization (TF) codes, which is a newer type of linear block code disclosed in [ARI2019b]. TF codes are based on a triangular factorization of a code generator matrix into an outer transform matrix and an inner transform matrix. In one embodiment of TF codes, the outer transform matrix is an invertible upper-triangular (IUT) matrix and the inner transform matrix is an invertible lower-triangular (ILT) matrix. A more specific embodiment of TF codes is polarization adjusted convolutional (PAC) code, also introduced in [ARI2019b] and further discussed in [ARI2019c],

[0007] There are no methods in prior art specifically designed for systematic encoding of TF codes or PAC codes. The present disclosure provides systematic encoding methods for TF codes and their various embodiments, such as PAC codes. The systematic encoding methods provided herein take advantage of the special properties of TF codes and their various embodiments in order to reduce the complexity of systematic encoding.

[0008] In PAC codes, the outer transform matrix is an IUT Toeplitz matrix. The IUT Toeplitz outer transform matrix of a PAC code gives rise to an irregular convolutional code. Convolutional codes are a well-known class of error correcting codes introduced by Elias [ELI1954]. Irregular convolutional codes are a generalization of convolution codes in which the number of source bits accepted into the encoder varies with time in accordance with a polarization phenomenon [ARI2009b]. Systematic encoders for irregular convolutional codes are a novelty of the present disclosure with no counterpart in the prior art.

[0009] In PAC codes, the inner transform matrix a polar transform, which is a type of transform introduced in [ARI2009] in connection with polar codes. Polar codes are a class of codes that are able to achieve channel capacity by low-complexity encoding and decoding algorithms [ARI2009], Systematic encoding of polar codes was first discussed in [ARI2011]. Recursive methods for carrying out systematic encoding of polar codes in a low-complexity manner have been disclosed in [ARI2013], Specific methods that utilize the recursive principles in [ARI2013] for systematic polar encoding appeared in [CHE2016], [SAR2014], [SAR2016], [WAN2014],

[0010] Prior art methods on systematic encoding of polar codes cannot be used directly as part of systematic encoding of PAC codes. Unlike polar codes, the input to the polar transform in PAC coding is not guaranteed to have any frozen symbols. In fact, as explained in [ARI2009c], the main motivation for PAC coding is to avoid fixing any coordinate of the polar transform input so as to avoid loss of channel capacity.

[0011] The present principles provide methods for systematic encoding for any inner transform that can be represented as an ILT matrix, which is a broader class of inner transforms than the class of polar transforms. This is another aspect of the present principles that differs from the prior art on systematic encoding of polar codes. [0012] In addition to systematic encoding, the present principles can be used for shortening of

TF codes and PAC codes. Shortening is a method of adjusting the block length of a given code. Prior art on polar codes, such as [HUA2016], [WAN2014], [ARI2019a], show how shortening and systematic encoding can be implemented. Similar methods can be applied to integrate shortening into the systematic encoding of TF codes in accordance with the present principles. [0013] References:

[ARI2009] E. Arikan, “Channel Polarization: A Method for Constructing Capacity- Achieving Codes for Symmetric Binary-Input Memoryless Channels,” IEEE Transactions on Information Theory, vol. 55, no. 7, pp. 3051-3073, Jul. 2009. [ARI2011] E. Arikan, “Systematic Polar Coding,” IEEE Communications Letters, vol. 15, no. 8, pp. 860-862, Aug. 2011.

[ARI2013] E. Arikan, “Method and system for error correction in transmitting data using low complexity systematic encoder,” U.S. Patent No. 8,347,186 Bl, 01-Jan- 2013.

[ARI2019a] E. Arikan, “Method and system for error correction in transmitting data using low complexity systematic encoder,” U.S. Patent Publication No. 20190165887, 30-05-2019. [ARI2019b] E. Arikan, “Methods and apparatus for error correction coding with triangular factorization of generator matrix,” U.S. Patent Application No. 16453887, 84 pages 26-Jun-2019.

[ARI2019c] E. Ankan, “From sequential decoding to channel polarization and back again,” arXiv: 1908.09594 [cs, IT], 26 Aug. 2019.

[BER1996] C. Berrou and A. Glavieux, “Near optimum error correcting coding and decoding: turbo-codes,” IEEE Transactions on Communications, vol. 44, no. 10, pp. 1261-1271, Oct. 1996.

[CHE2016] G. T. Chen, Z. Zhang, C. Zhong, and L. Zhang, “A Low Complexity Encoding Algorithm for Systematic Polar Codes,” IEEE Communications Letters, vol. 20, no. 7, pp. 1277-1280, Jul. 2016.

[ELI1954] P. Elias, “Error-free Coding,” Transactions of the IRE Professional Group on Information Theory, vol. 4, no. 4, pp. 29-37, Sep. 1954.

[HUA2016] R1- 167209, Polar code design and rate matching, Huawei, Hi Silicon, 3 GPP TSG RAN WG1 Meeting #86, Gothenburg, Sweden, August 22nd - 26th, 2016. [SAR2014] G. Sarkis, P. Giard, A. Vardy, C. Thibeault, and W. J. Gross, “Fast Polar Decoders: Algorithm and Implementation,” IEEE Journal on Selected Areas in Communications, vol. 32, no. 5, pp. 946-957, May 2014.

[SAR2016] G. Sarkis, I. Tal, P. Giard, A. Vardy, C. Thibeault, and W. J. Gross, “Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes,” IEEE Transactions on Communications, vol. 64, no. 7, pp. 2732-2745, Jul. 2016.

[WAN2014] R. Wang and R. Liu, “A Novel Puncturing Scheme for Polar Codes,” IEEE Communications Letters, vol. 18, no. 12, pp. 2081-2084, Dec. 2014. [WAN2016] H. Vangala, Y. Hong, and E. Viterbo, “Efficient Algorithms for Systematic

Polar Encoding,” IEEE Communications Letters, vol. 20, no. 1, pp. 17-20, Jan. 2016.

The above-listed publications are incorporated herein by reference. SUMMARY

[0014] A systematic encoder apparatus for use in a communication system for reliable transfer of a source data block (SDB) is configured for an outer transform matrix and an inner transform matrix. Within the systematic encoder apparatus, an inner encoder is configured to receive the SDB and generate an output constraint block (OCB) as an image of the SDB under an inverse of a submatrix of the inner transform matrix, and an outer encoder is configured to receive a fixed data block (FDB) and the OCB and generate a transform output block (TOB) as an image of a transform input block (TIB) under the outer transform matrix, the TIB containing the FDB transparently in a sub-block of the TIB, the TOB containing the OCB transparently in a sub- block of the TOB. The inner encoder is further configured to receive the TOB and generate a transmitted code block (TCB), the TCB containing the SDB transparently in a sub-block of the TCB. The outer transform matrix is optionally an invertible upper triangular (IUT) matrix. The sub-block of the TOB optionally comprises elements of the TOB whose indices belong to an index set, and the sub-block of the TIB optionally comprises elements of the TIB whose indices belong to a complement of the index set. The inner transform matrix is optionally an invertible lower triangular (ILT) matrix, with the submatrix of the inner transform matrix comprising elements of the inner transform matrix whose row indices belong to the index set and whose column indices belong to the index set, with the sub-block of the TCB comprising elements of the TCB whose indices belong to the index set, and the TCB being an image of the TOB under the inner transform matrix. The outer encoder optionally comprises a feed-forward computation circuit, where the feed-forward computation circuit is configured to receive a sequence of TIB elements and, for each TIB element received, produce a feed-forward value. In embodiments in which the outer transform matrix is an IUT Toeplitz matrix, the feed- forward computation circuit optionally comprises a convolution circuit, with the convolution circuit comprising a plurality of registers, multipliers, and adders and being configured in accordance with an impulse response derived from a first row of the IUT Toeplitz matrix. In some embodiments, the outer encoder is optionally further configured to use the feed-forward value together with a current element of the FDB or a current element of the OCB to generate a next element of the TIB and a next element of the TOB. [0015] A method for use in a communication system for reliable transfer of a source data block

(SDB) employs a systematic encoder apparatus configured for an outer transform matrix and an inner transform matrix. Within the method, an inner encoder is configured to receive the SDB and generate an output constraint block (OCB) as an image of the SDB under an inverse of a submatrix of the inner transform matrix, and an outer encoder is configured to receive a fixed data block (FDB) and the OCB and generate a transform output block (TOB) as an image of a transform input block (TIB) under the outer transform matrix, the TIB containing the FDB transparently in a sub-block of the TIB, the TOB containing the OCB transparently in a sub- block of the TOB. The inner encoder is further configured to receive the TOB and generate a transmitted code block (TCB), the TCB containing the SDB transparently in a sub-block of the TCB. The outer transform matrix is optionally an invertible upper-triangular (IUT) matrix, the sub-block of the TOB optionally comprises elements of the TOB whose indices belong to an index set, and the sub-block of the TIB optionally comprises elements of the TIB whose indices belong to a complement of the index set. In embodiments in which the inner transform matrix is an invertible lower-triangular (ILT) matrix, the submatrix of the inner transform matrix optionally comprises elements of the inner transform matrix whose column indices belong to the index set and whose row indices belong to the index set, the sub-block of the TCB optionally comprising elements of the TCB whose indices belong to the index set, and the TCB being an image of the TOB under the inner transform matrix. The outer encoder optionally comprises a feed-forward computation circuit, with the feed-forward computation circuit configured to receive a sequence of TIB elements and, for each TIB element received, produce a feed-forward value. In embodiments in which the outer transform matrix is an IUT Toeplitz matrix, the feed-forward computation circuit optionally comprises a convolution circuit comprising a plurality of registers, multipliers, and adders, the convolution circuit configured in accordance with an impulse response, the impulse response being obtained from a first row of the IUT Toeplitz matrix. The outer encoder may be further configured to use the feed- forward value together with a current element of the FDB or a current element of the OCB to generate a next element of the TIB and a next element of the TOB.

BRIEF DESCRIPTION OF THE DRAWINGS [0016] FIG. 1 is a block diagram illustrating a communication system 100 in which embodiments of the present principles may be used;

[0017] FIG. 2 is a block diagram illustrating a non-systematic encoder 200; [0018] FIG. 3 is a diagram displaying a systematic encoder 300 according to the present principles;

[0019] FIG. 4A is a flowchart of an IUT encoding method 400 according to the present principles;

[0020] FIG. 4B is a diagram illustrating an exemplary calculation 450 according to the IUT encoding method 400;

[0021] FIG. 5 A is a flowchart illustrating an IUT Toeplitz encoding method 500 according to the present principles;

[0022] FIG. 5B is a diagram illustrating an exemplary calculation 550 according to the IUT Toeplitz encoding method 500; [0023] FIG. 6 is a schematic diagram of a convolution circuit 600;

[0024] FIG. 7 is a schematic diagram of an IUT Toeplitz encoder circuit 700 according to the present principles;

[0025] FIG. 8 is a schematic diagram of a transpose-form convolution circuit 800;

[0026] FIG. 9A is a flowchart of an IUT Toeplitz transpose-form encoder method 900 according to the present principles;

[0027] FIG. 9B is a diagram illustrating an exemplary calculation 950 according to the IUT Toeplitz transpose-form encoding method 900;

[0028] FIG. 10 is a schematic diagram of a transpose-form IUT Toeplitz encoder circuit 1000 according to the present principles; [0029] FIG. 11 illustrates an example wireless network within which systematic encoding of data in error correction coding using triangular factorization of generator matrix may be implemented according to this disclosure;

[0030] FIG. 12 A illustrates an example user equipment network within which systematic encoding of data in error correction coding using triangular factorization of generator matrix may be implemented according to this disclosure; and

[0031] FIG. 12B illustrates an example enhanced NodeB (eNB) network within which systematic encoding of data in error correction coding using triangular factorization of generator matrix may be implemented according to this disclosure. DETAILED DESCRIPTION

[0032] FIGS. 1 through 12B, discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged communication system.

[0033] We will begin by introducing some notation, terminology, and definitions. We will also state some well-known facts about matrices that will be needed in the subsequent discussion of the present principles. [0034] We use script letters, such as A to denote sets. The notation denotes the number of elements in (the cardinality of)

[0035] The symbol denotes the finite field with elements {0,1, ··· , q — 1}.

[0036] The notation α ∈ indicates that a is a row vector α = (α ₁ , α ₂ , ··· , α _n ) with for i = 1,2, ··· , n. For α ∈ {1,2, ··· , n}, denotes the sub-vect or that consists of the elements of a with indices in likewise, denotes the sub-vector that consists of the elements of a with indices in the set where denotes the complement of in (1,2, For example, if m = 8 and ={ 1,2, 3, 5, 8}, then, = ( α ₁ , α ₂ , α ₃ , α ₅ , α ₈ ) and = ( α ₄ , α ₆ , α ₇ ). By convention, we write so that the coordinates of a appear in in the increasing order; thus, whether one specifies a set = (1,2, 3, 5, 8} or = (2, 3, 1,5, 8}, the sub-vector is given by = ( α ₁ , α ₂ , α ₃ , α ₅ , α ₈ ).

[0037] denotes the set of all m-by-n matrices with elements from The notation indicates that A is a matrix with m rows and n columns. Often, we define a matrix by writing it explicitly as a two-dimensional array where denotes the element (entry) in the ith row and jth column of A. For an element α _i,j of a matrix A, we refer to the index i as a row index and the index j as a column index. The element is said to be in the ith row and yth column of the matrix A.

[0038] The notation 0 will denote a matrix all of whose elements are 0. (The dimensions of 0 will be clear from the context.)

[0039] A matrix A is called diagonal if α _i,j =0 for all i ≠ j. The diagonal matrix with Is on the diagonal is called the identity matrix and denoted I.

[0040] A matrix is called invertible if there exists a matrix (called the inverse of A) such that AB = BA = I. If it exists, the inverse of A is denoted A ^-1 . [0041] If a square matrix A ∈ has a form where is a square matrix and where either then det(A) = and hence, A is invertible if and only if are both invertible.

[0042] A matrix A ∈ is called lower-triangular if α _i,j = 0 for all 1 ≤ i < j ≤ n. A matrix A ∈ is called upper-triangular if α _i,j = 0 for all 1 ≤ y < i ≤ n.

[0043] A matrix A ∈ is called upper-triangular Toeplitz if there exists a vector α = (α ₀ , 1 ₂ , ··· , α _n-1 ) ∈ such that A is an upper-triangular matrix with α _i,j = α _j-i for j ≥ i, i.e., if A has the form Such a Toeplitz matrix is invertible if and only if α ₀ ≠ 0. Toeplitz matrices we will consider below will be invertible. If A is upper triangular Toeplitz with first row a = (α ₀ , 1 ₂ , ··· , α _n-1 ) and m ∈ {0,1, ... ,n — 1} is the largest index such that a _m ≠ 0, then we refer to the initial segment (α ₀ , 1 ₂ , ··· , α _m ) of a as an impulse response and say that the upper-triangular Toeplitz matrix A is defined by the impulse response (α ₀ , 1 ₂ , ··· , α _m ). [0044] The Kronecker product of two matrices A ∈ and B ∈ is defined as the matrix

The nth Kronecker power of a matrix A is defined inductively as

[0045] In the following, the term “transform” is used in the sense of a linear mapping from one vector space to another vector space. Matrices are used to represent transforms in specific forms with respect to specific basis vectors. The term “transform matrix A” will refer to a particular realization of a transform in the form of a specific matrix A. When two vectors a and b are related by a transform relationship b = aA we say that b is the image of a under the transform matrix A. [0046] In the following description, we use row vectors to represent signals (such as source data blocks and coded data blocks); and, a multiplication involving a vector a and a matrix A will always have the form aA (a left multiplication). It is clear that the present principles can be implemented readily using column vectors instead of row vectors and right-multiplications instead of left-multiplications. All such variations of the methods presented below that are based on different representations of vectors spaces or the matrix representations of the transforms acting on such vector spaces fall within the scope of the present principles.

[0047] A matrix P ∈ is called a permutation matrix if all entries of P are either 0 or 1 and P has exactly one 1 in each row and one 1 in each column. We will say that two matrices A ∈ and B ∈ are permutation-equivalent if there exist permutation matrices P ∈ and Q ∈ such that A = PBQ. Permutation-equivalent matrices differ from each other only by a permutation of the rows and columns, which in a communication system corresponds to receiving source data or transmitting coded data in a different (permuted) order. In the following, the present principles will be described using matrix representations that are most convenient for purposes of explaining the essential ideas; however, the person skilled in the art will have no difficulty in applying the present principles to situations where it may be more desirable to use alternative matrix representations.

[0048] The primary motivation for the present principles is to provide systematic encoding methods that can be useful in connection with TF codes and, more specifically, PAC codes, a subclass of TF codes. TF codes are a class of linear block codes whose generator matrix is factored into triangular matrices (or matrices that are permutation-equivalent to triangular matrices) for purposes of encoding and decoding. Before discussing the details of the present principles, we wish to restate the motivation for systematic encoding in more general terms, which will help better understand the benefits and utility of the present principles.

[0049] A channel encoder is called systematic if it encodes source data into a codeword in such a way that the source data appears transparently as part of codeword. For a given linear block code, it is possible to encode the source data either in systematic form or non-systematic form. Systematic encoding provides several advantages over non-systematic encoding. First, systematic encoding provides a better bit/symbol error rate (BER/SER) performance than non- systematic encoding. Often, this alone is a sufficient reason for preferring systematic encoding. Second, in many application scenarios, having the source data appear transparently as part of the codeword is a system requirement, rather than on option. Third, systematic encoding makes it possible to complete the decoding immediately when “hard-decisions” on the received codeword yields a valid codeword. Fourth, systematic encoding may be a necessity in various concatenated coding schemes where two or more decoders exchange information over systematically encoded data bits (as in turbo coding).

[0050] Despite the advantages of systematic encoding, there is no systematic encoding method in the prior art specifically targeting TF codes. The present disclosure fills this gap in the prior art by providing systematic encoding methods for TF codes that take advantage of the special structure of TF codes. Details of the present principles and their specific embodiments are described below with reference to FIGS. 1 through 12B.

[0051] FIG. 1 is a block diagram illustrating a communication system 100, in which embodiments of the present principles may be used. The communication system 100 comprises an encoder 110 located at a transmitter side, a channel 120 connecting the transmitter to a receiver, and a decoder 130 at the receiver side.

[0052] The communication system 100 receives a source data block (SDB) d from a source and delivers it as a decoded source data block (DSDB) d to a destination. (The source and the destination are not shown in the figure since they are regarded as given and fall outside the scope of the present principles.) A frame error is said to occur when the DSDB does not match the SDB d exactly, i.e., when ≠ d. A primary performance criterion for the communication system 100 is the frame error rate (FER), defined as the probability Pr ( ≠ d). It is in general preferable to have a communication system 100 with as small a FER as feasible. The encoder 110 and the decoder 130 implement a channel coding scheme in order to reduce the FER at the expense of increased channel bandwidth, equipment cost, and latency. Details of channel coding operation are as follows.

[0053] The encoder 110 receives the SDB d and encodes it into a transmitted code block (TCB) x. The channel 120 comprises a channel input and a channel output. The encoder 110 applies the TCB x to the channel input. The channel responds to the TCB x applied to the channel input by producing a received code block (RCB) y at the channel output. The decoder 130 receives the RCB y from the channel output and processes the RCB y to produce the DSDB d. [0054] It will be apparent to those skilled in the art that a typical communication system comprises many functional blocks (such as modulators and demodulators, digital-to-analog and analog-to-digital converters, amplifiers, transmit and receive antennas, signal acquisition and synchronization circuitry) that are essential for transmitting and receiving signals across the channel 120. From the viewpoint of the present principles, such functional blocks are regarded as part of the channel 120 and fall outside the scope of the present principles. [0055] The present disclosure is mainly about specific implementations of the encoder 110. Some notational conventions and terminology about the encoding operation are as follows. Throughout the following, we will represent the SDB and the TCB as row vectors d = (d ₁ , d ₂ , ··· , d _k ) and x = (x ₁ , x ₂ , ··· , x _N ), respectively, where K is a source block length and N is a code block length. The mapping from the SDB d to the TCB x is referred to as a code. Throughout, we will consider codes such that both d and x are vectors over a common finite field The ratio R = K/N is called the code rate and we will assume that the code rate R is a number satisfying 0 ≤ R ≤ 1.

[0056] The encoder 110 is called systematic if the SDB d appears transparently as part of the TCB x. The present principles are concerned with systematic encoding of TF codes. TF codes are a type of linear block code that is based on a triangular factorization of an invertible transform matrix G ∈ (a generator matrix) into a product of an invertible upper-triangular (IUT) matrix U ∈ and an invertible lower-triangular (ILT) matrix L ∈ . We refer to U as the outer transform matrix and L as the inner transform matrix. A preferred embodiment of TF codes is PAC codes for which the outer transform matrix is an IUT Toeplitz matrix and the inner transform matrix is a polar transform matrix (a Kronecker power of a kernel matrix). The prior art on encoding of TF codes is based on non-systematic encoding.

[0057] FIG. 2 is a block diagram illustrating a non-systematic encoder 200 for a TF code, where the TF code is as described in [ARI2019b], As in the case of the encoder 110 of FIG. 1, the overall function of the non-systematic encoder 200 is to receive the SDB d ∈ from a source and encode it into the TCB x ∈ where the TCB x is a codeword from the TF code. [0058] The non-systematic encoder 200 comprises a data inserter 211, an outer transform 212, and an inner transform 213. The encoding operation for the non-systematic encoder 200 is configured according to four parameters is an outer transform matrix, is an inner transform matrix, is an index set (of size K), and a ∈ is a fixed data block (FDB). It is assumed that the matrix representations of the outer and inner transforms are such that U is an IUT matrix and L is an ILT matrix.

[0059] The data inserter 211 receives the SDB d ∈ and generates a transform input block (TIB) so that where denotes the complement of the index set (the complement being with respect to the universal set {1,2, ··· , N }). The outer transform 212 receives the TIB and generates a transform output block TOB w ∈ so that w = vU. The inner transform 213 receives the TOB w and generates the TCB x ∈ so that x = wL. In other words, the TOB is the image of the TIB under the outer transform matrix and the TCB is the image of the TOB under the inner transform matrix.

[0060] The present principles provide solutions to the systematic encoding problem for TF codes. Before we begin describing specific methods, it will be useful to discuss the mathematical essence of the systematic encoding problem for TF codes to understand if and under what conditions a solution exists.

[0061] In general, the systematic encoding of a TF code can be specified by five parameters is an outer transform matrix, is an inner transform matrix, is a first index set (of size K), s a second index set (of size N — K), and a ∈ is a FDB. We assume that the matrix representations of the outer and inner transforms are such that U is an IUT matrix and L is an ILT matrix.

[0062] A systematic encoder with parameters receives the SDB d E and generates a pair of vectors and x ∈ so that are satisfied. To analyze if such a pair of vectors v and x exists, let G = UL denote the generator matrix for the TF code and rewrite the equation and Substituting = d and in accordance with systematic coding constraints, and solving for we obtain a formal solution as where we have defined This solution is valid if and only if the submatrix of the generator matrix G is invertible. A sufficient condition for being invertible is given as follows.

[0063] Proposition 1. If then can be made invertible by choosing as the complement of in {1,2, ... ,N}.

[0064] Proof. Suppose and set Then, equals which in turn equals Using the assumption we obtain Since are principal submatrices of triangular matrices, they are invertible. Since the product of two invertible matrices is invertible, is invertible.

[0065] If and are selected as in Proposition 1, the systematic encoding equations become

30 In implementing such a systematic encoder, one can pre-compute the matrix E ∈ and the vector e ∈ and configure the systematic encoder accordingly.

[0066] We have shown that under the conditions of Proposition 1, the systematic encoding problem is feasible. However, a direct solution of the systematic encoding problem by computing is far from being practical. Computing the product dE directly involves 0((N — K) ² ) arithmetic operations (additions and multiplications in the field which is typically prohibitively complex for many practical applications.

[0067] It is an object of the present principles to reduce the complexity of systematic encoding of TF codes. To this end, the present principles exploit the triangular factorization of the generator matrix G into U and L in solving the systematic encoding problem. We begin by describing a general framework for the application of the present principles. In describing the general framework, it will be sufficient to use four parameters instead of by restricting attention to the cases where is the complement of in

{1,2, — ,N}. [0068] FIG. 3 is a block diagram illustrating a systematic encoder 300 for a TF code in accordance with the present principles. As in the case of the non-systematic encoder 200, the TF code for the systematic encoder 300 is characterized by a set of four parameters where U ∈ is an outer transform matrix, L ∈ is an inner transform matrix, {1,2, — ,N} is an index set of size K, and a ∈ is a fixed data block (FDB). It is assumed that the matrix representations of the outer and inner transforms are such that U is an IUT matrix and L is an ILT matrix. Further, it is assumed that the parameters are chosen so that

[0069] The systematic encoder 300 comprises an inner encoder 301 and an outer encoder 302 and operates according to systematic coding constraints 320. The operation of the systematic encoder 300 will be described by dividing the operation into three steps.

[0070] In the first step, the inner encoder 301 receives the SDB d ∈ 311 and generates an outer constraint block (OCB) γ ∈ 312 such that In other words, the OCB

312 γ is generated as the image of the SDB d 311 under the inverse of the submatrix of the inner transform matrix. As already pointed out above, is invertible due to the assumption that

[0071] In the second step, the outer encoder 302 receives the FDB a 313 and the OCB γ 312 and generates a TIB 314 and a TOB w 315 such that an outer transform constraint w = 321, an OCB constraint a and an FDB constraint are satisfied. In the third step, the inner encoder 301 receives the TOB w 315 and generates the TCB x 316 so that an inner transform constraint x = wL 324 is satisfied. We now provide a proof that at the end of the third step we obtain systematic encoding in the sense that the TCB x 316 satisfies a systematic coding constraint = d 325.

[0072] We observe that the inner transform operation x = wL in the third step contains a subset of equations Since (by assumption) and (by the second step), the operation in the third step is equivalent to Substituting γ = from the first step, we see that the third step yields This argument shows that the systematic encoder 300 is indeed systematic.

[0073] The preceding argument also reveals the crucial role of the condition = 0 in relation to the present principles. The introduction of = 0 as a condition on the choice of code parameters and the resulting decomposition of the systematic encoding of TF codes into three smaller sub-problems is an important novel aspect of the present principles. We now discuss how each step can be implemented and assess their complexity.

[0074] The first step of the systematic encoder 300 involves computing the OCB γ = Since is an ILT matrix (a property it inherits from L) and since the inverse of an ILT matrix is ILT, the matrix is ILT. If L has no structure other than being ILT, then a direct computation of γ = may be the only option. In that case, the matrix can be pre-computed and the inner encoder 301 can be pre-configured with knowledge of The storage complexity of is 0(K ² ) and the arithmetic complexity of computing γ = is also 0(K ² ). As already pointed out, a complexity 0(K ² ) is often prohibitive for many applications. Fortunately, when we consider special cases of TF coding, such as PAC coding, the complexity of the present principles is reduced to practical levels.

[0075] An important special case of TF codes is PAC codes, in which case the inner transform matrix L has the form of a Kronecker power, e.g., L = with and n = log ₂ N.

The inverse of such an inner transform L is itself, L ^-1 = L, which together with the condition implies that In this case, a preferred method of computing γ = is to prepare a vector x' by setting = d and = 0, then compute w' = and finally extract γ from w' by setting γ = The transform step w' = x'L can be implemented by exploiting the recursive structure of L, resulting in a complexity of 0(N log N), which may be significantly better than the complexity 0(K ² ) of computing γ = directly. (The problem with direct computation is that the recursive structure of L may get lost when we consider the submatrix

[0076] The person skilled in the art will recognize that the above method of computing the OCB γ by exploiting the recursive structure of the polar transform exploits the prior art on systematic encoding of polar codes. It is worth pointing out that when L = the condition that we imposed on the systematic encoder 300 is usually satisfied by the preferred choice of the set for PAC codes. In other words, the condition does not necessarily imply a loss of optimality in the construction of PAC codes.

[0077] The comments on the complexity of the first step of the systematic encoder 300 are valid to a great extent for the complexity of the third step. For a general ILT matrix L, the complexity of computing x = wL is 0(N ² ). On the other hand, for a PAC code with L = the complexity of the third step is reduced to 0(N log N), which is the complexity of encoding a polar code. Thus, the first and third steps of the systematic encoder 250, which are carried out by the inner encoder 301, have a combined complexity 0(N log N) in the case of PAC codes, which are the codes of main interest for the present principles. [0078] We now turn attention to the complexity of the outer encoder 302, which carries out the second step of the systematic encoder 300.

[0079] Proposition 2. For any instance of parameters there exist realizations of the outer encoder 302 that solve the outer encoding problem (find the unique TIB 314 and TOB w 315 pair that satisfy the constraints 321, 322, and 323) using 0(N ² ) arithmetic operations (additions and multiplications in lf U is Toeplitz (in addition to being IUT) with an impulse response g = (g ₀ ,g ₁ , ,9 _m ) ∈ then there exist realizations of the outer encoder 302 that solve the outer encoding problem using 0(mN) arithmetic operations.

[0080] Proof. We will prove the claim by giving an algorithm that computes the solution. Let U _i,j denote the (i,j)th element of U. Since U is upper-triangular by assumption, U _i,j = 0 for i > j. Thus, the system of equations w = vU can be written as and more generally, These equations can be solved sequentially. The first equation is and we have two cases, either In the first case, in the second case, where is the multiplicative inverse of Note that, since U is invertible by assumption, and the multiplicative inverse exists for every i. As an induction hypothesis, suppose that has been determined for each h = 1,2, ··· , i — 1, and consider the next pair . Define a feed-forward variable s + Note that the value of the feed-forward variable s becomes available at the end of step i — 1 of the above algorithm and is available for computing the pair at step i. One of the two unknowns is also known at step i since either i ∈ A and for some element of the FDB a or for some element of the OCB y. In either case, the remaining element of the pair can be obtained from the relation Specifically, if i ∈ then alternatively, if i e , then = This completes the proof that the solution (v,w) exists and is unique. [0081] The complexity of the above procedure is dominated by the computation of the feed- forward variable s. There are N feed-forward variable calculations, each requiring at most N multiplication and N — 1 addition operations. So, the overall complexity is 0(N ² ). If U is IUT Toeplitz with an impulse response g = then with the notational convention that The feed- forward variable is given by which requires at most m multiplications and m — 1 additions. Thus, the complexity of computing the feed-forward variable s is reduced from 0(N) to 0(m), and the overall complexity becomes 0(mN ). This completes the proof of Proposition 2.

[0082] The procedure given in the proof of Proposition 2 forms the basis of the outer encoder 302 in accordance with the present principles. We will now give a more precise algorithmic description of this procedure.

[0083] FIG. 4A is a flowchart of an IUT encoding method 400 for implementing the outer encoder 302 in accordance with the present principles. The IUT encoding method 400 (hereafter, the method 400) is configured for operation with the four parameters which have been defined above in connection with the outer encoder 302. The method 400 solves the outer encoding problem by computing a TIB v 314 and TOB w 315 pair satisfying the constraints 321, 322 and 323. The method 400 begins operations in a start step 401 and moves into an OCB input step 402 when a new OCB γ ∈ 312 becomes available for encoding. In the OCB input step 402, the method 400 fetches the OCB γ 312 from outside, e.g., from the inner encoder 301.

[0084] Following the OCB input step 402, the method 400 moves to a variable initialization step 403 and initializes a loop counter i, an FDB constraint counter j, and an OCB constraint counter k. The loop counter i counts the number of times the method 400 executes a main loop, where the main loop begins with the execution of the loop counter increment step 404. The initial value of the loop counter i is set to 0 in the step 403. The FDB constraint counter j is initialized as j ← min {1, N — K }, and at any moment during the operation of the method 400, the counter j indicates which constraint among the N — K FDB constraints 323 is going to be processed next by the method 400. If the number of FDB constraints 323 is 0, i.e., if N — K = 0, then the FDB constraint counter j is set to 0 in the step 403 and remains 0 throughout the rest of the operation of the method 400. The OCB constraint counter k is initialized as k «- min {1, K}, and at any moment during the operation of the method 400, the counter k indicates which constraint among the K OCB constraints 322 is going to be processed next by the method 400. If the number of OCB constraints is 0, i.e., if K = 0, then the OCB constraint counter k is set to 0 in the step 403 and remains 0 throughout the rest of the operation of the method 400. [0085] Following the variable initialization step 403, the method 400 executes a loop counter increment step 404 by incrementing the loop counter i by 1. The step 404 marks the beginning of the main loop for the method 400. The main loop is executed N times. During the ith execution of the main loop, the method 400 processes a feed-forward value s together with a current element α _j of the FDB a 313 or a current element γ _k of the OCB γ 312 to a generate a next element V _i of the TIB v 314 and a next element w _i of the TOB w 315. The details of the main loop are as follows.

[0086] The method 400 enters a loop counter check step 405 following the step 404 and checks if the loop counter i is still less than or equal to its final value N. If a result of the check is NO, the method 400 moves into an exit step 406. (If a next OCB is available for encoding, the exit step 406 may be bypassed and the method 400 may proceed to the processing the next OCB by reentering the OCB input step 402.) If the result of the check in the step 405 is YES, the method 400 moves into a feed-forward computation step 407 and computes a feed-forward value s = If i = 1, the feed-forward value is set to zero, s = 0. The next step from the step

407 is a constraint-type check step 408.

[0087] In the constraint-type check step 408, a check is made to see if the next constraint to be processed is an FDB constraint 323 (indicated by b _i = 0) or an OCB constraint 322 (indicated by b _i = 1). Here, b = (b ₁ , b ₂ , — ,b _N ) is a constraint type indicator (CTI) derived from the index set so that b _i = 1 if i ∈ and b _i = 0 if In other words, the CTI b is the indicator vector of the index set Checking whether i ∈ by looking at the ith coordinate of the CTI b is more efficient than searching the set to see if it contains i. Using a Boolean vector for such purpose is especially useful in the hardware implementations discussed below. [0088] If a result of the constraint-type check step 408 is NO, then the method 400 executes an FDB constraint processing step 409 by setting w _i = a _j u _i,i + s and v _i = a _j . The step 409 is always followed by a step 411, in which the FDB constraint counter j is updated as j ← min {j + 1,N — K}. At the end of the step 411, the FDB constraint counter j points at the next FDB constraint 323 to be processed if there is any left; if all FDB constraints 323 have been processed, the value of j remains as N — K .

[0089] If the result of the constraint-type check step 408 is YES, then the method 400 executes an OCB constraint processing step 410 by setting w _i = γ _k and v _i = ( γ _k — s)(u _i,i ) ^-1 . The step 410 is always followed by a step 412, in which the OCB constraint counter k is updated as k «- min {k + 1, K}. At the end of the step 412, the OCB constraint 322 counter k points at the next OCB constraint to be processed if there is any left; if all OCB constraints 322 have been processed, the value of k remains as K.

[0090] The steps 411 and 412 are both followed by an output step 413, in which the method 400 outputs the ith element w _i of the TOB w 315. Optionally, the method 400 may output the ith element v _i of the TIB v 314 as part of the output step 413.

[0091] Following the output step 413, the method 400 loops back to the step 404 and continues operating as described above.

[0092] It is possible to simplify the method 400 somewhat by eliminating all “min” operations and using j ← 1 and k ← 1 instead of j ← min {1, N - K} and k ← min {1, K} in the step 403, and j ← j + 1 and k ← 1 instead of j ← min {j + 1, N — K } and k ← min {k + 1, K} in the steps 411 and 412. This simplification allows j or k to take on out-of-range values, but an inspection of the method 400 reveals that the ΊΊΒ v 314 and the TOB w 315 will still be computed correctly. This type of simplification is also valid in the more specific embodiments of the method 400 as discussed below in connection with FIGS. 5 and 9.

[0093] Another simplification takes place in the implementation of the method 400 when the diagonal elements of the IUT matrix U are all 1 (the multiplicative identity in ), then the operation w _i = a _j u _i,i + s in the step 409 simplifies to w _i = α _j + s and the operation v _i = ( γ _k — s)(u _i,i ) ^-1 in the step 410 simplifies to and v _i = γ _k — s. In particular, when the transform operations are over the binary field = {0,1}, all multiplication and division operations in the method 400 can be replaced with simpler operations, which reduces the complexity of implementing the outer encoder 302 both in hardware and software.

[0094] FIG. 4B is a diagram illustrating an exemplary calculation 450 according to the method 400. The exemplary calculation 450 uses an exemplary IUT matrix U 452, an exemplary CTI b 453, an exemplary FDB a 454, and an exemplary OCB γ 455. The exemplary calculation

450 is assumed to be over the binary field By inspecting the exemplary parameters 453 and 454, we understand that the length parameters in this exemplary calculation are N = 8 and K =

3. Details of the exemplary calculation 450 are shown in a table 451. The ith row of the table

451 lists values of the variables of the method 400, where the values are sampled immediately after completion of the FDB constraint processing step 409 or the OCB constraint processing step 410. At the end of the exemplary calculation, an exemplary TIB v 456 and an exemplary TOB w 457 are obtained. It can be verified easily that the exemplary variables 452 through 457 satisfy the transform constraint w = vU 321, the FDB constraint = a 323, and the OCB constraint = γ 322 with = {4,6,8} and = {1,2, 3, 5, 7}.

[0095] Although the method 400 provides a solution to the outer encoding problem, it has complexity 0(N ² ) for a general LUT matrix U ∈ which is often prohibitive in practice. The complexity can be reduced if U has a special structure. A particularly important case is when U is Toeplitz in addition to being IUT, as in the case of PAC codes. We now turn our focus to this important special case.

[0096] FIG. 5A is a flowchart illustrating an IUT Toeplitz encoding method 500 for implementing the outer encoder 302 in accordance with the present principles. The IUT Toeplitz encoding method 500 (hereafter, the method 500) is a special instance of the method 400 adapted to the case where the outer transform matrix U is an IUT Toeplitz matrix. In accordance with the IUT Toeplitz assumption, the method 500 is configured for an impulse response with and where the impulse response g is derived from the first row of the outer transform matrix U ∈ . [0097] The method 500 begins operations in a start step 501 and moves into an OCB input step

502 when the OCB γ e 312 becomes available for encoding. In the OCB input step 502, the method 500 fetches the OCB γ 312 from outside, e.g., from the inner encoder 301. [0098] Following the OCB input step 502, the method 500 moves to a variable initialization step 503 and initializes a loop counter i, an FDB constraint counter j, an OCB constraint counter k, and initializes a register array r = (r ₁ , ··· , r _m ) by setting r _i ← 0 for i = 1, ··· , m. The counters i, j, and k perform the same counting functions as in the case of the method 400. The role of the register array r will become clear in the following discussion.

[0099] As in the case of the method 400, the initialization and updates of the counters j and k can be simplified by removing the “min” operation in the same way as described for the method 400. Such a simplification does not affect the final values of the TIB v 314 and TOB w 315 calculated by the method 500. [0100] Following the variable initialization step 503, the method 500 executes a loop counter increment step 504 by incrementing the loop counter i by 1. The step 504 marks the beginning of a main loop for the method 500. The main loop is executed N times each time the method 500 is invoked. During the ith execution of the main loop, the method 500 processes a feed- forward value s together with a current element a _j . of the FDB a 313 or a current element γ _k of the OCB γ 312 to a generate a next element v _i of the TIB v 314 and a next element w _i of the TOB w 315. The details of the main loop are as follows.

[0101] The method 500 enters a loop counter check step 505 following the step 504 and checks if the loop counter i is still less than or equal to its final value N. If a result of the check is NO, the method 500 moves into an exit step 506. (If a next OCB 312 is available for encoding, the exit step 506 may be bypassed and the method 500 may proceed to the encoding of the next

OCB by reentering the OCB input step 502.) If the result of the check in the step 505 is YES, the method 500 moves into a feed-forward computation step 507, computes a feed-forward value s = , and moves into a constraint-type check step 508.

[0102] In the constraint-type check step 508, a check is made to see if the next constraint to be processed is an FDB constraint 323 (indicated by b _i = 0) or an OCB constraint 322 (indicated by b _i = 1).

[0103] If a result of the constraint-type check step 508 is NO, then the method 500 executes an FDB constraint processing step 509 by setting w _i = α _j g ₀ + s and v _i = α _j . The step 509 is followed by a step 511, in which the FDB constraint counter j is updated as j ← min {j + 1 ,N — K}. At the end of the step 511, the FDB constraint counter j points at the next FDB constraint 323 to be processed if there is any left; if all FDB constraints 323 have been processed, the value of j remains as N — K . [0104] If the result of the constraint-type check step 508 is YES, then the method 500 executes an OCB constraint processing step 510 by setting w _i = γ _k and v _i = ( γ _k — s)(g ₀ ) ^-1 · The step 510 is followed by a step 512, in which the OCB constraint counter k is updated as k ← min { k + 1, K}. At the end of the step 512, the OCB constraint counter k points at the next OCB constraint 322 to be processed if there is any left; if all OCB constraints 322 have been processed, the value of k remains as K.

[0105] The steps 511 and 512 are both followed by a register update step 513, in which the contents of the register array r are shifted one place to the right by setting r _h ← r _h-1 in the order h = m, m - 1, ··· ,2, followed by r ₁ ← v _i . [0106] The step 513 is followed by an output step 514, in which the method 500 outputs the ith element vv _i of the TOB w 315. Optionally, the method 500 may output the ith element v _i of the TIB v 314 as part of the output step 514.

[0107] Following the output step 514, the method 500 loops back to the step 504 and continues operating as described above. [0108] The complexity of the method 500 is 0(mN), which is typically significantly smaller than the complexity 0(N ² ) for the method 400. For example, in the case of PAC codes, the parameter m is usually a fixed small integer while N may be arbitrarily large.

[0109] The main benefit of the present principles becomes visible at this point. Thanks to the decomposition of the systematic encoding problem for TF codes into three steps, an outer encoder has been obtained that can take full advantage of a Toeplitz form of the outer transform matrix and solve the outer encoding problem at complexity 0(mN ). This complexity compares very favorably with the complexity 0(N ² ) of a general systematic encoder for TF codes. In particular, the direct method of systematic encoding of TF codes, as discussed above, would compute the TCB x by setting = d and = dE + e. The direct method does not exploit any Toeplitz structure of the outer transform matrix and suffers from 0(N ² ) complexity, while the present principles reduce the complexity to 0(mN).

[0110] It is possible to simplify the method 500 by eliminating all “min” operations as in the case of the method 400. As in the case of the method 400, another simplification takes place in the implementation of the method 500 when the diagonal elements of the IUT transform U are all 1 (the multiplicative identity in or when the transform operations are over the binary field = {0,1}. [0111] FIG. SB is a diagram illustrating in tabular form an exemplary calculation 550 according to the method 500. The exemplary calculation 550 uses an exemplary IUT Toeplitz matrix U 552, an exemplary CTI b 553, an exemplary FDB a 554, and an exemplary OCB y 555. The exemplary calculation 550 is assumed to be over the binary field By inspecting the exemplary parameters 553 and 554, we understand that the length parameters in the exemplary calculation 550 are N = 8 and K = 3. Details of the exemplary calculation 550 are shown in a table 551. The ith row of the table 551 lists values of the variables of the method 500, where the values are sampled immediately after completion of the FDB constraint processing step 509 or the OCB constraint processing step 510. At the end of the exemplary calculation 550, an exemplary TIB v 556 and an exemplary TOB w 557 are obtained. It can be verified easily that the exemplary variables 552 through 557 satisfy the transform constraint w = vU 321, the FDB constraint = a 323, and the OCB constraint = γ 322 with {4,6,8} and = {1,2, 3, 5, 7}.

[0112] We now turn our attention to providing an efficient hardware implementation of the method 500. The most computationally intensive step of the method 500 is the feed-forward computation step 507. This step can be carried out using well-known convolution circuits. To discuss such circuits, it will be convenient to use a polynomial representation of the Toeplitz matrix operations.

[0113] Proposition 3. Let U ∈ be an upper-triangular Toeplitz matrix with first row g = be an arbitrary vector, and let w = be defined by the product w = vU. Define the polynomials Then, the relation w = vU can be expressed in terms of polynomials as w(D) = mod D ^N . [0114] Proof. Suppose w = vU. Then, by definition of matrix multiplication, we have w _i = Since U is upper-triangular and Toeplitz, we have if otherwise. Thus, We observe that, for 1 ≤ i ≤ N, the term w _i is the coefficient of D ^i-1 in the product v(D)g(D). In other words, w(D) equals v(D)g(D) mod D ^N as claimed. [0115] The person skilled in the art of digital signal processing will recognize that the relationship w(D) = v(D)g(D) mod D ^N , or equivalently the equations define a convolution relationship between the TIB v 314 and the TOB w 315. Specifically, the TOB w 315 may be regarded as the first N terms produced by a linear time- invariant filter with an impulse response g = (g ₀ , g ₁ , ··· , g _N-1 ) when the TIB v 314 is applied as the input. There are many circuits for realization of such filters in hardware, which can be used in the present context to implement the method 500. In order to minimize the hardware complexity, we will henceforth omit the trailing zeros of the impulse response g = (g ₀ , g ₁ , ··· , g _N-1 ) and write g = (g ₀ , g ₁ , ... , g _m ) where m is the largest integer i in the range 0 ≤ i ≤ N — 1 such that gi ≠ 0. In circuit implementations that are given below, the parameter m will be the number of register stages that are required. In typical applications of the present principles, the parameter m will be fixed as some number significantly smaller than the code block length N.

[0116] FIG. 6 is a schematic diagram of a convolution circuit 600. The convolution circuit 600 is configured for computing the product w(D) = v(D)g(D ) mod D ^N in Proposition 3, wherein g(D) = g ₀ + g ₁ D + ... + g _m D ^m is fixed polynomial, v(D) = v ₁ + v ₂ D + ... + v _N D ^N-1 and w(D) = w ₁ + w ₂ D + ... + w _N D ^N~1 are an input polynomial and an output polynomial, respectively.

[0117] The convolution circuit 600 comprises an input port 601, an output port 602, registers 611-613, multipliers 621-625, and adders 631-634. The convolution circuit 600 receives the coefficients v _i of the input polynomial v(D) at the input port 601 in the natural order v ₁ (first), v ₂ , ···, v _N , and computes and sends out the coefficients w _i of the output polynomial w(D) at the output port 602 in the order w ₁ (first), w ₂ , ···, w _N . Prior to receiving the first input v ₁ , the contents of the registers r ₁ , r ₁ , ··· , r _m 611-613 are initialized to 0. For i = 1,2, ··· , N, the circuit enforces the relation w _i = wherein v _i-j is interpreted as 0 for i — j < 1. Thus, the first output coefficient w ₁ is given by w ₁ = g ₀ v ₁ ; the second output coefficient by w ₂ = g ₀ v ₂ + g ₁ v ₁ ; and the final output coefficient by w _N = g ₀ v _N + g ₁ v _N-1 + ... + g _m v _N-m . It takes N time units for the convolution circuit 600 to complete its operation. The convolution circuit 600 is capable of computing the product w(D) = g(D)v(D) mod D ^N in any field. If a coefficient gi of the fixed polynomial g(D) is zero, it is clear that the corresponding multiplier and adder circuits can be eliminated so as to simplify the circuit. For example, if g ₁ = 0, then the multiplier 621 and the adder 631 can be eliminated. A further simplification takes place when g _i = 11 (the multiplicative identity) in which case the corresponding multiplier can be eliminated. In particular, when the field of operations is the binary field, there is no need for any multipliers and the addition operations can be implemented using logic exclusive OR (XOR) gates. The convolution circuit 600 and its various implementations in digital logic are well known in the prior art.

[0118] FIG. 7 is a schematic diagram of an IUT Toeplitz encoder circuit 700 for implementing the outer encoder 302 in accordance with the present principles. The IUT Toeplitz encoder circuit 700 is an implementation of the method 500 in hardware using commonly available digital logic elements, such as adders, multipliers, random access memory, shift registers, and multiplexers. The circuit 700 comprises an FDB input port 701 for receiving elements α _j of the FDB a 313, an OCB input port 702 for receiving elements γ _k of the at the OCB γ 312, a CTI input port 703 for receiving elements b _i of the CTI b, a TOB output port 704 for sending out elements w _i of the TOB w 315, and a TIB output port 705 for sending out elements v _i of the TIB v 314.

[0119] The circuit 700 further comprises a feed-forward computation circuit 710, a first multiplexer MUX1720, and a second multiplexer MUX2730. The circuit 700 follows the steps of the method 500. Certain steps in the implementation of the method 500 are not shown explicitly in the circuit 700 in order not to clutter the circuit 700 with unnecessary detail. In particular, clock circuitry, control logic, and storage elements for holding the FDB a 313, the OCB γ 312, and the CTI b are not shown in the circuit 700. Logic circuits for initialization and incrementing of the counters j, k, i, which are used as memory addresses for fetching the elements α _j , γ _k , and b _i from their respective memory locations, are also not shown in the circuit 700. The person skilled in the art of digital circuit design will have no difficulty is completing such routine details of the control logic for the circuit 700 so as to obtain a full implementation of the method 500.

[0120] The feed-forward computation circuit 710 is inspired by the convolution circuit 600. The function of the feed-forward computation circuit 710 is to execute the step 507 of the method 500. The feed-forward computation circuit 710 receives elements v _i of the TIB v 314 as input and generates the feed-forward value s = as output. The contents of the registers inside the feed-forward computation circuit 710 are initialized to 0 at the start of the operation as in the step 503 of the method 500.

[0121] The multiplexers MLJX1720 and MUX2730 are regular 2-to-1 multiplexers commonly employed in digital circuits. To be specific, the 2-to-1 multiplexer employed here has two input ports INI and IN0, a control port SEL, and an output port OUT. When the signal at the control port SEL is a logical 1 (respectively, logical 0), the 2-to-1 multiplexer forwards the logic signal at the input port INI (respectively, input port INO) to the output port OUT.

[0122] The constraint-type check step 508 is implemented by connecting the CTI input port 703 to the SEL inputs 723 and 733 of the multiplexers MLJX1 720 and MUX2 730, respectively. [0123] When b _i = 0, the first multiplexer MLJX1 720 routes the signal a _j g ₀ + s from the input port INO 722 to the output port OUT 724 and the second multiplexer MUX2 730 routes the signal a _j . from the input port INO 732 to the output port OUT 734. Thus, when b _i = 0, the signal at the TOB output port 704 is obtained as w _i = a _j g ₀ + s and the signal at the TIB output port 705 is obtained as = a _j , as required by the step 509 of the method 500. When b _i = 0, the control logic updates the FDB constraint counter j in accordance with the step 511 of the method 500.

[0124] When b _i = 1, the first multiplexer MLJX1 720 routes the signal γ _k from the input port INI 721 to the output port OUT 724 and the second multiplexer MUX2730 routes the signal (γ _k — s)(g ₀ ) ^-1 from the input port INI 731 to the output port OUT 734. Thus, when b _i = 1, the signal at the TOB output port 704 is obtained as w _i = γ _k and the signal at the output port 705 is obtained as = (γ _k — s)(g ₀ ) ^-1 , as required by the step 510 of the method 500. When b _i = 1, the control logic updates the OCB constraint counter k in accordance with the step 512 of the method 500.

[0125] At the end of the ith round of computation, the signal v _i becomes the next signal at the input to the feed-forward computation circuit 710, while the contents of the registers r ₁ , r ₂ , ··· , r _m-1 are shifted one place to the right.

[0126] Following the above description, the person skilled in the art will have no difficulty in implementing the circuit 700 so that it performs as described in the method 500. The person skilled in the art will also recognize that there exist various alternative realizations of the method 500 which involve pipelining and parallelization in order to decrease the processing latency and improve throughput.

[0127] When the outer transform matrix is IUT Toeplitz, it is possible to implement the outer encoder 302 using a transpose-form of the convolution circuit 600. We will now discuss such transpose-form circuits, compare them with the direct-form circuit 600, and give alternative implementations of the outer encoder 302 based on transpose-form convolutions.

[0128] FIG. 8 is a schematic diagram of a transpose-form convolution circuit 800. The transpose-form convolution circuit 800 performs the same function as the convolution circuit 600 but may be preferable for having certain implementation advantages. The transpose-form convolution circuit 800 is configured for computing the product w(D) = v(D)g(D) mod

D ^N as in Proposition 3, wherein g(D) = g ₀ + g ₁ D + ... + g _m D ^m is fixed polynomial, v(D) = v ₁ + V ₂ D + ... + V _N D ^n-1 and w(D) = w ₁ + w ₂ D + ... + w _N D ^N-1 are an input polynomial and an output polynomial, respectively.

[0129] The transpose-form convolution circuit 800 is obtained from the convolution circuit 600 by Mason’s rule (see, e.g., page 156 of the book “A. V. Oppenheim and R. W. Schafer, Digital Signal Processing, Prentice-Hall, Englewood Cliffs, New Jersey, 1975”). The transpose-form convolution circuit 800 comprises an input port 801, an output port 802, registers 811-813, multipliers 821-825, and adders 831-834.

[0130] The transpose-form convolution circuit 800 receives the coefficients v _i of the input polynomial v(D) at the input port 801 in the natural order v ₁ (first), v ₂ , ···, v _N , and computes and sends out the coefficients w _i of the output polynomial w(D) at the output port 802 in the order w ₁ (first), w ₂ , ···, w _N . Prior to receiving the first input v ₁ , the contents of registers r ₁ ,r ₁ ,...,r _m 811-813 are initialized to 0. It takes N time units for the transpose-form convolution circuit 800 to complete its operation. The transpose-form convolution circuit 800 is capable of computing the product w(D) = g(D)v(D) mod D ^N in any field. If a coefficient gi of the fixed polynomial g(D) is zero, it is clear that the corresponding multiplier and adder circuits can be eliminated so as to simplify the circuit. A further simplification takes place when g _i = 1 (the multiplicative identity) in which case the corresponding multiplier can be eliminated. In particular, when the field of operations is the binary field, there is no need for any multipliers and the addition operations can be implemented using logic exclusive OR (XOR) gates. Details of the operation of the transpose-form convolution circuit 800 and its various implementations in digital logic are well known in the prior art. [0131] It will be clear to the person skilled in the art of digital circuit design that the direct- form convolution circuit 600 (for short, direct-form circuit 600) and the transpose-form convolution circuit 800 (for short, transpose-form circuit 800) have certain advantages and disadvantages relative to each other from an implementation viewpoint. A disadvantage of the direct-form circuit 600 is that it has a larger delay (also called latency or critical path) compared to the transpose-form circuit 800. The delay for the direct-form circuit 600 is determined by the calculation of the output 602, which takes mT _add + T _mult time units, where T _add is the delay for an adder and T _mult is the delay for a multiplier. In contrast, the delay for the transform-form circuit 800 is T _add + T _mult . Thus, the transpose-form circuit 800 may run with a higher clock frequency compared to the direct-form circuit 600, which is important for high- throughput applications. On the other hand, the person skilled in the art will recognize that it is possible to introduce pipelining to the direct-form circuit 600 and reduce its delay to T _add + T _mult by adding an extra pipeline register in tandem with each existing register. If the two circuits are compared in terms of fan-out of signals, the input 801 in the transpose-form circuit 800 has fan-out of m, while the direct-form circuit 600 does not use any signals with a fan-out larger than two. When m is large, the fan-out becomes a factor that needs to be taken into consideration. [0132] FIG. 9A is a flowchart of an IUT Toeplitz transpose-form encoder method 900 according to an embodiment of the present principles. The IUT Toeplitz transpose-form encoding method 900 (hereafter, the method 900) is configured for an IUT Toeplitz matrix with an impulse response wherein g ₀ ≠ 0 and g _m ≠ 0. The method 900 begins operations in a start step 901 and moves into an OCB input step 902 when a new becomes available for encoding. In the OCB input step 902, the method 900 fetches the OCB γ 312 from outside, e.g., from the inner encoder 301.

[0133] Following the OCB input step 902, the method 900 moves to a variable initialization step 903 and initializes a loop counter i, an FDB constraint counter j, an OCB constraint counter k, and a register array r = (r ₁ , ··· , r _m ) by setting r _i ← 0 for i = 1, ··· , m. The counters i, j, and k perform the same counting functions as in the case of the method 400. The role of the register array r is explained below.

[0134] As in the case of the method 400, the initialization and updates of the counters j and k can be simplified by removing the “min” operation in the same way as described for the method 400. Such a simplification does not affect the final values of the TIB v 314 and TOB v 315 calculated by the method 900.

[0135] Following the variable initialization step 903, the method 900 executes a loop counter increment step 904 by incrementing the loop counter i by 1. The step 904 marks the beginning of a main loop for the method 900. The main loop is executed N times each time the method 900 is invoked. During the ith execution of the main loop, the method 900 processes a feed- forward value s together with a current element a _j . of the FDB a 313 or a current element γ _k of the OCB γ 312 to a generate a next element v _i of the TIB v 314 and a next element w _i of the TOB w 315. The details of the main loop are as follows. [0136] The method 900 enters a loop coimter check step 905 following the step 904 and checks if the loop counter i is still less than or equal to its final value N. If a result of the check is NO, the method 900 moves into an exit step 906. (If a next OCB 312 is available for encoding, the exit step 906 may be bypassed and the method 900 may proceed to the encoding of the next OCB by reentering the parameter initialization step 902.)

[0137] If the result of the check in the step 905 is YES, the method 900 moves into a constraint- type check step 907 and checks if the next constraint to be processed is an FDB constraint 323 (indicated by b _i = 0) or an OCB constraint 322 (indicated by b _i = 1).

[0138] If a result of the constraint-type check step 907 is NO, then the method 900 executes an FDB processing step 908 by setting w _i = a _j g ₀ + r ₁ and v _i = a _j . The step 908 is followed by a step 910, in which the FDB constraint counter j is updated as j ← min {j + 1, N — K}. At the end of the step 910, the FDB constraint counter y points at the next FDB constraint 323 to be processed if there is any left; if all FDB constraints 323 have been processed, the value of j remains as N — K . [0139] If the result of the constraint-type check step 907 is YES, then the method 900 executes an OCB processing step 909 by setting w _i = γ _k and v _i = (γ _k - r ₁ )(g ₀ ) ^-1 · The step 909 is followed by a step 911, in which the OCB constraint counter k is updated as k ← min { k + 1 ,K}. At the end of the step 911, the OCB constraint counter k points at the next OCB constraint 322 to be processed if there is any left; if all OCB constraints 322 have been processed, the value of k remains as K.

[0140] The steps 910 and 911 are both followed by a register update step 912, in which the contents of the register array r are updated as r _h ← r _h+1 + v _i g _h in the order h = 1,2, ··· , m — 1, followed by r _m ← v _i g _m . Here, r ₁ plays the role of a feed-forward variable s.

[0141] The next step from the step 912 is an output step 913, in which the method 900 outputs the ith element w _i of the TOB w 315. Optionally, the method 500 may output the ith element v _i of the TIB v 314 as part of the output step 913.

[0142] Following the output step 913, the method 900 loops back to the step 904 and continues operating as described above.

[0143] The complexity of the method 900 is 0(mN), which is the same as the complexity of the method 500 but may be significantly smaller than the complexity 0(N ² ) of the method 400 when m is small compared to N.

[0144] It is possible to simplify the method 900 by eliminating all “min” operations as in the case of the method 400. As in the case of the method 400, another simplification takes place in the implementation of the method 900 when the diagonal elements of the IUT transform U are all 1 (the multiplicative identity in or when the transform operations are over the binary field [0145] FIG. 9B is a diagram illustrating in tabular form an exemplary calculation 950 according to the method 900. The exemplary calculation 950 uses an exemplary transform matrix U 952, an exemplary CTI b 953, an exemplary FDB a 954, and an exemplary OCB y 955. The exemplary calculation 950 is assumed to be over the binary field By inspecting the exemplary parameters b 953 and a 954, we understand that the length parameters in the exemplary calculation 950 are N = 8 and K = 3. Details of the exemplary calculation 950 are shown in a table 951. The ith row of the table 951 lists values of the variables of the method 900, where the values are sampled immediately after completion of the FDB constraint processing step 908 or the OCB constraint processing step 909. At the end of the exemplary calculation 950, an exemplary TIB v 956 and an exemplary TOB w 957 are obtained. It can be verified easily that the exemplary variables 952-957 satisfy the transform constraint w = vU 321, the FDB constraint 322 and the OCB constraint 323 with and

[0146] Note that the input parameters for the exemplary calculation 550 and the exemplary calculation 950 are the identical. As expected, both 550 and 950 produce as outputs the same TIB v 314 and the same TOB w 315.

[0147] Next, we give a hardware implementation of the method 900 based on the transpose- form convolution circuit 800.

[0148] FIG. 10 is a schematic diagram of a transpose-form IUT Toeplitz encoder circuit 1000 according to an embodiment of the present principles. The transpose-form IUT Toeplitz encoder circuit 1000 (hereafter, the circuit 1000) is an implementation of the method 900 in hardware using commonly available digital logic elements, such as adders, multipliers, random access memory, shift registers, and multiplexers. The circuit 1000 comprises an FDB input port 1001 for receiving the elements α _j of the FDB a 313, an OCB input port 1002 for receiving the elements γ _k of the OCB γ 312, a CTI input port 1003 for receiving the elements of the CTI b, a TOB output port 1004 for sending out the elements w _i of the TOB w 315, and a TIB output port 1005 for sending out the elements v _i of the TIB v 314.

[0149] The circuit 1000 further comprises a transpose-form feed-forward calculation circuit 1010, a first multiplexer MLJX1 1020, and second multiplexer MUX2 1030. The circuit 1000 follows the steps of the method 900. Certain steps in the implementation of the method 900 are not shown explicitly in the circuit 1000 in order not to clutter the circuit 1000 with unnecessary detail. In particular, clock circuitry, control logic, and storage elements for holding the FDB a 313, the OCB γ 312, and the CTI b are not shown in the circuit 1000. Logic circuits for initialization and incrementing of the counters j, k, i, which are used as memory addresses for fetching the elements β _j , γ _k , and b _i from their respective memory locations, are also not shown in the circuit 1000. The person skilled in the art of digital circuit design will have no difficulty is completing such routine details of the circuit 1000 so as to obtain a full implementation of the method 900.

[0150] The transpose-form feed-forward computation circuit 1010 is inspired by the transpose- form convolution circuit 800. The function of the transpose-form feed-forward computation circuit 1010 is to execute the step 912 of the method 900. The transpose-form feed-forward computation circuit 1010 receives elements v _i of the TIB v 314 as input and generates as the feed-forward variable s at its output. The contents of the registers inside the transpose-form feed-forward computation circuit 1010 are initialized to 0 at the start of the operation as in the step 903 of the method 900.

[0151] The multiplexers MLJX1 1020 and MUX2 1030 are regular 2-to-1 multiplexers commonly employed in digital circuits. To be specific, the 2-to-1 multiplexer employed here has two input ports INI and IN0, a control port SEL, and an output port OUT. When the signal at the control port SEL is a logical 1 (respectively, logical 0), the 2-to-1 multiplexer forwards the logic signal at the input port INI (respectively, input port IN0) to the output port OUT. [0152] The constraint-type check step 907 is implemented by connecting the CTI input port 1003 to the SEL ports 1023 and 1033 of the multiplexers MLJX1 1020 and MUX2 1030, respectively.

[0153] When b _i = 0, the first multiplexer MLJX1 1020 routes the signal α _j from the input port IN0 1021 to the output port OUT 1024 and the second multiplexer MUX2 1030 routes the signal a _j g ₀ + r ₁ from the input port IN0 1031 to the output port OUT 1034. Thus, when b _i = 0, the signal at the TOB output port 1004 is obtained as w _i = a _j g ₀ + r ₁ and the signal at the TIB output port 1005 is obtained as v _i = a _j , as required by the step 908 of the method 900. When b _i = 0, the control logic updates the FDB constraint counter j in accordance with the step 910 of the method 900. [0154] When b _i = 1, the first multiplexer MUX1 1020 routes the signal (γ _k — r ₁ )(g ₀ ) ^-1 from the input port INI 1022 to the output port OUT 1024 and the second multiplexer MUX2 1030 routes the signal γ _k from the input port INI 1032 to the output port OUT 1034. Thus, when b _i = 1, the signal at the TOB output port 1004 is obtained as w _i = γ _k and the signal at the TIB output port 1005 is obtained as v _i = (γ _k — 7ϊ)(0 _ο ) ^-1 , as required by the step 909 of the method 900. When b _i = 1, the control logic updates the OCB constraint counter k in accordance with the step 911 of the method 900.

[0155] At the end of the ith round of computation, the signal v _i becomes the next input to the transpose-form feed-forward computation circuit 1010, while the contents of the registers 7i, r ₂ , ··· , r _m _i are updated in accordance with the step 912 of the method 900. Following the above description, the person skilled in the art will have no difficulty in implementing the circuit 1000 so that it performs as described in the method 900. The person skilled in the art will also recognize various alternative realizations of the method 900 which involve pipelining and parallelization in order to decrease the processing latency and improve throughput. [0156] The embodiments of the present principles described above can be modified or extended in several ways to obtain alternative embodiments. We will list some such alternatives.

[0157] In some implementations of the outer encoder 302 it may be preferable to use dual methods. The idea of dual methods is to replace a primal set of parameters for the outer encoder 302 with a dual set of parameters In the dual method, the methods discussed above are applied to the dual case. We will state two basic results that form the foundation of the dual methods.

[0158] Proposition 4. For any N > 1, the class of all N-by-N IUT matrices forms a group under matrix multiplication; in other words, the product of two IUT matrices is an IUT matrix and the inverse of IUT matrix is an IUT matrix.

[0159] We omit the proof of Proposition 4 since it is a well-known result.

[0160] Proposition 5. The class of all N-by-N IUT Toeplitz matrices forms a group under matrix multiplication. Let U ∈ be an IUT Toeplitz matrix with first row g = (g ₀ , g ₁ , ... ,g _N-1 ) ∈ Then, U ^-1 is an IUT Toeplitz matrix with a first row h = (h ₀ , h _1, ^.. , h _N-1 ) given by the recursive formulas h ₀ = (1/g ₀ ) and Equivalently, the polynomials g(D) = g ₀ + g ₁ D + are related by g(D)] mod D ^N .

[0161] We omit the proof of Proposition 5 since it is a known result (see, e.g., D. Commenges and M. Monsion, “Fast inversion of triangular Toeplitz matrices,” IEEE Transactions on Automatic Control, vol. 29, no. 3, pp. 250-251, Mar. 1984). [0162] The following example shows that the dual Toeplitz transform may be less complex to implement in some cases.

[0163] Example. Let U ∈ be an IUT Toeplitz matrix with first row g = (1,1,1,1,0,0,0,0,1,1,0,1,1,0,1,0). By Proposition 5, the inverse U ^-1 e is the IUT Toeplitz matrix with first row h = (1,1,0,0,1,1,0,0,0,0,1,0,0,0,0,0). We observe that g(D) has degree 14 while h(D) has degree 10. Thus, implementing the circuits 700 and 1000 using the dual polynomial h(D) requires 10 shift registers compared to 14 if g(D) is used.

[0164] We leave out the details of dual methods for implementing the outer encoder 302 since the person skilled in the art will have no difficulty in implementing such methods from the above description. Next, we turn to another direction in which the present principles may be extended.

[0165] In the above embodiments of the present principles, as presented, e.g., in FIG. 3, we have assumed that the outer transform matrix is an IUT matrix and the inner transform is an ILT matrix. The person skilled in the art will readily see that the present principles can be applied to carry out systematic encoding for any code whose generator matrix G splits into a product G = AB of an outer transform A and an inner transform B where A = PUQ and B = RLS for some IUT matrix U, ILT matrix L, and permutation matrices P, Q, R, S. The person skilled in the art will be able to modify the systematic encoder 300 (and its more specific embodiments presented in FIGS. 4 A, 5 A, 7, 9 A, and 10) to implement a systematic encoder based on the modified triangular factorization G = AB. [0166] Another extension of the present principles is the following. In the above treatment of systematic encoding of TF codes, we have assumed that the various transforms under consideration are represented by square matrices. The present principles can be extended to the case where systematic encoding is desired for a code with a generator matrix where the generator matrix is specified as a non-square matrix. In such a case, the non-square generator matrix may be augmented by extra rows or columns to turn it into a square matrix and a triangular factorization of the resulting square matrix can be used in connection with the present principles to obtain a systematic encoder for the code. All such embodiments that explicitly or implicitly use the present principles fall within the scope of the present principles.

[0167] Finally, we note that the present principles can be readily used for code shortening. Shortening is a method of providing flexibility with respect to the length of a code. Several code families have some natural code lengths dictated by the way the code is constructed. The natural code lengths for a given code may not suit the special requirements of particular applications, in which case it is desirable to have a method for adjusting the code lengths. In shortening, a portion of the TCB is set equal to a fixed shortening block (FSB), where the FSB is a fixed pattern of symbols (usually, a pattern of all-zeros). The TCB is shortened by not sending the FSB over the transmission channel. When shortening is applied, it is common practice to ensure that the decoder in the system knows the FSB so that it can restore the missing part of the TCB before starting the decoding task.

[0168] For joint shortening and systematic encoding of TF codes, the present principles can be applied by embedding the FSB into the SDB. If shortening is desired with non-systematic encoding of TF codes, then the SDB may be embedded into the FDB and systematic encoding according to the present principles can be carried out with the FSB embedded into the TCB (as if it were the SDB).

[0169] This completes our description of various embodiments of the present principles. We now turn to some examples of communication systems within which the present principles may be used.

[0170] FIG. 11 illustrates an example wireless network within which data encoding in error correction coding using triangular transforms may be implemented according to this disclosure. The embodiment of the wireless network 1100 shown in FIG. 11 is for illustration only. Other embodiments of the wireless network 1100 could be used without departing from the scope of this disclosure. The wireless network 1100 includes an eNodeB (eNB) 1101, an eNB 1102, and an eNB 1103. The eNB 1101 communicates with the eNB 1102 and the eNB 1103. The eNB 1101 also communicates with at least one Internet Protocol (IP) network 1130, such as the Internet, a proprietary IP network, or other data network.

[0171] Depending on the network type, other well-known terms may be used instead of “eNodeB” or “eNB,” such as “base station” or “access point.” For the sake of convenience, the terms “eNodeB” and “eNB” are used in this patent document to refer to network infrastructure components that provide wireless access to remote terminals. Also, depending on the network type, other well-known terms may be used instead of “user equipment” or “UE,” such as “mobile station” (or “MS”), “subscriber station” (or “SS”), “remote terminal,” “wireless terminal,” or “user device.” For the sake of convenience, the terms “user equipment” and “UE” are used in this patent document to refer to remote wireless equipment that wirelessly accesses an eNB, whether the UE is a mobile device (such as a mobile telephone or smartphone) or is normally considered a stationary device (such as a desktop computer or vending machine). [0172] The eNB 1102 provides wireless broadband access to the network 1130 for a first plurality of user equipments (UEs) within a coverage area 1120 of the eNB 1102. The first plurality of UEs includes a UE 1111, which may be located in a small business (SB); a UE 1112, which may be located in an enterprise (E); a UE 1113, which may be located in a WiFi hotspot (HS); a UE 1114, which may be located in a first residence (R1); a UE 1115, which may be located in a second residence (R2); and a UE 1116, which may be a mobile device (M) like a cell phone, a wireless laptop, a wireless personal digital assistant (PDA), tablet, or the like. The eNB 1103 provides wireless broadband access to the network 1130 for a second plurality of UEs within a coverage area 1125 of the eNB 1103. The second plurality of UEs includes the UE 1115 and the UE 1116. In some embodiments, one or more of the eNBs 1101- 1103 may communicate with each other and with the UEs 1111-1116 using 3G, 4G or 5G, long-term evolution (LTE), LTE-A, WiMAX, or other advanced wireless communication techniques.

[0173] Dotted lines show the approximate extents of the coverage areas 1120 and 1125, which are shown as approximately circular for the purposes of illustration and explanation only. It should be clearly understood that the coverage areas associated with eNBs, such as the coverage areas 1120 and 1125, may have other shapes, including irregular shapes, depending upon the configuration of the eNBs and variations in the radio environment associated with natural and man-made obstructions. [0174] As described in more detail below, one or more of eNB 1101, eNB 1102 and eNB 1103 include 2D antenna arrays as described in embodiments of the present disclosure. In some embodiments, one or more of eNB 1101, eNB 1102 and eNB 1103 support the codebook design and structure for systems having 2D antenna arrays.

[0175] Although FIG. 11 illustrates one example of a wireless network 1100, various changes may be made to FIG. 11. For example, the wireless network 1100 could include any number of eNBs and any number of UEs in any suitable arrangement. Also, the eNB 1101 could communicate directly with any number of UEs and provide those UEs with wireless broadband access to the network 1130. Similarly, each eNB 1102-1103 could communicate directly with the network 1130 and provide UEs with direct wireless broadband access to the network 1130. Further, the eNB 1101, 1102, and/or 1103 could provide access to other or additional external networks, such as external telephone networks or other types of data networks.

[0176] The example channel decoding systems depicted in the figures and described above may be implemented in an eNB (such as eNB 1102) and/or a UE (such as UE 1116), as described in further detail below.

[0177] FIG. 12A illustrates an example user equipment network within which data encoding in error correction coding using triangular transforms may be implemented according to this disclosure. The embodiment of the UE 1116 illustrated in FIG. 12A is for illustration only, and the UEs 1111-1115 of FIG. 11 could have the same or similar configuration. However, UEs come in a wide variety of configurations, and FIG. 12A does not limit the scope of this disclosure to any particular implementation of a UE.

[0178] The UE 1116 includes an antenna 1205, a radio frequency (RF) transceiver 1210, transmit (TX) processing circuitry 1215 (which may include the encoder 110 in FIG. 1), a microphone 1220, and receive (RX) processing circuitry 1225 (which may include the decoder

130 in FIG. 1). The UE 1116 also includes a speaker 1230, a main processor 1240, an input/output (I/O) interface (IF) 1245, a keypad 1250, a display 1255, and a memory 1260. The memory 1260 includes a basic operating system (OS) program 1261 and one or more applications 1262. Either the OS program 1261, one of the applications 1262, or some combination thereof may implement programming for employing error correction coding as described in the various embodiments of FIGS. 1 through 10.

[0179] The RF transceiver 1210 receives, from the antenna 1205, an incoming RF signal transmitted by an eNB of the network 1100. The RF transceiver 1210 may down-convert the incoming RF signal to generate an intermediate frequency (IF) or baseband signal which would be sent to the receiver (Rx) processing circuitry 1225. The Rx processing circuitry 1225 transmits the processed signal to the speaker 1230 (such as for voice data) or to the main processor 1240 for further processing (such as for web browsing data).

[0180] The transmit (Tx) processing circuitry 1215 receives, as at least some input data for the source data block, analog or digital voice data from the microphone 1220 or other outgoing baseband data (such as web data, e-mail, or interactive video game data) from the main processor 1240. The Tx processing circuitry 1215 implements encoding. The RF transceiver 1210 receives the outgoing processed baseband or IF signal from the Tx processing circuitry 1215 and up-converts the baseband or IF signal to an RF signal that is transmitted via the antenna 1205.

[0181] The main processor 1240 can include one or more processors or other processing devices and execute the basic OS program 1261 stored in the memory 1260 in order to control the overall operation of the UE 1116. For example, the main processor 1240 could control the reception of forward channel signals and the transmission of reverse channel signals by the RF transceiver 1210, the Rx processing circuitry 1225, and the Tx processing circuitry 1215 in accordance with well-known principles. In some embodiments, the main processor 1240 includes at least one programmable microprocessor or microcontroller, while in other embodiments the main processor includes dedicated circuitry (e.g., for systematic and/or non- systematic encoding or decoding processes, shortening processes, data mapping, etc.) as well as (optionally) programmable logic or processing circuits.

[0182] The main processor 1240 is also capable of executing other processes and programs resident in the memory 1260, such as operations for channel quality measurement and reporting for systems having 2D antenna arrays. The main processor 1240 can move data and/or instructions into or out of the memory 1260 as required by an executing process. In some embodiments, the main processor 1240 is configured to execute the applications 1262 based on the OS program 1261 or in response to signals received from eNBs or an operator. The main processor 1240 is also coupled to the VO interface 1245, which provides the UE 1116 with the ability to connect to other devices such as laptop computers and handheld computers. The VO interface 1245 is the communication path between these accessories and the main controller 1240.

[0183] The main processor 1240 is also coupled to the keypad 1250 (which may simply be a single button or may be an array or other set of buttons) and the display unit 1255. The operator of the UE 1116 can use the keypad 1250 to enter data into the UE 1116. The display 1255 may be a touch screen display or other display capable of rendering text and/or at least limited graphics, such as from web sites, and receiving touch inputs by a user in accordance with known practices.

[0184] The memory 1260 is coupled to the main processor 1240, and at least a part of the memory 1260 could include a random access memory (RAM), and another part of the memory 1260 could include a Flash memory or other read-only memory (ROM).

[0185] Although FIG. 12A illustrates one example of UE 1116, various changes may be made to FIG. 12A. For example, various components in FIG. 12A could be combined, further subdivided, or omitted and additional components could be added according to particular needs. As a particular example, the main processor 1240 could be divided into multiple processors, such as one or more central processing units (CPUs), one or more application specific integrated circuits (ASICs), one or more field programmable gate arrays (FPGAs), and one or more graphics processing units (GPUs). Also, while FIG. 12A illustrates the UE 1116 configured as a mobile telephone or smartphone, UEs could be configured to operate as other types of mobile or stationary devices.

[0186] FIG. 12B illustrates an example enhanced NodeB (eNB) network within which data encoding in error correction coding using triangular transforms may be implemented according to this disclosure. The embodiment of the eNB 1102 shown in FIG. 12B is for illustration only, and other eNBs of FIG. 11 could have the same or similar configuration. However, eNBs come in a wide variety of configurations, and FIG. 12B does not limit the scope of this disclosure to any particular implementation of an eNB. It is noted that eNB 1101 and eNB 1103 can include the same or similar structure as eNB 1102.

[0187] As shown in FIG. 12B, the eNB 1102 includes multiple antennas 1270a-1270n, multiple RF transceivers 1272a-1272n, transmit (Tx) processing circuitry 1274, and receive (Rx) processing circuitry 1276. In certain embodiments, one or more of the multiple antennas 1270a- 1270n include 2D antenna arrays. The eNB 1102 also includes a controller/processor 1278, a memory 1280, and a backhaul or network interface 1282.

[0188] The RF transceivers 1272a-1272n receive, from the antennas 1270a-1270n, incoming RF signals, such as signals transmitted by UEs or other eNBs. The RF transceivers 1272a- 1272n down-convert the incoming RF signals to generate IF or baseband signals. The IF or baseband signals are sent to the Rx processing circuitry 1276, which generates processed signals by filtering, decoding, and/or digitizing the baseband or IF signals. The Rx processing circuitry 1276 transmits the processed signals to the controller/ processor 1278 for further processing.

[0189] The Tx processing circuitry 1274 receives, as at least some input data for source data blocks, analog or digital data (such as voice data, web data, e-mail, or interactive video game data) from the controller/processor 1278. The Tx processing circuitry 1274 implements circuits to encode, multiplex, and/or digitize the outgoing baseband data to generate processed signals. The RF transceivers 1272a-1272n receive the outgoing processed signals from the Tx processing circuitry 1274 and up-converts the baseband or IF signals to RF signals that are transmitted via the antennas 1270a-1270n.

[0190] The controller/processor 1278 can include one or more processors or other processing devices that control the overall operation of the eNB 1102. For example, the controller/processor 1278 could control the reception of forward channel signals and the transmission of reverse channel signals by the RF transceivers 1272a-1272n, the Rx processing circuitry 1276, and the Tx processing circuitry 1274 in accordance with well-known principles. The controller/processor 1278 could support additional functions as well, such as more advanced wireless communication functions. Any of a wide variety of other functions could be supported in the eNB 1102 by the controller/processor 1278. In some embodiments, the controller/ processor 1278 includes at least one microprocessor or microcontroller, while in other embodiments the main processor includes dedicated circuitry (e.g., for systematic and/or non-systematic encoding processes, shortening processes, data mapping, etc.) as well as (optionally) programmable logic or processing circuits.

[0191] The controller/processor 1278 is also capable of executing programs and other processes resident in the memory 1280, such as a basic OS. The controller/processor 1278 is also capable of supporting channel quality measurement and reporting for systems having 2D antenna arrays. In some embodiments, the controller/processor 1278 supports communications between entities. The controller/processor 1278 can move data and/or instructions into or out of the memory 1280 as required by an executing process.

[0192] The controller/processor 1278 is also coupled to the backhaul or network interface 1282. The backhaul or network interface 1282 allows the eNB 1102 to communicate with other devices or systems over a backhaul connection or over a network. The interface 1282 could support communications over any suitable wired or wireless connect! on(s). For example, when the eNB 1102 is implemented as part of a cellular communication system (such as one supporting 3G, 4G, 5G, LTE, or LTE-A), the interface 1282 could allow the eNB 1102 to communicate with other eNBs over a wired or wireless backhaul connection. When the eNB 1102 is implemented as an access point, the interface 1282 could allow the eNB 1102 to communicate over a wired or wireless local area network or over a wired or wireless connection to a larger network (such as the Internet). The interface 1282 includes any suitable structure supporting communications over a wired or wireless connection, such as an Ethernet or RF transceiver. [0193] The memory 1280 is coupled to the controller/processor 1278. Part of the memory 1280 could include a RAM, and another part of the memory 1280 could include a Flash memory or other ROM. In certain embodiments, a plurality of instructions is stored in memory. The instructions are configured to cause the controller/processor 1278 to perform the systematic and/or non-systematic encoding or decoding processes, shortening processes, data mapping, etc.

[0194] Although FIG. 12B illustrates one example of an eNB 1102, various changes may be made to FIG. 12B. For example, the eNB 1102 could include any number of each component shown. As a particular example, an access point could include a number of interfaces 1282, and the controller/processor 1278 could support routing functions to route data between different network addresses. As another particular example, while shown as including a single instance of Tx processing circuitry 1274 and a single instance of Rx processing circuitry 1276, the eNB 1102 could include multiple instances of each (such as one per RF transceiver). [0195] While particular embodiments of METHODS AND APPARATUS FOR

SYSTEMATIC ENCODING OF DATA IN ERROR CORRECTION CODING USING TRIANGULAR FACTORIZATION OF GENERATOR MATRIX are herein described in detail and depicted in the drawings, it is to be understood that the subject matter which is encompassed by the present disclosure is limited only by the claims. Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications that fall within the scope of the appended claims. The description in the present application should not be read as implying that any particular element, step, or function is an essential or critical element which must be included in the claim scope: the scope of patented subj ect matter is defined only by the allowed claims. Moreover, none of these claims are intended to invoke 35 USC § 112(f) with respect to any of the appended claims or claim elements unless the exact words “means for” or “step for” are explicitly used in the particular claim, followed by a participle phrase identifying a function. Use of terms such as (but not limited to) “mechanism,” “module,” “device,” “unit,” “component,” “element,” “member,” “apparatus,” “machine,” “system,” “processor,” or “controller” within a claim is understood and intended to refer to structures known to those skilled in the relevant art, as further modified or enhanced by the features of the claims themselves, and is not intended to invoke 35 U.S.C. § 112(f).